ATA: get rid of x86_ata
We'll be using our own implementation.
This commit is contained in:
parent
a75279df1f
commit
5d1b4ed55d
13
Cargo.lock
generated
13
Cargo.lock
generated
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@ -65,7 +65,6 @@ dependencies = [
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"wasmi",
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"watson",
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"x86_64",
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"x86_ata",
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"y-compositor-protocol",
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]
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@ -879,18 +878,6 @@ dependencies = [
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"volatile 0.4.5",
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]
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[[package]]
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name = "x86_ata"
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version = "0.1.0"
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dependencies = [
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"bit_field",
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"lazy_static",
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"log",
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"serde",
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"spin 0.9.4",
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"x86_64",
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]
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[[package]]
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name = "y-compositor-protocol"
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version = "0.1.1"
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@ -148,7 +148,6 @@ git = "https://git.ablecorp.us:443/able/externc-libm.git"
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riscv = "*"
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[target.'cfg(target_arch = "x86_64")'.dependencies]
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x86_ata = { path = "../x86_ata" }
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bootloader = { version = "0.9.8", features = ["map_physical_memory"] }
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cpuio = { git = "https://git.ablecorp.us/ondra05/cpuio.git" }
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pic8259 = "0.10.1"
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@ -1,25 +0,0 @@
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[package]
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name = "x86_ata"
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version = "0.1.0"
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edition = "2021"
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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[dependencies]
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log = "*"
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[dependencies.bit_field]
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version = "0.10.0"
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[dependencies.lazy_static]
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features = ["spin_no_std"]
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version = "1.4.0"
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[dependencies.serde]
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default-features = false
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version = "1.0.126"
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[dependencies.spin]
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version = "0.9.0"
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[dependencies.x86_64]
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version = "0.14.3"
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@ -1,380 +0,0 @@
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#![no_std]
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/// Implementation Courtesy of MOROS.
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/// Currently Only Supports ATA-PIO, with 24-bit LBA Addressing.
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extern crate alloc;
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use alloc::string::String;
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use alloc::vec::Vec;
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use bit_field::BitField;
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use core::hint::spin_loop;
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use lazy_static::lazy_static;
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use log::trace;
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use spin::Mutex;
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use x86_64::instructions::port::{Port, PortReadOnly, PortWriteOnly};
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pub type BlockIndex = u32;
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pub const ATA_BLOCK_SIZE: usize = 512;
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fn sleep_ticks(ticks: usize) {
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for _ in 0..=ticks {
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x86_64::instructions::hlt();
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}
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}
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#[repr(u16)]
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enum Command {
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Read = 0x20,
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Write = 0x30,
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Identify = 0xEC,
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}
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#[allow(dead_code)]
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#[repr(usize)]
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enum Status {
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ERR = 0,
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IDX = 1,
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CORR = 2,
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DRQ = 3,
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SRV = 4,
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DF = 5,
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RDY = 6,
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BSY = 7,
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}
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#[allow(dead_code)]
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#[derive(Debug, Clone)]
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pub struct Bus {
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id: u8,
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irq: u8,
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data_register: Port<u16>,
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error_register: PortReadOnly<u8>,
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features_register: PortWriteOnly<u8>,
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sector_count_register: Port<u8>,
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lba0_register: Port<u8>,
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lba1_register: Port<u8>,
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lba2_register: Port<u8>,
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drive_register: Port<u8>,
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status_register: PortReadOnly<u8>,
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command_register: PortWriteOnly<u8>,
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alternate_status_register: PortReadOnly<u8>,
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control_register: PortWriteOnly<u8>,
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drive_blockess_register: PortReadOnly<u8>,
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}
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impl Bus {
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pub fn new(id: u8, io_base: u16, ctrl_base: u16, irq: u8) -> Self {
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Self {
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id,
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irq,
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data_register: Port::new(io_base),
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error_register: PortReadOnly::new(io_base + 1),
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features_register: PortWriteOnly::new(io_base + 1),
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sector_count_register: Port::new(io_base + 2),
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lba0_register: Port::new(io_base + 3),
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lba1_register: Port::new(io_base + 4),
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lba2_register: Port::new(io_base + 5),
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drive_register: Port::new(io_base + 6),
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status_register: PortReadOnly::new(io_base + 7),
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command_register: PortWriteOnly::new(io_base + 7),
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alternate_status_register: PortReadOnly::new(ctrl_base),
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control_register: PortWriteOnly::new(ctrl_base),
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drive_blockess_register: PortReadOnly::new(ctrl_base + 1),
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}
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}
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fn reset(&mut self) {
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unsafe {
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self.control_register.write(4); // Set SRST bit
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sleep_ticks(2);
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self.control_register.write(0); // Then clear it
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sleep_ticks(2);
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}
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}
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fn wait(&mut self) {
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for _ in 0..4 {
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// Wait about 4 x 100 ns
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unsafe {
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self.alternate_status_register.read();
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}
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}
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}
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fn write_command(&mut self, cmd: Command) {
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unsafe {
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self.command_register.write(cmd as u8);
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}
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}
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fn status(&mut self) -> u8 {
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unsafe { self.status_register.read() }
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}
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fn lba1(&mut self) -> u8 {
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unsafe { self.lba1_register.read() }
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}
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fn lba2(&mut self) -> u8 {
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unsafe { self.lba2_register.read() }
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}
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fn read_data(&mut self) -> u16 {
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unsafe { self.data_register.read() }
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}
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fn write_data(&mut self, data: u16) {
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unsafe { self.data_register.write(data) }
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}
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fn busy_loop(&mut self) {
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self.wait();
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let start = 0;
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while self.is_busy() {
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if 0 - start > 1 {
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// Hanged
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return self.reset();
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}
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spin_loop();
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}
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}
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fn is_busy(&mut self) -> bool {
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self.status().get_bit(Status::BSY as usize)
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}
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fn is_error(&mut self) -> bool {
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self.status().get_bit(Status::ERR as usize)
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}
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fn is_ready(&mut self) -> bool {
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self.status().get_bit(Status::RDY as usize)
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}
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fn select_drive(&mut self, drive: u8) {
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// Drive #0 (primary) = 0xA0
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// Drive #1 (secondary) = 0xB0
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let drive_id = 0xA0 | (drive << 4);
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unsafe {
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self.drive_register.write(drive_id);
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}
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}
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fn setup(&mut self, drive: u8, block: u32) {
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let drive_id = 0xE0 | (drive << 4);
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unsafe {
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self.drive_register
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.write(drive_id | ((block.get_bits(24..28) as u8) & 0x0F));
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self.sector_count_register.write(1);
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self.lba0_register.write(block.get_bits(0..8) as u8);
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self.lba1_register.write(block.get_bits(8..16) as u8);
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self.lba2_register.write(block.get_bits(16..24) as u8);
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}
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}
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pub fn identify_drive(&mut self, drive: u8) -> Option<[u16; 256]> {
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self.reset();
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self.wait();
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self.select_drive(drive);
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unsafe {
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self.sector_count_register.write(0);
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self.lba0_register.write(0);
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self.lba1_register.write(0);
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self.lba2_register.write(0);
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}
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self.write_command(Command::Identify);
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if self.status() == 0 {
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return None;
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}
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self.busy_loop();
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if self.lba1() != 0 || self.lba2() != 0 {
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return None;
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}
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for i in 0.. {
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if i == 256 {
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self.reset();
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return None;
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}
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if self.is_error() {
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return None;
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}
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if self.is_ready() {
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break;
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}
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}
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let mut res = [0; 256];
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for i in 0..256 {
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res[i] = self.read_data();
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}
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Some(res)
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}
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/// Read A single, 512-byte long slice from a given block
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/// panics if buf isn't EXACTLY 512 Bytes long;
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/// Example:
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/// ```rust
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/// // Read A Single block from a disk
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/// pub fn read_single() {
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/// use x86_ata::{init, ATA_BLOCK_SIZE, read};
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/// // 1. Initialise ATA Subsystem. (Perform Once, on boot)
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/// init().expect("Failed To Start ATA...");
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/// // 2. Create a temporary buffer of size 512.
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/// let mut buffer: [u8;ATA_BLOCK_SIZE] = [0; ATA_BLOCK_SIZE];
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/// // 3. Pass the buffer over to the Subsystem, to be filled.
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/// read(0, 0, 0, &mut buffer);
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/// }
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pub fn read(&mut self, drive: u8, block: BlockIndex, buf: &mut [u8]) {
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assert!(buf.len() == 512);
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trace!("Reading Block 0x{:8X}", block);
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// trace!("{:?}", self);
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self.setup(drive, block);
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self.write_command(Command::Read);
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self.busy_loop();
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for i in (0..256).step_by(2) {
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let data = self.read_data();
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//log!("Read[{:08X}][{:02X}]: 0x{:04X}\n", block, i, data);
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buf[i] = data.get_bits(0..8) as u8;
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buf[i + 1] = data.get_bits(8..16) as u8;
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}
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}
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/// Write A single, 512-byte long slice to a given block
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/// panics if buf isn't EXACTLY 512 Bytes long;
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/// Example:
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/// ```rust
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/// // Read A Single block from a disk
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/// pub fn write_single() {
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/// use x86_ata::{init, ATA_BLOCK_SIZE, write};
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/// // 1. Initialise ATA Subsystem. (Perform Once, on boot)
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/// init().expect("Failed To Start ATA...");
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/// // 2. Create a temporary buffer of size 512.
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/// let buffer: [u8;ATA_BLOCK_SIZE] = [0; ATA_BLOCK_SIZE];
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/// // 3. Pass the buffer over to the Subsystem, to be filled.
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/// write(0, 0, 0, &buffer);
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/// }
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pub fn write(&mut self, drive: u8, block: BlockIndex, buf: &[u8]) {
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assert!(buf.len() == 512);
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self.setup(drive, block);
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self.write_command(Command::Write);
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self.busy_loop();
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for i in 0..256 {
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let mut data = 0_u16;
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data.set_bits(0..8, buf[i * 2] as u16);
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data.set_bits(8..16, buf[i * 2 + 1] as u16);
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//log!("Data: 0x{:04X} | {}{} \n", data, buf[i * 2] as char, buf[i * 2 + 1] as char);
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self.write_data(data);
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}
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self.busy_loop();
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}
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}
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lazy_static! {
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pub static ref BUSES: Mutex<Vec<Bus>> = Mutex::new(Vec::new());
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}
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fn disk_size(sectors: u32) -> (u32, String) {
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let bytes = sectors * 512;
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if bytes >> 20 < 1000 {
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(bytes >> 20, String::from("MB"))
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} else {
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(bytes >> 30, String::from("GB"))
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}
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}
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pub fn list() -> Vec<(u8, u8, String, String, u32, String, u32)> {
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let mut buses = BUSES.lock();
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let mut res = Vec::new();
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for bus in 0..2 {
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for drive in 0..2 {
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if let Some(buf) = buses[bus as usize].identify_drive(drive) {
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let mut serial = String::new();
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for i in 10..20 {
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for &b in &buf[i].to_be_bytes() {
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serial.push(b as char);
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}
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}
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serial = serial.trim().into();
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let mut model = String::new();
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for i in 27..47 {
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for &b in &buf[i].to_be_bytes() {
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model.push(b as char);
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}
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}
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model = model.trim().into();
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let sectors = (buf[61] as u32) << 16 | (buf[60] as u32);
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let (size, unit) = disk_size(sectors);
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res.push((bus, drive, model, serial, size, unit, sectors));
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}
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}
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}
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res
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}
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/// Identify a specific drive on a bus, format: (bus, drive, model, serial. size, unit, sectors)
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pub fn indentify_drive(bus: u8, drive: u8) -> Option<(u8, u8, String, String, u32, String, u32)> {
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let mut buses = BUSES.lock();
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if let Some(buf) = buses[bus as usize].identify_drive(drive) {
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let mut serial = String::new();
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for i in 10..20 {
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for &b in &buf[i].to_be_bytes() {
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serial.push(b as char);
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}
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}
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serial = serial.trim().into();
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let mut model = String::new();
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for i in 27..47 {
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for &b in &buf[i].to_be_bytes() {
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model.push(b as char);
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}
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}
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model = model.trim().into();
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let sectors = (buf[61] as u32) << 16 | (buf[60] as u32);
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let (size, unit) = disk_size(sectors);
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Some((bus, drive, model, serial, size, unit, sectors))
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} else {
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None
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}
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}
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pub fn read(bus: u8, drive: u8, block: BlockIndex, buf: &mut [u8]) {
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let mut buses = BUSES.lock();
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trace!("Reading Block 0x{:08X}\n", block);
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buses[bus as usize].read(drive, block, buf);
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}
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pub fn write(bus: u8, drive: u8, block: BlockIndex, buf: &[u8]) {
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let mut buses = BUSES.lock();
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//log!("Writing Block 0x{:08X}\n", block);
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buses[bus as usize].write(drive, block, buf);
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}
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pub fn drive_is_present(bus: usize) -> bool {
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unsafe { BUSES.lock()[bus].status_register.read() != 0xFF }
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}
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pub fn init() -> Result<(), ()> {
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{
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let mut buses = BUSES.lock();
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buses.push(Bus::new(0, 0x1F0, 0x3F6, 14));
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buses.push(Bus::new(1, 0x170, 0x376, 15));
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}
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Ok(())
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}
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