Formatting, LF and RISC-V kmain
This commit is contained in:
ondra05
parent
e3ce700295
commit
cef19a8fe4
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@ -1,268 +1,268 @@
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use core::num;
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use alloc::boxed::Box;
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use spin::{Mutex, Once};
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use crate::memory::{MemoryManager, PhysicalAddress, VirtualAddress};
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use super::PAGE_SIZE;
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pub enum PageSize {
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Size4KiB,
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Size2MiB,
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Size1GiB,
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// FIXME: SV48 support
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// Size512GiB,
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// FIXME: SV57 support
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// Size256TiB,
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}
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impl PageSize {
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fn level(&self) -> usize {
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match self {
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PageSize::Size4KiB => 0,
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PageSize::Size2MiB => 1,
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PageSize::Size1GiB => 2,
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// FIXME: SV48 and SV57 support
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}
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}
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}
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pub struct PageTable {
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entries: [PageEntry; 512]
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}
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impl PageTable {
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/// Walk the page table to convert a virtual address to a physical address.
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/// If a page fault would occur, this returns None. Otherwise, it returns the physical address.
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pub fn virt_to_phys(&self, vaddr: VirtualAddress) -> Option<PhysicalAddress> {
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let vpn = vaddr.vpns();
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let mut v = &self.entries[vpn[2]];
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for i in (0..=2).rev() {
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if v.is_invalid() {
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// This is an invalid entry, page fault.
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break;
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} else if v.is_leaf() {
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// In RISC-V, a leaf can be at any level.
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// The offset mask masks off the PPN. Each PPN is 9 bits and they start at bit #12.
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// So, our formula 12 + i * 9
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let off_mask = (1 << (12 + i * 9)) - 1;
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let vaddr_pgoff = vaddr.as_addr() & off_mask;
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let addr = ((v.entry() << 2) as usize) & !off_mask;
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return Some((addr | vaddr_pgoff).into());
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}
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// Set v to the next entry which is pointed to by this entry.
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// However, the address was shifted right by 2 places when stored in the page table
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// entry, so we shift it left to get it back into place.
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let entry = v.addr().as_ptr::<PageEntry>();
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// We do i - 1 here, however we should get None or Some() above
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// before we do 0 - 1 = -1.
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v = unsafe { entry.add(vpn[i - 1]).as_ref().unwrap() };
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}
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// If we get here, we've exhausted all valid tables and haven't
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// found a leaf.
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None
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}
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/// Maps a virtual address to a physical address
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/// flags should contain only the following:
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/// Read, Write, Execute, User, and/or Global
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/// flags MUST include one or more of the following:
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/// Read, Write, Execute
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/// The valid bit automatically gets added
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pub fn map(&mut self, vaddr: VirtualAddress, paddr: PhysicalAddress, flags: PageEntryFlags, page_size: PageSize) {
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assert!(flags as usize & 0xe != 0);
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let vpn = vaddr.vpns();
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let ppn = paddr.ppns();
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let level = page_size.level();
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let mut v = &mut self.entries[vpn[2]];
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// Now, we're going to traverse the page table and set the bits properly. We expect the root
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// to be valid, however we're required to create anything beyond the root
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for i in (level..2).rev() {
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if v.is_invalid() {
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let mut mm = MEMORY_MANAGER.get().unwrap().lock();
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let page = mm.zallocate_pages(1).unwrap().as_addr();
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v.set_entry((page as usize >> 2) | PageEntryFlags::Valid as usize);
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}
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let entry = v.addr().as_mut_ptr::<PageEntry>();
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v = unsafe { entry.add(vpn[i]).as_mut().unwrap() };
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}
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// When we get here, we should be at VPN[0] and v should be pointing to our entry.
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// The entry structure is Figure 4.18 in the RISC-V Privileged Specification
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let entry = (ppn[2] << 28) as usize // PPN[2] = [53:28]
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| (ppn[1] << 19) as usize // PPN[1] = [27:19]
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| (ppn[0] << 10) as usize // PPN[0] = [18:10]
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| flags as usize // Specified bits, such as User, Read, Write, etc.
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| PageEntryFlags::Valid as usize;
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v.set_entry(entry);
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}
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/// Identity maps a page of memory
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pub fn identity_map(&mut self, addr: PhysicalAddress, flags: PageEntryFlags, page_size: PageSize) {
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// log::debug!("identity mapped {addr}");
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self.map(addr.as_addr().into(), addr, flags, page_size);
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}
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/// Identity maps a range of contiguous memory
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/// This assumes that start <= end
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pub fn identity_map_range(&mut self, start: PhysicalAddress, end: PhysicalAddress, flags: PageEntryFlags) {
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log::debug!("start: {start}, end: {end}");
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let mut mem_addr = start.as_addr() & !(PAGE_SIZE - 1);
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let num_pages = (align_val(end.as_addr(), 12) - mem_addr - 1) / PAGE_SIZE + 1;
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for _ in 0..num_pages {
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// FIXME: we can merge these page entries if possible into Size2MiB or larger entries
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self.identity_map(mem_addr.into(), flags, PageSize::Size4KiB);
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mem_addr += 1 << 12;
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}
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}
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/// Unmaps a page of memory at vaddr
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pub fn unmap(&mut self, vaddr: VirtualAddress) {
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let vpn = vaddr.vpns();
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// Now, we're going to traverse the page table and clear the bits
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let mut v = &mut self.entries[vpn[2]];
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for i in (0..2).rev() {
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if v.is_invalid() {
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// This is an invalid entry, page is already unmapped
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return;
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} else if v.is_leaf() {
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// This is a leaf, which can be at any level
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// In order to make this page unmapped, we need to clear the entry
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v.set_entry(0);
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return;
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}
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let entry = v.addr().as_mut_ptr::<PageEntry>();
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v = unsafe { entry.add(vpn[i]).as_mut().unwrap() };
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}
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// If we're here this is an unmapped page
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return;
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}
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/// Unmaps a range of contiguous memory
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/// This assumes that start <= end
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pub fn unmap_range(&mut self, start: VirtualAddress, end: VirtualAddress) {
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let mut mem_addr = start.as_addr() & !(PAGE_SIZE - 1);
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let num_pages = (align_val(end.as_addr(), 12) - mem_addr) / PAGE_SIZE;
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for _ in 0..num_pages {
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self.unmap(mem_addr.into());
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mem_addr += 1 << 12;
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}
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}
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/// Frees all memory associated with a table.
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/// NOTE: This does NOT free the table directly. This must be freed manually.
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fn destroy(&mut self) {
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for entry in &mut self.entries {
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entry.destroy()
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}
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}
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}
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#[repr(usize)]
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#[derive(Clone, Copy, Debug)]
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pub enum PageEntryFlags {
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None = 0,
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Valid = 1,
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Read = 1 << 1,
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Write = 1 << 2,
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Execute = 1 << 3,
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User = 1 << 4,
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Global = 1 << 5,
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Access = 1 << 6,
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Dirty = 1 << 7,
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// for convenience
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ReadWrite = Self::Read as usize | Self::Write as usize,
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ReadExecute = Self::Read as usize | Self::Execute as usize,
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ReadWriteExecute = Self::Read as usize | Self::Write as usize | Self::Execute as usize,
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UserReadWrite = Self::User as usize | Self::ReadWrite as usize,
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UserReadExecute = Self::User as usize | Self::ReadExecute as usize,
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UserReadWriteExecute = Self::User as usize | Self::ReadWriteExecute as usize,
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}
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struct PageEntry(usize);
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impl PageEntry {
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fn is_valid(&self) -> bool {
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self.0 & PageEntryFlags::Valid as usize != 0
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}
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fn is_invalid(&self) -> bool {
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!self.is_valid()
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}
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fn is_leaf(&self) -> bool {
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self.0 & PageEntryFlags::ReadWriteExecute as usize != 0
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}
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fn is_branch(&self) -> bool {
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!self.is_leaf()
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}
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fn entry(&self) -> usize {
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self.0
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}
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fn set_entry(&mut self, entry: usize) {
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self.0 = entry;
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}
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fn clear_flag(&mut self, flag: PageEntryFlags) {
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self.0 &= !(flag as usize);
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}
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fn set_flag(&mut self, flag: PageEntryFlags) {
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self.0 |= flag as usize;
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}
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fn addr(&self) -> PhysicalAddress {
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((self.entry() as usize & !0x3ff) << 2).into()
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}
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fn destroy(&mut self) {
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if self.is_valid() && self.is_branch() {
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// This is a valid entry so drill down and free
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let memaddr = self.addr();
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let table = memaddr.as_mut_ptr::<PageTable>();
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unsafe {
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(*table).destroy();
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let mut mm = MEMORY_MANAGER.get().unwrap().lock();
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mm.deallocate_pages(memaddr.into(), 0);
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}
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}
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}
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}
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// FIXME: PageTable should be integrated into MemoryManager *somehow*
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pub static MEMORY_MANAGER: Once<Mutex<MemoryManager>> = Once::new();
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pub static PAGE_TABLE: Once<Mutex<PhysicalAddress>> = Once::new();
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pub fn init(start_addr: PhysicalAddress, page_count: usize) {
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let mut memory_manager = MemoryManager::new();
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unsafe {
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memory_manager.add_range(start_addr, page_count);
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PAGE_TABLE.call_once(|| Mutex::new(memory_manager.zallocate_pages(0).unwrap()));
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}
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MEMORY_MANAGER.call_once(|| Mutex::new(memory_manager));
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}
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/// Align (set to a multiple of some power of two)
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/// This function always rounds up.
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fn align_val(val: usize, order: usize) -> usize {
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let o = (1 << order) - 1;
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(val + o) & !o
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}
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use core::num;
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use alloc::boxed::Box;
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use spin::{Mutex, Once};
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use crate::memory::{MemoryManager, PhysicalAddress, VirtualAddress};
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use super::PAGE_SIZE;
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pub enum PageSize {
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Size4KiB,
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Size2MiB,
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Size1GiB,
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// FIXME: SV48 support
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// Size512GiB,
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// FIXME: SV57 support
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// Size256TiB,
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}
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impl PageSize {
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fn level(&self) -> usize {
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match self {
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PageSize::Size4KiB => 0,
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PageSize::Size2MiB => 1,
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PageSize::Size1GiB => 2,
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// FIXME: SV48 and SV57 support
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}
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}
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}
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pub struct PageTable {
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entries: [PageEntry; 512]
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}
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impl PageTable {
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/// Walk the page table to convert a virtual address to a physical address.
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/// If a page fault would occur, this returns None. Otherwise, it returns the physical address.
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pub fn virt_to_phys(&self, vaddr: VirtualAddress) -> Option<PhysicalAddress> {
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let vpn = vaddr.vpns();
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let mut v = &self.entries[vpn[2]];
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for i in (0..=2).rev() {
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if v.is_invalid() {
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// This is an invalid entry, page fault.
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break;
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} else if v.is_leaf() {
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// In RISC-V, a leaf can be at any level.
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// The offset mask masks off the PPN. Each PPN is 9 bits and they start at bit #12.
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// So, our formula 12 + i * 9
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let off_mask = (1 << (12 + i * 9)) - 1;
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let vaddr_pgoff = vaddr.as_addr() & off_mask;
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let addr = ((v.entry() << 2) as usize) & !off_mask;
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return Some((addr | vaddr_pgoff).into());
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}
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// Set v to the next entry which is pointed to by this entry.
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// However, the address was shifted right by 2 places when stored in the page table
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// entry, so we shift it left to get it back into place.
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let entry = v.addr().as_ptr::<PageEntry>();
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// We do i - 1 here, however we should get None or Some() above
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// before we do 0 - 1 = -1.
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v = unsafe { entry.add(vpn[i - 1]).as_ref().unwrap() };
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}
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// If we get here, we've exhausted all valid tables and haven't
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// found a leaf.
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None
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}
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/// Maps a virtual address to a physical address
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/// flags should contain only the following:
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/// Read, Write, Execute, User, and/or Global
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/// flags MUST include one or more of the following:
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/// Read, Write, Execute
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/// The valid bit automatically gets added
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pub fn map(&mut self, vaddr: VirtualAddress, paddr: PhysicalAddress, flags: PageEntryFlags, page_size: PageSize) {
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assert!(flags as usize & 0xe != 0);
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let vpn = vaddr.vpns();
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let ppn = paddr.ppns();
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let level = page_size.level();
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let mut v = &mut self.entries[vpn[2]];
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// Now, we're going to traverse the page table and set the bits properly. We expect the root
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// to be valid, however we're required to create anything beyond the root
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for i in (level..2).rev() {
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if v.is_invalid() {
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let mut mm = MEMORY_MANAGER.get().unwrap().lock();
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let page = mm.zallocate_pages(1).unwrap().as_addr();
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v.set_entry((page as usize >> 2) | PageEntryFlags::Valid as usize);
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}
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let entry = v.addr().as_mut_ptr::<PageEntry>();
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v = unsafe { entry.add(vpn[i]).as_mut().unwrap() };
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}
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// When we get here, we should be at VPN[0] and v should be pointing to our entry.
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// The entry structure is Figure 4.18 in the RISC-V Privileged Specification
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let entry = (ppn[2] << 28) as usize // PPN[2] = [53:28]
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| (ppn[1] << 19) as usize // PPN[1] = [27:19]
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| (ppn[0] << 10) as usize // PPN[0] = [18:10]
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| flags as usize // Specified bits, such as User, Read, Write, etc.
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| PageEntryFlags::Valid as usize;
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v.set_entry(entry);
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}
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/// Identity maps a page of memory
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pub fn identity_map(&mut self, addr: PhysicalAddress, flags: PageEntryFlags, page_size: PageSize) {
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// log::debug!("identity mapped {addr}");
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self.map(addr.as_addr().into(), addr, flags, page_size);
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}
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/// Identity maps a range of contiguous memory
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/// This assumes that start <= end
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pub fn identity_map_range(&mut self, start: PhysicalAddress, end: PhysicalAddress, flags: PageEntryFlags) {
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log::debug!("start: {start}, end: {end}");
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let mut mem_addr = start.as_addr() & !(PAGE_SIZE - 1);
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let num_pages = (align_val(end.as_addr(), 12) - mem_addr - 1) / PAGE_SIZE + 1;
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for _ in 0..num_pages {
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// FIXME: we can merge these page entries if possible into Size2MiB or larger entries
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self.identity_map(mem_addr.into(), flags, PageSize::Size4KiB);
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mem_addr += 1 << 12;
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}
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}
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/// Unmaps a page of memory at vaddr
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pub fn unmap(&mut self, vaddr: VirtualAddress) {
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let vpn = vaddr.vpns();
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// Now, we're going to traverse the page table and clear the bits
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let mut v = &mut self.entries[vpn[2]];
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for i in (0..2).rev() {
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if v.is_invalid() {
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// This is an invalid entry, page is already unmapped
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return;
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} else if v.is_leaf() {
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// This is a leaf, which can be at any level
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// In order to make this page unmapped, we need to clear the entry
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v.set_entry(0);
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return;
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}
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let entry = v.addr().as_mut_ptr::<PageEntry>();
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v = unsafe { entry.add(vpn[i]).as_mut().unwrap() };
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}
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// If we're here this is an unmapped page
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return;
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}
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/// Unmaps a range of contiguous memory
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/// This assumes that start <= end
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pub fn unmap_range(&mut self, start: VirtualAddress, end: VirtualAddress) {
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let mut mem_addr = start.as_addr() & !(PAGE_SIZE - 1);
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let num_pages = (align_val(end.as_addr(), 12) - mem_addr) / PAGE_SIZE;
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for _ in 0..num_pages {
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self.unmap(mem_addr.into());
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mem_addr += 1 << 12;
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}
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}
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/// Frees all memory associated with a table.
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/// NOTE: This does NOT free the table directly. This must be freed manually.
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fn destroy(&mut self) {
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for entry in &mut self.entries {
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entry.destroy()
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}
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}
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}
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#[repr(usize)]
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#[derive(Clone, Copy, Debug)]
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pub enum PageEntryFlags {
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None = 0,
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Valid = 1,
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Read = 1 << 1,
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Write = 1 << 2,
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Execute = 1 << 3,
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User = 1 << 4,
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Global = 1 << 5,
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Access = 1 << 6,
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Dirty = 1 << 7,
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// for convenience
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ReadWrite = Self::Read as usize | Self::Write as usize,
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ReadExecute = Self::Read as usize | Self::Execute as usize,
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ReadWriteExecute = Self::Read as usize | Self::Write as usize | Self::Execute as usize,
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UserReadWrite = Self::User as usize | Self::ReadWrite as usize,
|
||||
UserReadExecute = Self::User as usize | Self::ReadExecute as usize,
|
||||
UserReadWriteExecute = Self::User as usize | Self::ReadWriteExecute as usize,
|
||||
}
|
||||
|
||||
struct PageEntry(usize);
|
||||
|
||||
impl PageEntry {
|
||||
fn is_valid(&self) -> bool {
|
||||
self.0 & PageEntryFlags::Valid as usize != 0
|
||||
}
|
||||
|
||||
fn is_invalid(&self) -> bool {
|
||||
!self.is_valid()
|
||||
}
|
||||
|
||||
fn is_leaf(&self) -> bool {
|
||||
self.0 & PageEntryFlags::ReadWriteExecute as usize != 0
|
||||
}
|
||||
|
||||
fn is_branch(&self) -> bool {
|
||||
!self.is_leaf()
|
||||
}
|
||||
|
||||
fn entry(&self) -> usize {
|
||||
self.0
|
||||
}
|
||||
|
||||
fn set_entry(&mut self, entry: usize) {
|
||||
self.0 = entry;
|
||||
}
|
||||
|
||||
fn clear_flag(&mut self, flag: PageEntryFlags) {
|
||||
self.0 &= !(flag as usize);
|
||||
}
|
||||
|
||||
fn set_flag(&mut self, flag: PageEntryFlags) {
|
||||
self.0 |= flag as usize;
|
||||
}
|
||||
|
||||
fn addr(&self) -> PhysicalAddress {
|
||||
((self.entry() as usize & !0x3ff) << 2).into()
|
||||
}
|
||||
|
||||
fn destroy(&mut self) {
|
||||
if self.is_valid() && self.is_branch() {
|
||||
// This is a valid entry so drill down and free
|
||||
let memaddr = self.addr();
|
||||
let table = memaddr.as_mut_ptr::<PageTable>();
|
||||
unsafe {
|
||||
(*table).destroy();
|
||||
let mut mm = MEMORY_MANAGER.get().unwrap().lock();
|
||||
mm.deallocate_pages(memaddr.into(), 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// FIXME: PageTable should be integrated into MemoryManager *somehow*
|
||||
pub static MEMORY_MANAGER: Once<Mutex<MemoryManager>> = Once::new();
|
||||
pub static PAGE_TABLE: Once<Mutex<PhysicalAddress>> = Once::new();
|
||||
|
||||
pub fn init(start_addr: PhysicalAddress, page_count: usize) {
|
||||
let mut memory_manager = MemoryManager::new();
|
||||
|
||||
unsafe {
|
||||
memory_manager.add_range(start_addr, page_count);
|
||||
PAGE_TABLE.call_once(|| Mutex::new(memory_manager.zallocate_pages(0).unwrap()));
|
||||
}
|
||||
|
||||
MEMORY_MANAGER.call_once(|| Mutex::new(memory_manager));
|
||||
}
|
||||
|
||||
/// Align (set to a multiple of some power of two)
|
||||
/// This function always rounds up.
|
||||
fn align_val(val: usize, order: usize) -> usize {
|
||||
let o = (1 << order) - 1;
|
||||
(val + o) & !o
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,35 +1,30 @@
|
|||
.section .rodata
|
||||
.global TEXT_START
|
||||
TEXT_START: .quad _text_start
|
||||
.global TEXT_END
|
||||
TEXT_END: .quad _text_end
|
||||
|
||||
.global RODATA_START
|
||||
RODATA_START: .quad _rodata_start
|
||||
.global RODATA_END
|
||||
RODATA_END: .quad _rodata_end
|
||||
|
||||
.global DATA_START
|
||||
DATA_START: .quad _data_start
|
||||
.global DATA_END
|
||||
DATA_END: .quad _data_end
|
||||
|
||||
.global SDATA_START
|
||||
SDATA_START: .quad _sdata_start
|
||||
.global SDATA_END
|
||||
SDATA_END: .quad _sdata_end
|
||||
|
||||
.global BSS_START
|
||||
BSS_START: .quad _bss_start
|
||||
.global BSS_END
|
||||
BSS_END: .quad _bss_end
|
||||
|
||||
.global INITIAL_KERNEL_HEAP_START
|
||||
INITIAL_KERNEL_HEAP_START: .quad _initial_kernel_heap_start
|
||||
.global INITIAL_KERNEL_HEAP_SIZE
|
||||
INITIAL_KERNEL_HEAP_SIZE: .quad _initial_kernel_heap_size
|
||||
|
||||
.global USABLE_MEMORY_START
|
||||
USABLE_MEMORY_START: .quad _usable_memory_start
|
||||
.global USABLE_MEMORY_SIZE
|
||||
USABLE_MEMORY_SIZE: .quad _usable_memory_size
|
||||
.section .rodata
|
||||
.global TEXT_START
|
||||
.global TEXT_END
|
||||
.global RODATA_START
|
||||
.global RODATA_END
|
||||
.global DATA_START
|
||||
.global DATA_END
|
||||
.global SDATA_START
|
||||
.global SDATA_END
|
||||
.global BSS_START
|
||||
.global BSS_END
|
||||
.global INITIAL_KERNEL_HEAP_START
|
||||
.global INITIAL_KERNEL_HEAP_SIZE
|
||||
.global USABLE_MEMORY_START
|
||||
.global USABLE_MEMORY_SIZE
|
||||
|
||||
TEXT_START: .quad _text_start
|
||||
TEXT_END: .quad _text_end
|
||||
RODATA_START: .quad _rodata_start
|
||||
RODATA_END: .quad _rodata_end
|
||||
DATA_START: .quad _data_start
|
||||
DATA_END: .quad _data_end
|
||||
SDATA_START: .quad _sdata_start
|
||||
SDATA_END: .quad _sdata_end
|
||||
BSS_START: .quad _bss_start
|
||||
BSS_END: .quad _bss_end
|
||||
INITIAL_KERNEL_HEAP_START: .quad _initial_kernel_heap_start
|
||||
INITIAL_KERNEL_HEAP_SIZE: .quad _initial_kernel_heap_size
|
||||
USABLE_MEMORY_START: .quad _usable_memory_start
|
||||
USABLE_MEMORY_SIZE: .quad _usable_memory_size
|
||||
|
|
|
|||
|
|
@ -1,93 +1,90 @@
|
|||
mod memory;
|
||||
|
||||
use core::{arch::{asm, global_asm}, fmt::Write};
|
||||
use alloc::boxed::Box;
|
||||
use sbi::system_reset::{ResetType, ResetReason, system_reset};
|
||||
use spin::{Mutex, Once};
|
||||
use uart_16550::MmioSerialPort;
|
||||
|
||||
use crate::{allocator, memory::PhysicalAddress, arch::riscv64::memory::{PAGE_TABLE, PageEntryFlags, PageSize, PageTable}};
|
||||
|
||||
global_asm!(include_str!("entry.s"));
|
||||
global_asm!(include_str!("memory_regions.s"));
|
||||
|
||||
pub const PAGE_SIZE: usize = 4096;
|
||||
|
||||
extern {
|
||||
static TEXT_START: PhysicalAddress;
|
||||
static TEXT_END: PhysicalAddress;
|
||||
|
||||
static RODATA_START: PhysicalAddress;
|
||||
static RODATA_END: PhysicalAddress;
|
||||
|
||||
static DATA_START: PhysicalAddress;
|
||||
static DATA_END: PhysicalAddress;
|
||||
|
||||
static SDATA_START: PhysicalAddress;
|
||||
static SDATA_END: PhysicalAddress;
|
||||
|
||||
static BSS_START: PhysicalAddress;
|
||||
static BSS_END: PhysicalAddress;
|
||||
|
||||
static INITIAL_KERNEL_HEAP_START: PhysicalAddress;
|
||||
static INITIAL_KERNEL_HEAP_SIZE: usize;
|
||||
|
||||
static USABLE_MEMORY_START: PhysicalAddress;
|
||||
static USABLE_MEMORY_SIZE: usize;
|
||||
}
|
||||
|
||||
static SERIAL_CONSOLE: Once<Mutex<MmioSerialPort>> = Once::new();
|
||||
|
||||
#[no_mangle]
|
||||
unsafe extern fn _kernel_start() -> ! {
|
||||
SERIAL_CONSOLE.call_once(|| Mutex::new(unsafe { MmioSerialPort::new(0x1000_0000) }));
|
||||
crate::logger::init().expect("failed to set logger");
|
||||
log::info!("Initialising AKern {}", crate::VERSION);
|
||||
|
||||
allocator::init(INITIAL_KERNEL_HEAP_START.as_mut_ptr::<u8>(), INITIAL_KERNEL_HEAP_SIZE);
|
||||
memory::init(USABLE_MEMORY_START.into(), USABLE_MEMORY_SIZE / PAGE_SIZE);
|
||||
|
||||
let mut page_table_addr = PAGE_TABLE.get().unwrap().lock();
|
||||
let mut page_table = page_table_addr.as_mut_ptr::<PageTable>().as_mut().unwrap();
|
||||
|
||||
// Map text (executable) section
|
||||
page_table.identity_map_range(TEXT_START, TEXT_END, PageEntryFlags::ReadExecute);
|
||||
// Map rodata section
|
||||
page_table.identity_map_range(RODATA_START, RODATA_END, PageEntryFlags::Read);
|
||||
// Map data section
|
||||
page_table.identity_map_range(DATA_START, DATA_END, PageEntryFlags::ReadWrite);
|
||||
// Map sdata section
|
||||
page_table.identity_map_range(SDATA_START, SDATA_END, PageEntryFlags::ReadWrite);
|
||||
// Map bss section (includes stack and initial kernel heap)
|
||||
page_table.identity_map_range(BSS_START, BSS_END, PageEntryFlags::ReadWrite);
|
||||
// Map usable memory range (as rw so not executable)
|
||||
page_table.identity_map_range(USABLE_MEMORY_START, USABLE_MEMORY_START + USABLE_MEMORY_SIZE.into(), PageEntryFlags::ReadWrite);
|
||||
// Map Uart so we can continue using serial
|
||||
page_table.identity_map(0x1000_0000_usize.into(), PageEntryFlags::ReadWrite, PageSize::Size4KiB);
|
||||
|
||||
let table_ppn = page_table_addr.as_addr() as usize >> 12;
|
||||
let satp_value = 8 << 60 | table_ppn;
|
||||
log::info!("Enabling the MMU...");
|
||||
|
||||
asm!(
|
||||
"csrw satp, {}",
|
||||
"sfence.vma",
|
||||
in(reg) satp_value,
|
||||
);
|
||||
|
||||
log::info!("We're in PAGING LAND!");
|
||||
|
||||
#[allow(unreachable_code)]
|
||||
match system_reset(ResetType::Shutdown, ResetReason::NoReason).unwrap() {}
|
||||
}
|
||||
|
||||
/// Spin loop
|
||||
pub fn sloop() -> ! {
|
||||
loop {
|
||||
unsafe { asm!("wfi") }
|
||||
}
|
||||
}
|
||||
|
||||
pub fn log(args: core::fmt::Arguments<'_>) -> core::fmt::Result {
|
||||
SERIAL_CONSOLE.get().unwrap().lock().write_fmt(args)
|
||||
}
|
||||
mod memory;
|
||||
|
||||
use core::{arch::{asm, global_asm}, fmt::Write};
|
||||
use alloc::boxed::Box;
|
||||
use sbi::system_reset::{ResetType, ResetReason, system_reset};
|
||||
use spin::{Mutex, Once};
|
||||
use uart_16550::MmioSerialPort;
|
||||
|
||||
use crate::{allocator, memory::PhysicalAddress, arch::riscv64::memory::{PAGE_TABLE, PageEntryFlags, PageSize, PageTable}};
|
||||
|
||||
global_asm!(include_str!("entry.s"));
|
||||
global_asm!(include_str!("memory_regions.s"));
|
||||
|
||||
pub const PAGE_SIZE: usize = 4096;
|
||||
|
||||
extern {
|
||||
static TEXT_START: PhysicalAddress;
|
||||
static TEXT_END: PhysicalAddress;
|
||||
|
||||
static RODATA_START: PhysicalAddress;
|
||||
static RODATA_END: PhysicalAddress;
|
||||
|
||||
static DATA_START: PhysicalAddress;
|
||||
static DATA_END: PhysicalAddress;
|
||||
|
||||
static SDATA_START: PhysicalAddress;
|
||||
static SDATA_END: PhysicalAddress;
|
||||
|
||||
static BSS_START: PhysicalAddress;
|
||||
static BSS_END: PhysicalAddress;
|
||||
|
||||
static INITIAL_KERNEL_HEAP_START: PhysicalAddress;
|
||||
static INITIAL_KERNEL_HEAP_SIZE: usize;
|
||||
|
||||
static USABLE_MEMORY_START: PhysicalAddress;
|
||||
static USABLE_MEMORY_SIZE: usize;
|
||||
}
|
||||
|
||||
static SERIAL_CONSOLE: Once<Mutex<MmioSerialPort>> = Once::new();
|
||||
|
||||
#[no_mangle]
|
||||
unsafe extern fn _kernel_start() -> ! {
|
||||
SERIAL_CONSOLE.call_once(|| Mutex::new(unsafe { MmioSerialPort::new(0x1000_0000) }));
|
||||
crate::logger::init().expect("failed to set logger");
|
||||
log::info!("Initialising AKern {}", crate::VERSION);
|
||||
|
||||
allocator::init(INITIAL_KERNEL_HEAP_START.as_mut_ptr::<u8>(), INITIAL_KERNEL_HEAP_SIZE);
|
||||
memory::init(USABLE_MEMORY_START.into(), USABLE_MEMORY_SIZE / PAGE_SIZE);
|
||||
|
||||
let mut page_table_addr = PAGE_TABLE.get().unwrap().lock();
|
||||
let mut page_table = page_table_addr.as_mut_ptr::<PageTable>().as_mut().unwrap();
|
||||
|
||||
// Map text (executable) section
|
||||
page_table.identity_map_range(TEXT_START, TEXT_END, PageEntryFlags::ReadExecute);
|
||||
// Map rodata section
|
||||
page_table.identity_map_range(RODATA_START, RODATA_END, PageEntryFlags::Read);
|
||||
// Map data section
|
||||
page_table.identity_map_range(DATA_START, DATA_END, PageEntryFlags::ReadWrite);
|
||||
// Map sdata section
|
||||
page_table.identity_map_range(SDATA_START, SDATA_END, PageEntryFlags::ReadWrite);
|
||||
// Map bss section (includes stack and initial kernel heap)
|
||||
page_table.identity_map_range(BSS_START, BSS_END, PageEntryFlags::ReadWrite);
|
||||
// Map usable memory range (as rw so not executable)
|
||||
page_table.identity_map_range(USABLE_MEMORY_START, USABLE_MEMORY_START + USABLE_MEMORY_SIZE.into(), PageEntryFlags::ReadWrite);
|
||||
// Map Uart so we can continue using serial
|
||||
page_table.identity_map(0x1000_0000_usize.into(), PageEntryFlags::ReadWrite, PageSize::Size4KiB);
|
||||
|
||||
let table_ppn = page_table_addr.as_addr() as usize >> 12;
|
||||
let satp_value = 8 << 60 | table_ppn;
|
||||
log::info!("Enabling MMU");
|
||||
|
||||
asm!(
|
||||
"csrw satp, {}",
|
||||
"sfence.vma",
|
||||
in(reg) satp_value,
|
||||
);
|
||||
|
||||
crate::kmain::kmain("baka=9", None);
|
||||
}
|
||||
|
||||
/// Spin loop
|
||||
pub fn sloop() -> ! {
|
||||
loop {
|
||||
unsafe { asm!("wfi") }
|
||||
}
|
||||
}
|
||||
|
||||
pub fn log(args: core::fmt::Arguments<'_>) -> core::fmt::Result {
|
||||
SERIAL_CONSOLE.get().unwrap().lock().write_fmt(args)
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue