Litrally almost functional PS/2 driver. #19
6
Cargo.lock
generated
6
Cargo.lock
generated
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@ -213,12 +213,12 @@ dependencies = [
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[[package]]
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[[package]]
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name = "hbbytecode"
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name = "hbbytecode"
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version = "0.1.0"
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version = "0.1.0"
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source = "git+https://git.ablecorp.us/AbleOS/holey-bytes.git#397b2a4b1b7c088f379f32d846e235c1286e17e0"
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source = "git+https://git.ablecorp.us/AbleOS/holey-bytes.git#fe5a8631f66e7acde8707a68ad25074ab5b1f408"
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[[package]]
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[[package]]
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name = "hblang"
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name = "hblang"
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version = "0.1.0"
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version = "0.1.0"
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source = "git+https://git.ablecorp.us/AbleOS/holey-bytes.git#397b2a4b1b7c088f379f32d846e235c1286e17e0"
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source = "git+https://git.ablecorp.us/AbleOS/holey-bytes.git#fe5a8631f66e7acde8707a68ad25074ab5b1f408"
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dependencies = [
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dependencies = [
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"hashbrown",
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"hashbrown",
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"hbbytecode",
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"hbbytecode",
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@ -229,7 +229,7 @@ dependencies = [
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[[package]]
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[[package]]
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name = "hbvm"
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name = "hbvm"
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version = "0.1.0"
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version = "0.1.0"
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source = "git+https://git.ablecorp.us/AbleOS/holey-bytes.git#397b2a4b1b7c088f379f32d846e235c1286e17e0"
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source = "git+https://git.ablecorp.us/AbleOS/holey-bytes.git#fe5a8631f66e7acde8707a68ad25074ab5b1f408"
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dependencies = [
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dependencies = [
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"hbbytecode",
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"hbbytecode",
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]
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]
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@ -2,6 +2,9 @@
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.{bit0, bit1, bit5, bit6, bit7} := @use("bits.hb");
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.{bit0, bit1, bit5, bit6, bit7} := @use("bits.hb");
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.{Port, port_at_startup} := @use("port.hb")
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.{Port, port_at_startup} := @use("port.hb")
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port1 := port_at_startup
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port2 := port_at_startup
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$disable_port1 := fn(): void memory.outb(0x64, 0xAD)
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$disable_port1 := fn(): void memory.outb(0x64, 0xAD)
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$enable_port1 := fn(): void memory.outb(0x64, 0xAE)
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$enable_port1 := fn(): void memory.outb(0x64, 0xAE)
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$disable_port2 := fn(): void memory.outb(0x64, 0xA7)
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$disable_port2 := fn(): void memory.outb(0x64, 0xA7)
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@ -58,9 +61,6 @@ flush_input := fn(): void {
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loop if has_input(get_info()) == false break else get_info()
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loop if has_input(get_info()) == false break else get_info()
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}
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}
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port1 := port_at_startup
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port2 := port_at_startup
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init := fn(): void {
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init := fn(): void {
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disable_port1()
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disable_port1()
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disable_port2()
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disable_port2()
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@ -5,7 +5,8 @@ format_page := memory.dangling(u8)
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info := controller.Info.(0)
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info := controller.Info.(0)
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process := fn(port: ^controller.Port): bool {
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process := fn(port: ^controller.Port): void {
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}
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}
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check_complete := fn(port: ^controller.Port): bool {
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check_complete := fn(port: ^controller.Port): bool {
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