AbleOS/holey-bytes
3
3
Fork 5
Code Issues 2 Pull requests Packages Projects Releases Wiki Activity

fixed float comparison in the vm

Browse source
This commit is contained in:
Jakub Doka 2024-11-16 21:38:10 +01:00
parent a64383e72b
commit 12bb7029b4
No known key found for this signature in database
GPG key ID: C6E9A89936B8C143
2 changed files with 12 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
lang/src/son.rs
View file

@ -4844,7 +4844,7 @@ mod tests {
fn generate(ident: &'static str, input: &'static str, output: &mut String) { fn generate(ident: &'static str, input: &'static str, output: &mut String) {
_ = log::set_logger(&crate::fs::Logger); _ = log::set_logger(&crate::fs::Logger);
log::set_max_level(log::LevelFilter::Info); log::set_max_level(log::LevelFilter::Info);
log::set_max_level(log::LevelFilter::Trace); //log::set_max_level(log::LevelFilter::Trace);
let mut ctx = CodegenCtx::default(); let mut ctx = CodegenCtx::default();
let (ref files, embeds) = crate::test_parse_files(ident, input, &mut ctx.parser); let (ref files, embeds) = crate::test_parse_files(ident, input, &mut ctx.parser);

19
vm/src/vmrun.rs
View file

@ -307,10 +307,10 @@ where
.write_reg(tg, 1. / self.read_reg(reg).cast::<f32>())), .write_reg(tg, 1. / self.read_reg(reg).cast::<f32>())),
I::FINV64 => handler!(self, |OpsRR(tg, reg)| self I::FINV64 => handler!(self, |OpsRR(tg, reg)| self
.write_reg(tg, 1. / self.read_reg(reg).cast::<f64>())), .write_reg(tg, 1. / self.read_reg(reg).cast::<f64>())),
I::FCMPLT32 => self.fcmp::<f32>(Ordering::Less), I::FCMPLT32 => self.fcmp::<f32>(false, Ordering::Less),
I::FCMPLT64 => self.fcmp::<f64>(Ordering::Less), I::FCMPLT64 => self.fcmp::<f64>(false, Ordering::Less),
I::FCMPGT32 => self.fcmp::<f32>(Ordering::Greater), I::FCMPGT32 => self.fcmp::<f32>(true, Ordering::Greater),
I::FCMPGT64 => self.fcmp::<f64>(Ordering::Greater), I::FCMPGT64 => self.fcmp::<f64>(true, Ordering::Greater),
I::ITF32 => handler!(self, |OpsRR(tg, reg)| self I::ITF32 => handler!(self, |OpsRR(tg, reg)| self
.write_reg(tg, self.read_reg(reg).cast::<i64>() as f32)), .write_reg(tg, self.read_reg(reg).cast::<i64>() as f32)),
I::ITF64 => handler!(self, |OpsRR(tg, reg)| self I::ITF64 => handler!(self, |OpsRR(tg, reg)| self
@ -512,12 +512,15 @@ where
/// Float comparsion /// Float comparsion
#[inline(always)] #[inline(always)]
unsafe fn fcmp<T: PartialOrd + ValueVariant>(&mut self, nan: Ordering) { unsafe fn fcmp<T: PartialOrd + ValueVariant>(&mut self, swapped: bool, expected: Ordering) {
unsafe { unsafe {
handler!(self, |OpsRRR(tg, a0, a1)| { handler!(self, |OpsRRR(tg, a0, a1)| {
let a0 = self.read_reg(a0).cast::<T>(); let mut a0 = self.read_reg(a0).cast::<T>();
let a1 = self.read_reg(a1).cast::<T>(); let mut a1 = self.read_reg(a1).cast::<T>();
self.write_reg(tg, (a0.partial_cmp(&a1).unwrap_or(nan) as i8 + 1) as u8) if swapped {
core::mem::swap(&mut a0, &mut a1);
}
self.write_reg(tg, a0.partial_cmp(&a1).map_or(false, |v| v == expected) as u8)
}); });
} }
} }