Removed some macros
parent
fce3fa5210
commit
193be0bd5a
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@ -130,9 +130,16 @@ dependencies = [
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"hbbytecode",
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"log",
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"paste",
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"sealed",
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"static_assertions",
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]
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[[package]]
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name = "heck"
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version = "0.4.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "95505c38b4572b2d910cecb0281560f54b440a19336cbbcb27bf6ce6adc6f5a8"
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[[package]]
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name = "lasso"
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version = "0.7.2"
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@ -246,6 +253,18 @@ dependencies = [
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"semver",
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]
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[[package]]
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name = "sealed"
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version = "0.5.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "f4a8caec23b7800fb97971a1c6ae365b6239aaeddfb934d6265f8505e795699d"
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dependencies = [
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"heck",
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"proc-macro2",
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"quote",
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"syn 2.0.25",
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]
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[[package]]
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name = "semver"
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version = "1.0.17"
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@ -27,8 +27,10 @@ macros::impl_both!(
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bbdh(p0: R, p1: R, p2: I, p3: u16)
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=> [LD, ST],
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bbd(p0: R, p1: R, p2: I)
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=> [ADDI, MULI, ANDI, ORI, XORI, SLI, SRI, SRSI, CMPI, CMPUI,
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BMC, JAL, JEQ, JNE, JLT, JGT, JLTU, JGTU, ADDFI, MULFI],
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=> [ADDI, MULI, ANDI, ORI, XORI, CMPI, CMPUI, BMC, JAL, JEQ, JNE, JLT, JGT, JLTU,
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JGTU, ADDFI, MULFI],
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bbw(p0: R, p1: R, p2: u32)
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=> [SLI, SRI, SRSI],
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bb(p0: R, p1: R)
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=> [NEG, NOT, CP, SWA, NEGF, ITF, FTI],
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bd(p0: R, p1: I)
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@ -215,37 +215,39 @@ macro_rules! extract_pat {
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};
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}
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/// Extract operand from code
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macro_rules! extract {
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// Register (require prefixing with r)
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($self:expr, R, $id:ident) => {
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extract_pat!($self, Token::Register($id));
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};
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/// Generate extract macro
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macro_rules! gen_extract {
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// Integer types have same body
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($($int:ident),* $(,)?) => {
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/// Extract operand from code
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macro_rules! extract {
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// Register (require prefixing with r)
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($self:expr, R, $id:ident) => {
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extract_pat!($self, Token::Register($id));
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};
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// Immediate
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($self:expr, I, $id:ident) => {
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let $id = match $self.next()? {
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// Either straight up integer
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Token::Integer(a) => InternalImm::Const(a),
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// …or a label
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Token::Symbol(a) => InternalImm::Named(a),
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_ => return Err(ErrorKind::UnexpectedToken),
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};
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};
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// Immediate
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($self:expr, I, $id:ident) => {
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let $id = match $self.next()? {
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// Either straight up integer
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Token::Integer(a) => InternalImm::Const(a),
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// …or a label
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Token::Symbol(a) => InternalImm::Named(a),
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_ => return Err(ErrorKind::UnexpectedToken),
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};
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};
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// Get u8, if not fitting, the token is claimed invalid
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($self:expr, u8, $id:ident) => {
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extract_pat!($self, Token::Integer($id));
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let $id = u8::try_from($id).map_err(|_| ErrorKind::InvalidToken)?;
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};
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// Get u16, if not fitting, the token is claimed invalid
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($self:expr, u16, $id:ident) => {
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extract_pat!($self, Token::Integer($id));
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let $id = u16::try_from($id).map_err(|_| ErrorKind::InvalidToken)?;
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// Get $int, if not fitting, the token is claimed invalid
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$(($self:expr, $int, $id:ident) => {
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extract_pat!($self, Token::Integer($id));
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let $id = $int::try_from($id).map_err(|_| ErrorKind::InvalidToken)?;
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});*;
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}
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};
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}
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gen_extract!(u8, u16, u32);
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/// Parameter extract incremental token-tree muncher
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///
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/// What else would it mean?
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@ -44,6 +44,11 @@ struct hbbc_ParamBBD
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typedef hbbc_ParamBBD;
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static_assert(sizeof(hbbc_ParamBBD) == 80 / 8);
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struct hbbc_ParamBBW
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{ uint8_t _0; uint8_t _1; uint32_t _2; }
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typedef hbbc_ParamBBW;
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static_assert(sizeof(hbbc_ParamBBW) == 48 / 8);
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struct hbbc_ParamBB
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{ uint8_t _0; uint8_t _1; }
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typedef hbbc_ParamBB;
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@ -20,7 +20,7 @@ constmod!(pub opcode(u8) {
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UN = 0, "N; Raises a trap";
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NOP = 1, "N; Do nothing";
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ADD = 2, "BBB; #0 ← #1 + #2";
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SUB = 3, "BBB; #0 ← #1 - #2";
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MUL = 4, "BBB; #0 ← #1 × #2";
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@ -41,9 +41,9 @@ constmod!(pub opcode(u8) {
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ANDI = 18, "BBD; #0 ← #1 & imm #2";
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ORI = 19, "BBD; #0 ← #1 | imm #2";
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XORI = 20, "BBD; #0 ← #1 ^ imm #2";
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SLI = 21, "BBD; #0 ← #1 « imm #2";
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SRI = 22, "BBD; #0 ← #1 » imm #2";
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SRSI = 23, "BBD; #0 ← #1 » imm #2 (signed)";
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SLI = 21, "BBW; #0 ← #1 « imm #2";
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SRI = 22, "BBW; #0 ← #1 » imm #2";
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SRSI = 23, "BBW; #0 ← #1 » imm #2 (signed)";
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CMPI = 24, "BBD; #0 ← #1 <=> imm #2";
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CMPUI = 25, "BBD; #0 ← #1 <=> imm #2 (unsigned)";
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@ -89,6 +89,9 @@ pub struct ParamBBDH(pub u8, pub u8, pub u64, pub u16);
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#[repr(packed)]
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pub struct ParamBBD(pub u8, pub u8, pub u64);
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#[repr(packed)]
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pub struct ParamBBW(pub u8, pub u8, pub u32);
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#[repr(packed)]
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pub struct ParamBB(pub u8, pub u8);
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@ -102,6 +105,7 @@ unsafe impl OpParam for ParamBBBB {}
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unsafe impl OpParam for ParamBBB {}
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unsafe impl OpParam for ParamBBDH {}
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unsafe impl OpParam for ParamBBD {}
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unsafe impl OpParam for ParamBBW {}
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unsafe impl OpParam for ParamBB {}
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unsafe impl OpParam for ParamBD {}
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unsafe impl OpParam for u64 {}
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@ -13,4 +13,5 @@ hashbrown = "0.13"
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hbbytecode.path = "../hbbytecode"
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log = "0.4"
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paste = "1.0"
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sealed = "0.5"
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static_assertions = "1.0"
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@ -69,7 +69,8 @@ pub fn validate(mut program: &[u8]) -> Result<(), Error> {
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| [ADD..=CMPU | BRC | ADDF..=MULF, _, _, _, rest @ ..]
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| [NEG..=NOT | CP..=SWA | NEGF..=FTI, _, _, rest @ ..]
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| [LI, _, _, _, _, _, _, _, _, _, rest @ ..]
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| [ADDI..=CMPUI | BMC | JAL..=JGTU | ADDFI..=MULFI, _, _, _, _, _, _, _, _, _, _, rest @ ..]
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| [ADDI..=XORI | CMPI..=CMPUI | BMC | JAL..=JGTU | ADDFI..=MULFI, _, _, _, _, _, _, _, _, _, _, rest @ ..]
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| [SLI..=SRSI, _, _, _, _, rest @ ..]
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| [LD..=ST, _, _, _, _, _, _, _, _, _, _, _, _, rest @ ..] => rest,
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_ => {
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return Err(Error {
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@ -7,91 +7,18 @@
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// - Instructions have to be valid as specified (values and sizes)
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// - Mapped pages should be at least 4 KiB
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use self::mem::HandlePageFault;
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pub mod mem;
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pub mod value;
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use {
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self::{mem::HandlePageFault, value::ValueVariant},
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crate::validate,
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core::ops,
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hbbytecode::{OpParam, ParamBB, ParamBBB, ParamBBBB, ParamBBD, ParamBBDH, ParamBD},
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core::{cmp::Ordering, ops},
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hbbytecode::{OpParam, ParamBB, ParamBBB, ParamBBBB, ParamBBD, ParamBBDH, ParamBBW, ParamBD},
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mem::Memory,
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static_assertions::assert_impl_one,
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value::Value,
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};
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/// Extract a parameter from program
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macro_rules! param {
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($self:expr, $ty:ty) => {{
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assert_impl_one!($ty: OpParam);
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let data = $self
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.program
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.as_ptr()
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.add($self.pc + 1)
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.cast::<$ty>()
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.read();
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$self.pc += 1 + core::mem::size_of::<$ty>();
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data
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}};
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}
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/// Perform binary operation `#0 ← #1 OP #2`
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macro_rules! binary_op {
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($self:expr, $ty:ident, $handler:expr) => {{
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let ParamBBB(tg, a0, a1) = param!($self, ParamBBB);
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$self.write_reg(
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tg,
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$handler(
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Value::$ty(&$self.read_reg(a0)),
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Value::$ty(&$self.read_reg(a1)),
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),
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);
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}};
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($self:expr, $ty:ident, $handler:expr, $con:ty) => {{
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let ParamBBB(tg, a0, a1) = param!($self, ParamBBB);
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$self.write_reg(
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tg,
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$handler(
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Value::$ty(&$self.read_reg(a0)),
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Value::$ty(&$self.read_reg(a1)) as $con,
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),
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);
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}};
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}
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/// Perform binary operation with immediate `#0 ← #1 OP imm #2`
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macro_rules! binary_op_imm {
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($self:expr, $ty:ident, $handler:expr) => {{
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let ParamBBD(tg, a0, imm) = param!($self, ParamBBD);
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$self.write_reg(
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tg,
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$handler(Value::$ty(&$self.read_reg(a0)), Value::$ty(&imm.into())),
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);
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}};
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($self:expr, $ty:ident, $handler:expr, $con:ty) => {{
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let ParamBBD(tg, a0, imm) = param!($self, ParamBBD);
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$self.write_reg(
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tg,
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$handler(Value::$ty(&$self.read_reg(a0)), Value::$ty(&imm.into()) as $con),
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);
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}};
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}
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/// Jump at `#3` if ordering on `#0 <=> #1` is equal to expected
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macro_rules! cond_jump {
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($self:expr, $ty:ident, $expected:ident) => {{
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let ParamBBD(a0, a1, jt) = param!($self, ParamBBD);
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if core::cmp::Ord::cmp(&$self.read_reg(a0).as_u64(), &$self.read_reg(a1).as_u64())
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== core::cmp::Ordering::$expected
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{
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$self.pc = jt as usize;
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}
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}};
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}
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/// HoleyBytes Virtual Machine
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pub struct Vm<'a, PfHandler, const TIMER_QUOTIENT: usize> {
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/// Holds 256 registers
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@ -107,7 +34,7 @@ pub struct Vm<'a, PfHandler, const TIMER_QUOTIENT: usize> {
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pub pfhandler: PfHandler,
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/// Program counter
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pc: usize,
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pub pc: usize,
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/// Program
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program: &'a [u8],
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@ -177,50 +104,56 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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unsafe {
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match *self.program.get_unchecked(self.pc) {
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UN => {
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param!(self, ());
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self.decode::<()>();
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return Err(VmRunError::Unreachable);
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}
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NOP => param!(self, ()),
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ADD => binary_op!(self, as_u64, u64::wrapping_add),
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SUB => binary_op!(self, as_u64, u64::wrapping_sub),
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MUL => binary_op!(self, as_u64, u64::wrapping_mul),
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AND => binary_op!(self, as_u64, ops::BitAnd::bitand),
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OR => binary_op!(self, as_u64, ops::BitOr::bitor),
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XOR => binary_op!(self, as_u64, ops::BitXor::bitxor),
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SL => binary_op!(self, as_u64, u64::wrapping_shl, u32),
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SR => binary_op!(self, as_u64, u64::wrapping_shr, u32),
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SRS => binary_op!(self, as_i64, i64::wrapping_shr, u32),
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NOP => self.decode::<()>(),
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ADD => self.binary_op(u64::wrapping_add),
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SUB => self.binary_op(u64::wrapping_sub),
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MUL => self.binary_op(u64::wrapping_mul),
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AND => self.binary_op::<u64>(ops::BitAnd::bitand),
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OR => self.binary_op::<u64>(ops::BitOr::bitor),
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XOR => self.binary_op::<u64>(ops::BitXor::bitxor),
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SL => self.binary_op(|l, r| u64::wrapping_shl(l, r as u32)),
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SR => self.binary_op(|l, r| u64::wrapping_shr(l, r as u32)),
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SRS => self.binary_op(|l, r| i64::wrapping_shl(l, r as u32)),
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CMP => {
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// Compare a0 <=> a1
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// < → -1
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// > → 1
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// = → 0
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let ParamBBB(tg, a0, a1) = param!(self, ParamBBB);
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0).as_i64().cmp(&self.read_reg(a1).as_i64()) as i64,
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self.read_reg(a0)
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.cast::<i64>()
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.cmp(&self.read_reg(a1).cast::<i64>())
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as i64,
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);
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}
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CMPU => {
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// Unsigned comparsion
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let ParamBBB(tg, a0, a1) = param!(self, ParamBBB);
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0).as_u64().cmp(&self.read_reg(a1).as_u64()) as i64,
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self.read_reg(a0)
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.cast::<u64>()
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.cmp(&self.read_reg(a1).cast::<u64>())
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as i64,
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);
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}
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NOT => {
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// Logical negation
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let param = param!(self, ParamBB);
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self.write_reg(param.0, !self.read_reg(param.1).as_u64());
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(tg, !self.read_reg(a0).cast::<u64>());
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}
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NEG => {
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// Bitwise negation
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let param = param!(self, ParamBB);
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(
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param.0,
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match self.read_reg(param.1).as_u64() {
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tg,
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match self.read_reg(a0).cast::<u64>() {
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0 => 1_u64,
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_ => 0,
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},
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@ -228,38 +161,41 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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}
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DIR => {
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// Fused Division-Remainder
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let ParamBBBB(dt, rt, a0, a1) = param!(self, ParamBBBB);
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let a0 = self.read_reg(a0).as_u64();
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let a1 = self.read_reg(a1).as_u64();
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let ParamBBBB(dt, rt, a0, a1) = self.decode();
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let a0 = self.read_reg(a0).cast::<u64>();
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let a1 = self.read_reg(a1).cast::<u64>();
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self.write_reg(dt, a0.checked_div(a1).unwrap_or(u64::MAX));
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self.write_reg(rt, a0.checked_rem(a1).unwrap_or(u64::MAX));
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}
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ADDI => binary_op_imm!(self, as_u64, ops::Add::add),
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MULI => binary_op_imm!(self, as_u64, ops::Mul::mul),
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ANDI => binary_op_imm!(self, as_u64, ops::BitAnd::bitand),
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ORI => binary_op_imm!(self, as_u64, ops::BitOr::bitor),
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XORI => binary_op_imm!(self, as_u64, ops::BitXor::bitxor),
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SLI => binary_op_imm!(self, as_u64, u64::wrapping_shl, u32),
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SRI => binary_op_imm!(self, as_u64, u64::wrapping_shr, u32),
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SRSI => binary_op_imm!(self, as_i64, i64::wrapping_shr, u32),
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ADDI => self.binary_op_imm(u64::wrapping_add),
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MULI => self.binary_op_imm(u64::wrapping_sub),
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ANDI => self.binary_op_imm::<u64>(ops::BitAnd::bitand),
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ORI => self.binary_op_imm::<u64>(ops::BitOr::bitor),
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XORI => self.binary_op_imm::<u64>(ops::BitXor::bitxor),
|
||||
SLI => self.binary_op_ims(u64::wrapping_shl),
|
||||
SRI => self.binary_op_ims(u64::wrapping_shr),
|
||||
SRSI => self.binary_op_ims(i64::wrapping_shr),
|
||||
CMPI => {
|
||||
let ParamBBD(tg, a0, imm) = param!(self, ParamBBD);
|
||||
let ParamBBD(tg, a0, imm) = self.decode();
|
||||
self.write_reg(
|
||||
tg,
|
||||
self.read_reg(a0).as_i64().cmp(&Value::from(imm).as_i64()) as i64,
|
||||
self.read_reg(a0)
|
||||
.cast::<i64>()
|
||||
.cmp(&Value::from(imm).cast::<i64>())
|
||||
as i64,
|
||||
);
|
||||
}
|
||||
CMPUI => {
|
||||
let ParamBBD(tg, a0, imm) = param!(self, ParamBBD);
|
||||
self.write_reg(tg, self.read_reg(a0).as_u64().cmp(&imm) as i64);
|
||||
let ParamBBD(tg, a0, imm) = self.decode();
|
||||
self.write_reg(tg, self.read_reg(a0).cast::<u64>().cmp(&imm) as i64);
|
||||
}
|
||||
CP => {
|
||||
let param = param!(self, ParamBB);
|
||||
self.write_reg(param.0, self.read_reg(param.1));
|
||||
let ParamBB(tg, a0) = self.decode();
|
||||
self.write_reg(tg, self.read_reg(a0));
|
||||
}
|
||||
SWA => {
|
||||
// Swap registers
|
||||
let ParamBB(r0, r1) = param!(self, ParamBB);
|
||||
let ParamBB(r0, r1) = self.decode();
|
||||
match (r0, r1) {
|
||||
(0, 0) => (),
|
||||
(dst, 0) | (0, dst) => self.write_reg(dst, 0_u64),
|
||||
|
|
@ -272,19 +208,19 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
|
|||
}
|
||||
}
|
||||
LI => {
|
||||
let param = param!(self, ParamBD);
|
||||
self.write_reg(param.0, param.1);
|
||||
let ParamBD(tg, imm) = self.decode();
|
||||
self.write_reg(tg, imm);
|
||||
}
|
||||
LD => {
|
||||
// Load. If loading more than register size, continue on adjecent registers
|
||||
let ParamBBDH(dst, base, off, count) = param!(self, ParamBBDH);
|
||||
let ParamBBDH(dst, base, off, count) = self.decode();
|
||||
let n: usize = match dst {
|
||||
0 => 1,
|
||||
_ => 0,
|
||||
};
|
||||
|
||||
self.memory.load(
|
||||
self.read_reg(base).as_u64() + off + n as u64,
|
||||
self.read_reg(base).cast::<u64>() + off + n as u64,
|
||||
self.registers.as_mut_ptr().add(usize::from(dst) + n).cast(),
|
||||
usize::from(count).saturating_sub(n),
|
||||
&mut self.pfhandler,
|
||||
|
|
@ -292,9 +228,9 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
|
|||
}
|
||||
ST => {
|
||||
// Store. Same rules apply as to LD
|
||||
let ParamBBDH(dst, base, off, count) = param!(self, ParamBBDH);
|
||||
let ParamBBDH(dst, base, off, count) = self.decode();
|
||||
self.memory.store(
|
||||
self.read_reg(base).as_u64() + off,
|
||||
self.read_reg(base).cast::<u64>() + off,
|
||||
self.registers.as_ptr().add(usize::from(dst)).cast(),
|
||||
count.into(),
|
||||
&mut self.pfhandler,
|
||||
|
|
@ -302,17 +238,17 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
|
|||
}
|
||||
BMC => {
|
||||
// Block memory copy
|
||||
let ParamBBD(src, dst, count) = param!(self, ParamBBD);
|
||||
let ParamBBD(src, dst, count) = self.decode();
|
||||
self.memory.block_copy(
|
||||
self.read_reg(src).as_u64(),
|
||||
self.read_reg(dst).as_u64(),
|
||||
self.read_reg(src).cast::<u64>(),
|
||||
self.read_reg(dst).cast::<u64>(),
|
||||
count as _,
|
||||
&mut self.pfhandler,
|
||||
)?;
|
||||
}
|
||||
BRC => {
|
||||
// Block register copy
|
||||
let ParamBBB(src, dst, count) = param!(self, ParamBBB);
|
||||
let ParamBBB(src, dst, count) = self.decode();
|
||||
core::ptr::copy(
|
||||
self.registers.get_unchecked(usize::from(src)),
|
||||
self.registers.get_unchecked_mut(usize::from(dst)),
|
||||
|
|
@ -322,24 +258,24 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
|
|||
JAL => {
|
||||
// Jump and link. Save PC after this instruction to
|
||||
// specified register and jump to reg + offset.
|
||||
let ParamBBD(save, reg, offset) = param!(self, ParamBBD);
|
||||
let ParamBBD(save, reg, offset) = self.decode();
|
||||
self.write_reg(save, self.pc as u64);
|
||||
self.pc = (self.read_reg(reg).as_u64() + offset) as usize;
|
||||
self.pc = (self.read_reg(reg).cast::<u64>() + offset) as usize;
|
||||
}
|
||||
// Conditional jumps, jump only to immediates
|
||||
JEQ => cond_jump!(self, int, Equal),
|
||||
JEQ => self.cond_jmp::<u64>(Ordering::Equal),
|
||||
JNE => {
|
||||
let ParamBBD(a0, a1, jt) = param!(self, ParamBBD);
|
||||
if self.read_reg(a0).as_u64() != self.read_reg(a1).as_u64() {
|
||||
let ParamBBD(a0, a1, jt) = self.decode();
|
||||
if self.read_reg(a0).cast::<u64>() != self.read_reg(a1).cast::<u64>() {
|
||||
self.pc = jt as usize;
|
||||
}
|
||||
}
|
||||
JLT => cond_jump!(self, int, Less),
|
||||
JGT => cond_jump!(self, int, Greater),
|
||||
JLTU => cond_jump!(self, sint, Less),
|
||||
JGTU => cond_jump!(self, sint, Greater),
|
||||
JLT => self.cond_jmp::<u64>(Ordering::Less),
|
||||
JGT => self.cond_jmp::<u64>(Ordering::Greater),
|
||||
JLTU => self.cond_jmp::<i64>(Ordering::Less),
|
||||
JGTU => self.cond_jmp::<i64>(Ordering::Greater),
|
||||
ECALL => {
|
||||
param!(self, ());
|
||||
self.decode::<()>();
|
||||
|
||||
// So we don't get timer interrupt after ECALL
|
||||
if TIMER_QUOTIENT != 0 {
|
||||
|
|
@ -347,38 +283,38 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
|
|||
}
|
||||
return Ok(VmRunOk::Ecall);
|
||||
}
|
||||
ADDF => binary_op!(self, as_f64, ops::Add::add),
|
||||
SUBF => binary_op!(self, as_f64, ops::Sub::sub),
|
||||
MULF => binary_op!(self, as_f64, ops::Mul::mul),
|
||||
ADDF => self.binary_op::<f64>(ops::Add::add),
|
||||
SUBF => self.binary_op::<f64>(ops::Sub::sub),
|
||||
MULF => self.binary_op::<f64>(ops::Mul::mul),
|
||||
DIRF => {
|
||||
let ParamBBBB(dt, rt, a0, a1) = param!(self, ParamBBBB);
|
||||
let a0 = self.read_reg(a0).as_f64();
|
||||
let a1 = self.read_reg(a1).as_f64();
|
||||
let ParamBBBB(dt, rt, a0, a1) = self.decode();
|
||||
let a0 = self.read_reg(a0).cast::<f64>();
|
||||
let a1 = self.read_reg(a1).cast::<f64>();
|
||||
self.write_reg(dt, a0 / a1);
|
||||
self.write_reg(rt, a0 % a1);
|
||||
}
|
||||
FMAF => {
|
||||
let ParamBBBB(dt, a0, a1, a2) = param!(self, ParamBBBB);
|
||||
let ParamBBBB(dt, a0, a1, a2) = self.decode();
|
||||
self.write_reg(
|
||||
dt,
|
||||
self.read_reg(a0).as_f64() * self.read_reg(a1).as_f64()
|
||||
+ self.read_reg(a2).as_f64(),
|
||||
self.read_reg(a0).cast::<f64>() * self.read_reg(a1).cast::<f64>()
|
||||
+ self.read_reg(a2).cast::<f64>(),
|
||||
);
|
||||
}
|
||||
NEGF => {
|
||||
let ParamBB(dt, a0) = param!(self, ParamBB);
|
||||
self.write_reg(dt, -self.read_reg(a0).as_f64());
|
||||
let ParamBB(dt, a0) = self.decode();
|
||||
self.write_reg(dt, -self.read_reg(a0).cast::<f64>());
|
||||
}
|
||||
ITF => {
|
||||
let ParamBB(dt, a0) = param!(self, ParamBB);
|
||||
self.write_reg(dt, self.read_reg(a0).as_i64() as f64);
|
||||
let ParamBB(dt, a0) = self.decode();
|
||||
self.write_reg(dt, self.read_reg(a0).cast::<i64>() as f64);
|
||||
}
|
||||
FTI => {
|
||||
let ParamBB(dt, a0) = param!(self, ParamBB);
|
||||
self.write_reg(dt, self.read_reg(a0).as_f64() as i64);
|
||||
let ParamBB(dt, a0) = self.decode();
|
||||
self.write_reg(dt, self.read_reg(a0).cast::<f64>() as i64);
|
||||
}
|
||||
ADDFI => binary_op_imm!(self, as_f64, ops::Add::add),
|
||||
MULFI => binary_op_imm!(self, as_f64, ops::Mul::mul),
|
||||
ADDFI => self.binary_op_imm::<f64>(ops::Add::add),
|
||||
MULFI => self.binary_op_imm::<f64>(ops::Mul::mul),
|
||||
op => return Err(VmRunError::InvalidOpcode(op)),
|
||||
}
|
||||
}
|
||||
|
|
@ -392,6 +328,55 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
|
|||
}
|
||||
}
|
||||
|
||||
/// Decode instruction operands
|
||||
#[inline]
|
||||
unsafe fn decode<T: OpParam>(&mut self) -> T {
|
||||
let data = self.program.as_ptr().add(self.pc + 1).cast::<T>().read();
|
||||
self.pc += 1 + core::mem::size_of::<T>();
|
||||
data
|
||||
}
|
||||
|
||||
/// Perform binary operating over two registers
|
||||
#[inline]
|
||||
unsafe fn binary_op<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
|
||||
let ParamBBB(tg, a0, a1) = self.decode();
|
||||
self.write_reg(
|
||||
tg,
|
||||
op(self.read_reg(a0).cast::<T>(), self.read_reg(a1).cast::<T>()),
|
||||
);
|
||||
}
|
||||
|
||||
/// Perform binary operation over register and immediate
|
||||
#[inline]
|
||||
unsafe fn binary_op_imm<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
|
||||
let ParamBBD(tg, reg, imm) = self.decode();
|
||||
self.write_reg(
|
||||
tg,
|
||||
op(self.read_reg(reg).cast::<T>(), Value::from(imm).cast::<T>()),
|
||||
);
|
||||
}
|
||||
|
||||
/// Perform binary operation over register and shift immediate
|
||||
#[inline]
|
||||
unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
|
||||
let ParamBBW(tg, reg, imm) = self.decode();
|
||||
self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm));
|
||||
}
|
||||
|
||||
/// Jump at `#3` if ordering on `#0 <=> #1` is equal to expected
|
||||
#[inline]
|
||||
unsafe fn cond_jmp<T: ValueVariant + Ord>(&mut self, expected: Ordering) {
|
||||
let ParamBBD(a0, a1, ja) = self.decode();
|
||||
if self
|
||||
.read_reg(a0)
|
||||
.cast::<T>()
|
||||
.cmp(&self.read_reg(a1).cast::<T>())
|
||||
== expected
|
||||
{
|
||||
self.pc = ja as usize;
|
||||
}
|
||||
}
|
||||
|
||||
/// Read register
|
||||
#[inline]
|
||||
unsafe fn read_reg(&self, n: u8) -> Value {
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
//! HoleyBytes register value definition
|
||||
|
||||
use core::fmt::Debug;
|
||||
use sealed::sealed;
|
||||
|
||||
/// Define [`Value`] union
|
||||
///
|
||||
|
|
@ -16,15 +16,6 @@ macro_rules! value_def {
|
|||
$(pub $ty: $ty),*
|
||||
}
|
||||
|
||||
paste::paste! {
|
||||
impl Value {$(
|
||||
#[doc = "Byte-reinterpret [`Value`] as [`" $ty "`]"]
|
||||
#[inline]
|
||||
pub fn [<as_ $ty>](&self) -> $ty {
|
||||
unsafe { self.$ty }
|
||||
}
|
||||
)*}
|
||||
}
|
||||
|
||||
$(
|
||||
impl From<$ty> for Value {
|
||||
|
|
@ -33,16 +24,41 @@ macro_rules! value_def {
|
|||
Self { $ty: value }
|
||||
}
|
||||
}
|
||||
|
||||
static_assertions::const_assert_eq!(
|
||||
core::mem::size_of::<$ty>(),
|
||||
core::mem::size_of::<Value>(),
|
||||
);
|
||||
|
||||
#[sealed]
|
||||
unsafe impl ValueVariant for $ty {}
|
||||
)*
|
||||
};
|
||||
}
|
||||
|
||||
impl Value {
|
||||
#[inline]
|
||||
pub fn cast<Variant: ValueVariant>(self) -> Variant {
|
||||
union Transmute<Variant: ValueVariant> {
|
||||
src: Value,
|
||||
variant: Variant,
|
||||
}
|
||||
|
||||
unsafe { Transmute { src: self }.variant }
|
||||
}
|
||||
}
|
||||
|
||||
/// # Safety
|
||||
/// - N/A, not to be implemented manually
|
||||
#[sealed]
|
||||
pub unsafe trait ValueVariant: Copy + Into<Value> {}
|
||||
|
||||
value_def!(u64, i64, f64);
|
||||
static_assertions::const_assert_eq!(core::mem::size_of::<Value>(), 8);
|
||||
|
||||
impl Debug for Value {
|
||||
impl core::fmt::Debug for Value {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
||||
// Print formatted as hexadecimal, unsigned integer
|
||||
write!(f, "{:x}", self.as_u64())
|
||||
write!(f, "{:x}", self.cast::<u64>())
|
||||
}
|
||||
}
|
||||
|
|
|
|||
6
spec.md
6
spec.md
|
|
@ -21,6 +21,7 @@
|
|||
| BBB | 24 bits |
|
||||
| BBDH | 96 bits |
|
||||
| BBD | 80 bits |
|
||||
| BBW | 48 bits |
|
||||
| BB | 16 bits |
|
||||
| BD | 72 bits |
|
||||
| D | 64 bits |
|
||||
|
|
@ -99,6 +100,11 @@
|
|||
| 18 | ANDI | Bitand |
|
||||
| 19 | ORI | Bitor |
|
||||
| 20 | XORI | Bitxor |
|
||||
|
||||
### Bitshifts
|
||||
- Type BBW
|
||||
| Opcode | Name | Action |
|
||||
|:------:|:----:|:-----------------------:|
|
||||
| 21 | SLI | Unsigned left bitshift |
|
||||
| 22 | SRI | Unsigned right bitshift |
|
||||
| 23 | SRSI | Signed right bitshift |
|
||||
|
|
|
|||
Loading…
Reference in New Issue