adding a lot better load elimination

This commit is contained in:
Jakub Doka 2024-10-29 10:31:52 +01:00
parent 30bd6103a6
commit 348d9014e3
No known key found for this signature in database
GPG key ID: C6E9A89936B8C143
6 changed files with 70 additions and 157 deletions

View file

@ -22,7 +22,6 @@ use {
fmt::{self, Debug, Display, Write}, fmt::{self, Debug, Display, Write},
format_args as fa, mem, format_args as fa, mem,
ops::{self, Deref}, ops::{self, Deref},
usize,
}, },
hashbrown::hash_map, hashbrown::hash_map,
hbbytecode::DisasmError, hbbytecode::DisasmError,
@ -678,10 +677,7 @@ impl Nodes {
loop { loop {
region = match self[region].kind { region = match self[region].kind {
Kind::BinOp { op: TokenKind::Add | TokenKind::Sub } => self[region].inputs[1], Kind::BinOp { op: TokenKind::Add | TokenKind::Sub } => self[region].inputs[1],
Kind::Phi => { Kind::Phi if self[region].inputs[2] == 0 => self[region].inputs[1],
debug_assert_eq!(self[region].inputs[2], 0);
self[region].inputs[1]
}
_ => break (self[region].aclass, region), _ => break (self[region].aclass, region),
}; };
} }
@ -1064,12 +1060,27 @@ impl Nodes {
} }
} }
K::Load => { K::Load => {
if self[target].inputs.len() == 3 let &[_, region, store] = self[target].inputs.as_slice() else { unreachable!() };
&& self[self[target].inputs[2]].kind == Kind::Stre
&& self[self[target].inputs[2]].inputs[2] == self[target].inputs[1] if self[store].kind == Kind::Stre
&& self[self[target].inputs[2]].ty == self[target].ty && self[store].inputs[2] == region
&& self[store].ty == self[target].ty
{ {
return Some(self[self[target].inputs[2]].inputs[1]); return Some(self[store].inputs[1]);
}
let (index, reg) = self.aclass_index(region);
if index != 0 && self[reg].kind == Kind::Stck {
let mut cursor = store;
while cursor != MEM
&& self[cursor].kind == Kind::Stre
&& self[cursor].inputs[1] != VOID
{
if self[cursor].inputs[2] == region && self[cursor].ty == self[target].ty {
return Some(self[cursor].inputs[1]);
}
cursor = self[cursor].inputs[3];
}
} }
} }
K::Loop => { K::Loop => {
@ -1537,7 +1548,7 @@ pub struct Node {
impl Node { impl Node {
fn is_dangling(&self) -> bool { fn is_dangling(&self) -> bool {
self.outputs.len() + self.lock_rc as usize == 0 self.outputs.len() + self.lock_rc as usize == 0 && self.kind != Kind::Arg
} }
fn key(&self) -> (Kind, &[Nid], ty::Id) { fn key(&self) -> (Kind, &[Nid], ty::Id) {

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@ -1,16 +1,6 @@
main: main:
ADDI64 r254, r254, -24d LI64 r1, 0d
ADDI64 r2, r254, 16d
ST r2, r254, 0a, 8h
LI64 r5, 0d
LI64 r4, 2d
ST r5, r254, 8a, 8h
ST r4, r254, 16a, 8h
LD r10, r254, 0a, 8h
ST r5, r10, 0a, 8h
LD r1, r254, 16a, 8h
ADDI64 r254, r254, 24d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 150 code size: 29
ret: 0 ret: 0
status: Ok(()) status: Ok(())

View file

@ -22,23 +22,9 @@ main:
JEQ r10, r9, :2 JEQ r10, r9, :2
LI64 r1, 64d LI64 r1, 64d
JMP :1 JMP :1
2: LD r4, r254, 0a, 1h 2: LI64 r1, 512d
LD r7, r254, 1a, 1h
ANDI r8, r4, 255d
LD r6, r254, 4a, 4h
LD r1, r254, 2a, 1h
ANDI r2, r7, 255d
ADD32 r7, r6, r8
LD r5, r254, 3a, 1h
ANDI r6, r1, 255d
ADD32 r11, r7, r2
ANDI r9, r5, 255d
ADD32 r2, r11, r6
ADD32 r4, r2, r9
ADD32 r6, r4, r12
ANDI r1, r6, 4294967295d
1: ADDI64 r254, r254, 12d 1: ADDI64 r254, r254, 12d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 387 code size: 257
ret: 512 ret: 512
status: Ok(()) status: Ok(())

View file

@ -13,17 +13,8 @@ main:
ADDI64 r254, r254, 24d ADDI64 r254, r254, 24d
JALA r0, r31, 0a JALA r0, r31, 0a
set: set:
ADDI64 r254, r254, -25d CP r1, r4
LI8 r7, 5b
ST r7, r254, 0a, 1h
ST r4, r254, 1a, 4h
LI64 r11, 8d
ST r11, r254, 5a, 4h
ST r2, r254, 9a, 8h
ST r3, r254, 17a, 8h
LD r1, r254, 1a, 4h
ADDI64 r254, r254, 25d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 277 code size: 167
ret: 1024 ret: 1024
status: Ok(()) status: Ok(())

View file

@ -1,99 +1,37 @@
main: main:
ADDI64 r254, r254, -152d ADDI64 r254, r254, -64d
LI8 r1, 0b LI64 r3, 1d
LI8 r3, 1b ADDI64 r2, r254, 48d
ST r1, r254, 116a, 1h
ST r3, r254, 112a, 1h
ST r1, r254, 117a, 1h
ST r3, r254, 113a, 1h
ST r1, r254, 118a, 1h
ST r3, r254, 114a, 1h
ST r1, r254, 119a, 1h
ST r3, r254, 115a, 1h
LD r1, r254, 116a, 1h
LD r4, r254, 112a, 1h
ADD8 r5, r4, r1
LD r8, r254, 113a, 1h
LD r9, r254, 117a, 1h
ST r5, r254, 116a, 1h
ADD8 r12, r9, r8
LD r4, r254, 114a, 1h
LD r5, r254, 118a, 1h
ST r12, r254, 117a, 1h
ADD8 r7, r5, r4
ST r7, r254, 118a, 1h
ST r3, r254, 119a, 1h
LD r12, r254, 117a, 1h
LD r1, r254, 118a, 1h
ADD8 r4, r1, r12
LD r5, r254, 116a, 1h
ADD8 r7, r5, r4
LI8 r9, 4b
ADD8 r1, r7, r3
ANDI r1, r1, 255d
ANDI r9, r9, 255d
JEQ r1, r9, :0
LI64 r1, 1008d
JMP :1
0: LI64 r6, 1d
ADDI64 r5, r254, 96d
ST r6, r254, 96a, 8h
LI64 r9, 2d
ST r9, r254, 104a, 8h
LI64 r2, 3d
ADDI64 r1, r254, 80d
ST r2, r254, 32a, 8h
LI64 r6, 4d
LI64 r2, 0d
BMC r5, r1, 16h
ST r6, r254, 40a, 8h
ST r2, r254, 16a, 8h
LD r11, r254, 80a, 8h
LD r1, r254, 32a, 8h
ST r2, r254, 24a, 8h
ADD64 r4, r1, r11
LD r7, r254, 88a, 8h
LD r2, r254, 16a, 8h
ST r4, r254, 120a, 8h
ADD64 r12, r7, r6
SUB64 r3, r2, r1
ADDI64 r8, r254, 48d
ST r12, r254, 128a, 8h
SUB64 r2, r1, r11
ST r3, r254, 48a, 8h ST r3, r254, 48a, 8h
LI64 r9, -4d LI64 r6, 2d
ST r2, r254, 136a, 8h ST r6, r254, 56a, 8h
SUB64 r7, r6, r7 LI64 r6, -3d
ST r9, r254, 56a, 8h ADDI64 r5, r254, 0d
ADDI64 r8, r8, 16d ADDI64 r11, r254, 32d
ST r7, r254, 144a, 8h ST r6, r254, 0a, 8h
BMC r5, r8, 16h LI64 r6, -4d
LD r6, r254, 120a, 8h BMC r2, r11, 16h
LD r8, r254, 48a, 8h
ADD64 r9, r8, r6
LD r11, r254, 56a, 8h
LD r1, r254, 128a, 8h
ST r9, r254, 48a, 8h
ADD64 r4, r1, r11
LD r8, r254, 64a, 8h
LD r9, r254, 136a, 8h
ST r4, r254, 56a, 8h
ADD64 r12, r9, r8
LD r2, r254, 72a, 8h
ST r12, r254, 64a, 8h
ADD64 r12, r2, r7
ST r12, r254, 72a, 8h
LD r7, r254, 48a, 8h
LD r9, r254, 64a, 8h
ADD64 r11, r9, r7
LD r1, r254, 56a, 8h
ST r11, r254, 0a, 8h
ADD64 r6, r1, r12
ST r6, r254, 8a, 8h ST r6, r254, 8a, 8h
LD r7, r254, 0a, 8h ADDI64 r3, r5, 16d
ADD64 r1, r7, r6 LD r9, r254, 40a, 8h
1: ADDI64 r254, r254, 152d LI64 r8, 4d
LD r10, r254, 32a, 8h
LI64 r11, 3d
BMC r2, r3, 16h
SUB64 r4, r8, r9
LD r12, r254, 24a, 8h
ADD64 r7, r10, r11
LD r1, r254, 0a, 8h
SUB64 r8, r11, r10
LD r2, r254, 16a, 8h
ADD64 r6, r12, r4
ADD64 r3, r1, r7
ADD64 r10, r2, r8
ADD64 r12, r9, r6
ADD64 r9, r10, r3
ADD64 r1, r9, r12
ADDI64 r254, r254, 64d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 980 code size: 308
ret: 10 ret: 10
status: Ok(()) status: Ok(())

View file

@ -33,22 +33,19 @@ fib_iter:
JMP :2 JMP :2
1: JALA r0, r31, 0a 1: JALA r0, r31, 0a
main: main:
ADDI64 r254, r254, -18d ADDI64 r254, r254, -24d
ST r31, r254, 2a, 16h ST r31, r254, 0a, 24h
LI8 r1, 10b LI64 r32, 10d
ST r1, r254, 0a, 1h CP r2, r32
ST r1, r254, 1a, 1h
LD r5, r254, 0a, 1h
ANDI r2, r5, 255d
JAL r31, r0, :fib JAL r31, r0, :fib
CP r32, r1 CP r2, r32
LI64 r2, 10d CP r33, r1
JAL r31, r0, :fib_iter JAL r31, r0, :fib_iter
CP r4, r32 CP r9, r33
SUB64 r1, r4, r1 SUB64 r1, r9, r1
LD r31, r254, 2a, 16h LD r31, r254, 0a, 24h
ADDI64 r254, r254, 18d ADDI64 r254, r254, 24d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 353 code size: 306
ret: 0 ret: 0
status: Ok(()) status: Ok(())