adding a lot better load elimination
This commit is contained in:
parent
30bd6103a6
commit
348d9014e3
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@ -22,7 +22,6 @@ use {
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fmt::{self, Debug, Display, Write},
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format_args as fa, mem,
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ops::{self, Deref},
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usize,
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},
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hashbrown::hash_map,
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hbbytecode::DisasmError,
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@ -678,10 +677,7 @@ impl Nodes {
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loop {
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region = match self[region].kind {
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Kind::BinOp { op: TokenKind::Add | TokenKind::Sub } => self[region].inputs[1],
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Kind::Phi => {
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debug_assert_eq!(self[region].inputs[2], 0);
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self[region].inputs[1]
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}
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Kind::Phi if self[region].inputs[2] == 0 => self[region].inputs[1],
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_ => break (self[region].aclass, region),
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};
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}
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@ -1064,12 +1060,27 @@ impl Nodes {
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}
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}
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K::Load => {
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if self[target].inputs.len() == 3
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&& self[self[target].inputs[2]].kind == Kind::Stre
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&& self[self[target].inputs[2]].inputs[2] == self[target].inputs[1]
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&& self[self[target].inputs[2]].ty == self[target].ty
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let &[_, region, store] = self[target].inputs.as_slice() else { unreachable!() };
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if self[store].kind == Kind::Stre
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&& self[store].inputs[2] == region
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&& self[store].ty == self[target].ty
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{
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return Some(self[self[target].inputs[2]].inputs[1]);
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return Some(self[store].inputs[1]);
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}
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let (index, reg) = self.aclass_index(region);
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if index != 0 && self[reg].kind == Kind::Stck {
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let mut cursor = store;
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while cursor != MEM
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&& self[cursor].kind == Kind::Stre
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&& self[cursor].inputs[1] != VOID
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{
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if self[cursor].inputs[2] == region && self[cursor].ty == self[target].ty {
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return Some(self[cursor].inputs[1]);
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}
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cursor = self[cursor].inputs[3];
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}
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}
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}
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K::Loop => {
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@ -1537,7 +1548,7 @@ pub struct Node {
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impl Node {
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fn is_dangling(&self) -> bool {
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self.outputs.len() + self.lock_rc as usize == 0
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self.outputs.len() + self.lock_rc as usize == 0 && self.kind != Kind::Arg
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}
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fn key(&self) -> (Kind, &[Nid], ty::Id) {
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@ -1,16 +1,6 @@
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main:
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ADDI64 r254, r254, -24d
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ADDI64 r2, r254, 16d
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ST r2, r254, 0a, 8h
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LI64 r5, 0d
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LI64 r4, 2d
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ST r5, r254, 8a, 8h
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ST r4, r254, 16a, 8h
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LD r10, r254, 0a, 8h
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ST r5, r10, 0a, 8h
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LD r1, r254, 16a, 8h
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ADDI64 r254, r254, 24d
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LI64 r1, 0d
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JALA r0, r31, 0a
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code size: 150
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code size: 29
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ret: 0
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status: Ok(())
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@ -22,23 +22,9 @@ main:
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JEQ r10, r9, :2
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LI64 r1, 64d
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JMP :1
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2: LD r4, r254, 0a, 1h
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LD r7, r254, 1a, 1h
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ANDI r8, r4, 255d
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LD r6, r254, 4a, 4h
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LD r1, r254, 2a, 1h
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ANDI r2, r7, 255d
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ADD32 r7, r6, r8
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LD r5, r254, 3a, 1h
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ANDI r6, r1, 255d
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ADD32 r11, r7, r2
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ANDI r9, r5, 255d
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ADD32 r2, r11, r6
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ADD32 r4, r2, r9
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ADD32 r6, r4, r12
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ANDI r1, r6, 4294967295d
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2: LI64 r1, 512d
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1: ADDI64 r254, r254, 12d
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JALA r0, r31, 0a
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code size: 387
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code size: 257
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ret: 512
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status: Ok(())
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@ -13,17 +13,8 @@ main:
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ADDI64 r254, r254, 24d
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JALA r0, r31, 0a
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set:
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ADDI64 r254, r254, -25d
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LI8 r7, 5b
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ST r7, r254, 0a, 1h
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ST r4, r254, 1a, 4h
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LI64 r11, 8d
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ST r11, r254, 5a, 4h
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ST r2, r254, 9a, 8h
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ST r3, r254, 17a, 8h
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LD r1, r254, 1a, 4h
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ADDI64 r254, r254, 25d
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CP r1, r4
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JALA r0, r31, 0a
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code size: 277
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code size: 167
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ret: 1024
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status: Ok(())
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@ -1,99 +1,37 @@
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main:
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ADDI64 r254, r254, -152d
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LI8 r1, 0b
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LI8 r3, 1b
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ST r1, r254, 116a, 1h
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ST r3, r254, 112a, 1h
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ST r1, r254, 117a, 1h
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ST r3, r254, 113a, 1h
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ST r1, r254, 118a, 1h
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ST r3, r254, 114a, 1h
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ST r1, r254, 119a, 1h
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ST r3, r254, 115a, 1h
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LD r1, r254, 116a, 1h
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LD r4, r254, 112a, 1h
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ADD8 r5, r4, r1
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LD r8, r254, 113a, 1h
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LD r9, r254, 117a, 1h
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ST r5, r254, 116a, 1h
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ADD8 r12, r9, r8
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LD r4, r254, 114a, 1h
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LD r5, r254, 118a, 1h
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ST r12, r254, 117a, 1h
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ADD8 r7, r5, r4
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ST r7, r254, 118a, 1h
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ST r3, r254, 119a, 1h
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LD r12, r254, 117a, 1h
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LD r1, r254, 118a, 1h
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ADD8 r4, r1, r12
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LD r5, r254, 116a, 1h
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ADD8 r7, r5, r4
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LI8 r9, 4b
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ADD8 r1, r7, r3
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ANDI r1, r1, 255d
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ANDI r9, r9, 255d
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JEQ r1, r9, :0
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LI64 r1, 1008d
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JMP :1
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0: LI64 r6, 1d
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ADDI64 r5, r254, 96d
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ST r6, r254, 96a, 8h
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LI64 r9, 2d
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ST r9, r254, 104a, 8h
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LI64 r2, 3d
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ADDI64 r1, r254, 80d
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ST r2, r254, 32a, 8h
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LI64 r6, 4d
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LI64 r2, 0d
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BMC r5, r1, 16h
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ST r6, r254, 40a, 8h
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ST r2, r254, 16a, 8h
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LD r11, r254, 80a, 8h
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LD r1, r254, 32a, 8h
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ST r2, r254, 24a, 8h
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ADD64 r4, r1, r11
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LD r7, r254, 88a, 8h
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LD r2, r254, 16a, 8h
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ST r4, r254, 120a, 8h
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ADD64 r12, r7, r6
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SUB64 r3, r2, r1
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ADDI64 r8, r254, 48d
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ST r12, r254, 128a, 8h
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SUB64 r2, r1, r11
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ADDI64 r254, r254, -64d
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LI64 r3, 1d
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ADDI64 r2, r254, 48d
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ST r3, r254, 48a, 8h
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LI64 r9, -4d
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ST r2, r254, 136a, 8h
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SUB64 r7, r6, r7
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ST r9, r254, 56a, 8h
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ADDI64 r8, r8, 16d
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ST r7, r254, 144a, 8h
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BMC r5, r8, 16h
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LD r6, r254, 120a, 8h
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LD r8, r254, 48a, 8h
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ADD64 r9, r8, r6
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LD r11, r254, 56a, 8h
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LD r1, r254, 128a, 8h
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ST r9, r254, 48a, 8h
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ADD64 r4, r1, r11
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LD r8, r254, 64a, 8h
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LD r9, r254, 136a, 8h
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ST r4, r254, 56a, 8h
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ADD64 r12, r9, r8
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LD r2, r254, 72a, 8h
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ST r12, r254, 64a, 8h
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ADD64 r12, r2, r7
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ST r12, r254, 72a, 8h
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LD r7, r254, 48a, 8h
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LD r9, r254, 64a, 8h
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ADD64 r11, r9, r7
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LD r1, r254, 56a, 8h
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ST r11, r254, 0a, 8h
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ADD64 r6, r1, r12
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LI64 r6, 2d
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ST r6, r254, 56a, 8h
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LI64 r6, -3d
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ADDI64 r5, r254, 0d
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ADDI64 r11, r254, 32d
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ST r6, r254, 0a, 8h
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LI64 r6, -4d
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BMC r2, r11, 16h
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ST r6, r254, 8a, 8h
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LD r7, r254, 0a, 8h
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ADD64 r1, r7, r6
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1: ADDI64 r254, r254, 152d
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ADDI64 r3, r5, 16d
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LD r9, r254, 40a, 8h
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LI64 r8, 4d
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LD r10, r254, 32a, 8h
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LI64 r11, 3d
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BMC r2, r3, 16h
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SUB64 r4, r8, r9
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LD r12, r254, 24a, 8h
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ADD64 r7, r10, r11
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LD r1, r254, 0a, 8h
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SUB64 r8, r11, r10
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LD r2, r254, 16a, 8h
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ADD64 r6, r12, r4
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ADD64 r3, r1, r7
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ADD64 r10, r2, r8
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ADD64 r12, r9, r6
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ADD64 r9, r10, r3
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ADD64 r1, r9, r12
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ADDI64 r254, r254, 64d
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JALA r0, r31, 0a
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code size: 980
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code size: 308
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ret: 10
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status: Ok(())
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@ -33,22 +33,19 @@ fib_iter:
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JMP :2
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1: JALA r0, r31, 0a
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main:
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ADDI64 r254, r254, -18d
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ST r31, r254, 2a, 16h
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LI8 r1, 10b
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ST r1, r254, 0a, 1h
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ST r1, r254, 1a, 1h
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LD r5, r254, 0a, 1h
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ANDI r2, r5, 255d
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ADDI64 r254, r254, -24d
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ST r31, r254, 0a, 24h
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LI64 r32, 10d
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CP r2, r32
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JAL r31, r0, :fib
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CP r32, r1
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LI64 r2, 10d
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CP r2, r32
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CP r33, r1
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JAL r31, r0, :fib_iter
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CP r4, r32
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SUB64 r1, r4, r1
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LD r31, r254, 2a, 16h
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ADDI64 r254, r254, 18d
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CP r9, r33
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SUB64 r1, r9, r1
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LD r31, r254, 0a, 24h
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ADDI64 r254, r254, 24d
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JALA r0, r31, 0a
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code size: 353
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code size: 306
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ret: 0
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status: Ok(())
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