Fixed some panics and some UB
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a7c4379976
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398687d8bf
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@ -80,17 +80,18 @@ where
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AND => self.binary_op::<u64>(ops::BitAnd::bitand),
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OR => self.binary_op::<u64>(ops::BitOr::bitor),
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XOR => self.binary_op::<u64>(ops::BitXor::bitxor),
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SLU8 => self.binary_op::<u8>(ops::Shl::shl),
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SLU16 => self.binary_op::<u16>(ops::Shl::shl),
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SLU32 => self.binary_op::<u32>(ops::Shl::shl),
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SLU64 => self.binary_op::<u64>(ops::Shl::shl),
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SRU8 => self.binary_op::<u8>(ops::Shr::shr),
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SRU16 => self.binary_op::<u16>(ops::Shr::shr),
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SRU32 => self.binary_op::<u32>(ops::Shr::shr),
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SRS8 => self.binary_op::<u64>(ops::Shr::shr),
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SRS16 => self.binary_op::<i8>(ops::Shr::shr),
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SRS32 => self.binary_op::<i16>(ops::Shr::shr),
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SRS64 => self.binary_op::<i64>(ops::Shr::shr),
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SLU8 => self.binary_op_shift::<u8>(u8::wrapping_shl),
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SLU16 => self.binary_op_shift::<u16>(u16::wrapping_shl),
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SLU32 => self.binary_op_shift::<u32>(u32::wrapping_shl),
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SLU64 => self.binary_op_shift::<u64>(u64::wrapping_shl),
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SRU8 => self.binary_op_shift::<u8>(u8::wrapping_shr),
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SRU16 => self.binary_op_shift::<u16>(u16::wrapping_shr),
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SRU32 => self.binary_op_shift::<u32>(u32::wrapping_shr),
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SRU64 => self.binary_op_shift::<u64>(u64::wrapping_shr),
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SRS8 => self.binary_op_shift::<i8>(i8::wrapping_shr),
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SRS16 => self.binary_op_shift::<i16>(i16::wrapping_shr),
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SRS32 => self.binary_op_shift::<i32>(i32::wrapping_shr),
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SRS64 => self.binary_op_shift::<i64>(i64::wrapping_shr),
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CMPU => handler!(self, |OpsRRR(tg, a0, a1)| self.cmp(
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tg,
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a0,
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@ -137,18 +138,18 @@ where
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ANDI => self.binary_op_imm::<u64>(ops::BitAnd::bitand),
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ORI => self.binary_op_imm::<u64>(ops::BitOr::bitor),
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XORI => self.binary_op_imm::<u64>(ops::BitXor::bitxor),
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SLUI8 => self.binary_op_ims::<u8>(ops::Shl::shl),
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SLUI16 => self.binary_op_ims::<u16>(ops::Shl::shl),
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SLUI32 => self.binary_op_ims::<u32>(ops::Shl::shl),
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SLUI64 => self.binary_op_ims::<u64>(ops::Shl::shl),
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SRUI8 => self.binary_op_ims::<u8>(ops::Shr::shr),
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SRUI16 => self.binary_op_ims::<u16>(ops::Shr::shr),
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SRUI32 => self.binary_op_ims::<u32>(ops::Shr::shr),
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SRUI64 => self.binary_op_ims::<u64>(ops::Shr::shr),
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SRSI8 => self.binary_op_ims::<i8>(ops::Shr::shr),
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SRSI16 => self.binary_op_ims::<i16>(ops::Shr::shr),
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SRSI32 => self.binary_op_ims::<i32>(ops::Shr::shr),
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SRSI64 => self.binary_op_ims::<i64>(ops::Shr::shr),
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SLUI8 => self.binary_op_ims::<u8>(u8::wrapping_shl),
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SLUI16 => self.binary_op_ims::<u16>(u16::wrapping_shl),
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SLUI32 => self.binary_op_ims::<u32>(u32::wrapping_shl),
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SLUI64 => self.binary_op_ims::<u64>(u64::wrapping_shl),
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SRUI8 => self.binary_op_ims::<u8>(u8::wrapping_shr),
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SRUI16 => self.binary_op_ims::<u16>(u16::wrapping_shr),
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SRUI32 => self.binary_op_ims::<u32>(u32::wrapping_shr),
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SRUI64 => self.binary_op_ims::<u64>(u64::wrapping_shr),
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SRSI8 => self.binary_op_ims::<i8>(i8::wrapping_shr),
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SRSI16 => self.binary_op_ims::<i16>(i16::wrapping_shr),
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SRSI32 => self.binary_op_ims::<i32>(i32::wrapping_shr),
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SRSI64 => self.binary_op_ims::<i64>(i64::wrapping_shr),
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CMPUI => handler!(self, |OpsRRD(tg, a0, imm)| { self.cmp(tg, a0, imm) }),
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CMPSI => handler!(self, |OpsRRD(tg, a0, imm)| { self.cmp(tg, a0, imm as i64) }),
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CP => handler!(self, |OpsRR(tg, a0)| self.write_reg(tg, self.read_reg(a0))),
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@ -404,7 +405,7 @@ where
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.as_mut_ptr()
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.add(usize::from(dst) + usize::from(n))
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.cast(),
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usize::from(count).wrapping_sub(n.into()),
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usize::from(count).saturating_sub(n.into()),
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)?;
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Ok(())
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@ -456,9 +457,23 @@ where
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/// Perform binary operation over register and shift immediate
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#[inline(always)]
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unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u8) -> T) {
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unsafe fn binary_op_shift<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
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let OpsRRR(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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op(
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self.read_reg(a0).cast::<T>(),
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self.read_reg(a1).cast::<u32>(),
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),
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);
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self.bump_pc::<OpsRRR, true>();
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}
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/// Perform binary operation over register and shift immediate
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#[inline(always)]
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unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
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let OpsRRB(tg, reg, imm) = self.decode();
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self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm));
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self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm.into()));
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self.bump_pc::<OpsRRW, true>();
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}
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