restruct + no-alloc support
This commit is contained in:
parent
f2ec9a3034
commit
6588837769
1
Cargo.lock
generated
1
Cargo.lock
generated
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@ -126,7 +126,6 @@ version = "0.1.0"
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dependencies = [
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"delegate",
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"derive_more",
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"hashbrown 0.13.2",
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"hbbytecode",
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"log",
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"paste",
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@ -6,10 +6,13 @@ edition = "2021"
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[profile.release]
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lto = true
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[features]
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default = ["alloc"]
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alloc = []
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[dependencies]
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delegate = "0.9"
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derive_more = "0.99"
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hashbrown = "0.13"
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hbbytecode.path = "../hbbytecode"
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log = "0.4"
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paste = "1.0"
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@ -1,7 +1,7 @@
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#![no_main]
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use {
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hbvm::vm::{
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hbvm::{
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mem::{HandlePageFault, Memory, MemoryAccessReason, PageSize},
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Vm,
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},
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@ -9,7 +9,7 @@ use {
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};
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fuzz_target!(|data: &[u8]| {
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if let Ok(mut vm) = Vm::<_, 0>::new_validated(data, TestTrapHandler) {
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if let Ok(mut vm) = Vm::<_, 0>::new_validated(data, TestTrapHandler, Default::default()) {
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let _ = vm.run();
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}
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});
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456
hbvm/src/lib.rs
456
hbvm/src/lib.rs
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@ -1,6 +1,458 @@
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#![doc = include_str!("../README.md")]
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//! HoleyBytes Virtual Machine
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//!
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//! # Alloc feature
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//! - Enabled by default
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//! - Provides [`mem::Memory`] mapping / unmapping, as well as
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//! [`Default`] and [`Drop`] implementation
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// # General safety notice:
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// - Validation has to assure there is 256 registers (r0 - r255)
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// - Instructions have to be valid as specified (values and sizes)
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// - Mapped pages should be at least 4 KiB
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#![no_std]
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#[cfg(feature = "alloc")]
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extern crate alloc;
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pub mod vm;
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pub mod mem;
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pub mod value;
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use {
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self::{mem::HandlePageFault, value::ValueVariant},
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core::{cmp::Ordering, ops},
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hbbytecode::{
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valider, OpParam, ParamBB, ParamBBB, ParamBBBB, ParamBBD, ParamBBDH, ParamBBW, ParamBD,
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},
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mem::Memory,
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value::Value,
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};
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/// HoleyBytes Virtual Machine
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pub struct Vm<'a, PfHandler, const TIMER_QUOTIENT: usize> {
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/// Holds 256 registers
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///
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/// Writing to register 0 is considered undefined behaviour
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/// in terms of HoleyBytes program execution
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pub registers: [Value; 256],
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/// Memory implementation
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pub memory: Memory,
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/// Trap handler
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pub pfhandler: PfHandler,
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/// Program counter
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pub pc: usize,
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/// Program
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program: &'a [u8],
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/// Cached program length (without unreachable end)
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program_len: usize,
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/// Program timer
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timer: usize,
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}
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impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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Vm<'a, PfHandler, TIMER_QUOTIENT>
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{
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/// Create a new VM with program and trap handler
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///
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/// # Safety
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/// Program code has to be validated
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pub unsafe fn new_unchecked(program: &'a [u8], traph: PfHandler, memory: Memory) -> Self {
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Self {
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registers: [Value::from(0_u64); 256],
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memory,
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pfhandler: traph,
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pc: 0,
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program_len: program.len() - 12,
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program,
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timer: 0,
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}
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}
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/// Create a new VM with program and trap handler only if it passes validation
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pub fn new_validated(
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program: &'a [u8],
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traph: PfHandler,
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memory: Memory,
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) -> Result<Self, valider::Error> {
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valider::validate(program)?;
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Ok(unsafe { Self::new_unchecked(program, traph, memory) })
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}
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/// Execute program
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///
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/// Program can return [`VmRunError`] if a trap handling failed
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pub fn run(&mut self) -> Result<VmRunOk, VmRunError> {
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use hbbytecode::opcode::*;
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loop {
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// Check instruction boundary
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if self.pc >= self.program_len {
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return Ok(VmRunOk::End);
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}
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// Big match
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//
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// Contribution guide:
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// - Zero register shall never be overwitten. It's value has to always be 0.
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// - Prefer `Self::read_reg` and `Self::write_reg` functions
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// - Extract parameters using `param!` macro
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// - Prioritise speed over code size
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// - Memory is cheap, CPUs not that much
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// - Do not heap allocate at any cost
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// - Yes, user-provided trap handler may allocate,
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// but that is not our »fault«.
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// - Unsafe is kinda must, but be sure you have validated everything
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// - Your contributions have to pass sanitizers and Miri
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// - Strictly follow the spec
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// - The spec does not specify how you perform actions, in what order,
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// just that the observable effects have to be performed in order and
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// correctly.
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// - Yes, we assume you run 64 bit CPU. Else ?conradluget a better CPU
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// sorry 8 bit fans, HBVM won't run on your Speccy :(
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unsafe {
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match *self.program.get_unchecked(self.pc) {
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UN => {
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self.decode::<()>();
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return Err(VmRunError::Unreachable);
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}
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NOP => self.decode::<()>(),
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ADD => self.binary_op(u64::wrapping_add),
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SUB => self.binary_op(u64::wrapping_sub),
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MUL => self.binary_op(u64::wrapping_mul),
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AND => self.binary_op::<u64>(ops::BitAnd::bitand),
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OR => self.binary_op::<u64>(ops::BitOr::bitor),
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XOR => self.binary_op::<u64>(ops::BitXor::bitxor),
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SL => self.binary_op(|l, r| u64::wrapping_shl(l, r as u32)),
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SR => self.binary_op(|l, r| u64::wrapping_shr(l, r as u32)),
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SRS => self.binary_op(|l, r| i64::wrapping_shl(l, r as u32)),
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CMP => {
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// Compare a0 <=> a1
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// < → -1
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// > → 1
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// = → 0
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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.cast::<i64>()
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.cmp(&self.read_reg(a1).cast::<i64>())
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as i64,
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);
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}
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CMPU => {
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// Unsigned comparsion
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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.cast::<u64>()
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.cmp(&self.read_reg(a1).cast::<u64>())
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as i64,
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);
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}
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NOT => {
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// Logical negation
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(tg, !self.read_reg(a0).cast::<u64>());
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}
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NEG => {
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// Bitwise negation
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(
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tg,
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match self.read_reg(a0).cast::<u64>() {
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0 => 1_u64,
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_ => 0,
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},
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);
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}
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DIR => {
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// Fused Division-Remainder
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let ParamBBBB(dt, rt, a0, a1) = self.decode();
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let a0 = self.read_reg(a0).cast::<u64>();
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let a1 = self.read_reg(a1).cast::<u64>();
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self.write_reg(dt, a0.checked_div(a1).unwrap_or(u64::MAX));
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self.write_reg(rt, a0.checked_rem(a1).unwrap_or(u64::MAX));
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}
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ADDI => self.binary_op_imm(u64::wrapping_add),
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MULI => self.binary_op_imm(u64::wrapping_sub),
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ANDI => self.binary_op_imm::<u64>(ops::BitAnd::bitand),
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ORI => self.binary_op_imm::<u64>(ops::BitOr::bitor),
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XORI => self.binary_op_imm::<u64>(ops::BitXor::bitxor),
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SLI => self.binary_op_ims(u64::wrapping_shl),
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SRI => self.binary_op_ims(u64::wrapping_shr),
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SRSI => self.binary_op_ims(i64::wrapping_shr),
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CMPI => {
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let ParamBBD(tg, a0, imm) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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.cast::<i64>()
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.cmp(&Value::from(imm).cast::<i64>())
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as i64,
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);
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}
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CMPUI => {
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let ParamBBD(tg, a0, imm) = self.decode();
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self.write_reg(tg, self.read_reg(a0).cast::<u64>().cmp(&imm) as i64);
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}
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CP => {
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(tg, self.read_reg(a0));
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}
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SWA => {
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// Swap registers
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let ParamBB(r0, r1) = self.decode();
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match (r0, r1) {
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(0, 0) => (),
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(dst, 0) | (0, dst) => self.write_reg(dst, 0_u64),
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(r0, r1) => {
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core::ptr::swap(
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self.registers.get_unchecked_mut(usize::from(r0)),
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self.registers.get_unchecked_mut(usize::from(r1)),
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);
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}
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}
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}
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LI => {
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let ParamBD(tg, imm) = self.decode();
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self.write_reg(tg, imm);
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}
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LD => {
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// Load. If loading more than register size, continue on adjecent registers
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let ParamBBDH(dst, base, off, count) = self.decode();
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ldst_bound_check(dst, count)?;
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let n: usize = match dst {
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0 => 1,
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_ => 0,
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};
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self.memory.load(
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self.read_reg(base).cast::<u64>() + off + n as u64,
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self.registers.as_mut_ptr().add(usize::from(dst) + n).cast(),
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usize::from(count).saturating_sub(n),
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&mut self.pfhandler,
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)?;
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}
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ST => {
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// Store. Same rules apply as to LD
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let ParamBBDH(dst, base, off, count) = self.decode();
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ldst_bound_check(dst, count)?;
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self.memory.store(
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self.read_reg(base).cast::<u64>() + off,
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self.registers.as_ptr().add(usize::from(dst)).cast(),
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count.into(),
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&mut self.pfhandler,
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)?;
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}
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BMC => {
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// Block memory copy
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let ParamBBD(src, dst, count) = self.decode();
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self.memory.block_copy(
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self.read_reg(src).cast::<u64>(),
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self.read_reg(dst).cast::<u64>(),
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count as _,
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&mut self.pfhandler,
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)?;
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}
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BRC => {
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// Block register copy
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let ParamBBB(src, dst, count) = self.decode();
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if src.checked_add(count).is_none() || dst.checked_add(count).is_none() {
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return Err(VmRunError::RegOutOfBounds);
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}
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core::ptr::copy(
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self.registers.get_unchecked(usize::from(src)),
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self.registers.get_unchecked_mut(usize::from(dst)),
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usize::from(count),
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);
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}
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JAL => {
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// Jump and link. Save PC after this instruction to
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// specified register and jump to reg + offset.
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let ParamBBD(save, reg, offset) = self.decode();
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self.write_reg(save, self.pc as u64);
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self.pc = (self.read_reg(reg).cast::<u64>() + offset) as usize;
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}
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// Conditional jumps, jump only to immediates
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JEQ => self.cond_jmp::<u64>(Ordering::Equal),
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JNE => {
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let ParamBBD(a0, a1, jt) = self.decode();
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if self.read_reg(a0).cast::<u64>() != self.read_reg(a1).cast::<u64>() {
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self.pc = jt as usize;
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}
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}
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JLT => self.cond_jmp::<u64>(Ordering::Less),
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JGT => self.cond_jmp::<u64>(Ordering::Greater),
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JLTU => self.cond_jmp::<i64>(Ordering::Less),
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JGTU => self.cond_jmp::<i64>(Ordering::Greater),
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ECALL => {
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self.decode::<()>();
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// So we don't get timer interrupt after ECALL
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if TIMER_QUOTIENT != 0 {
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self.timer = self.timer.wrapping_add(1);
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}
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return Ok(VmRunOk::Ecall);
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}
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ADDF => self.binary_op::<f64>(ops::Add::add),
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SUBF => self.binary_op::<f64>(ops::Sub::sub),
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MULF => self.binary_op::<f64>(ops::Mul::mul),
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DIRF => {
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let ParamBBBB(dt, rt, a0, a1) = self.decode();
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let a0 = self.read_reg(a0).cast::<f64>();
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let a1 = self.read_reg(a1).cast::<f64>();
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self.write_reg(dt, a0 / a1);
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self.write_reg(rt, a0 % a1);
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}
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FMAF => {
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let ParamBBBB(dt, a0, a1, a2) = self.decode();
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self.write_reg(
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dt,
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self.read_reg(a0).cast::<f64>() * self.read_reg(a1).cast::<f64>()
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+ self.read_reg(a2).cast::<f64>(),
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);
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}
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NEGF => {
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let ParamBB(dt, a0) = self.decode();
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self.write_reg(dt, -self.read_reg(a0).cast::<f64>());
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}
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ITF => {
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let ParamBB(dt, a0) = self.decode();
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self.write_reg(dt, self.read_reg(a0).cast::<i64>() as f64);
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}
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FTI => {
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let ParamBB(dt, a0) = self.decode();
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self.write_reg(dt, self.read_reg(a0).cast::<f64>() as i64);
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}
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ADDFI => self.binary_op_imm::<f64>(ops::Add::add),
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MULFI => self.binary_op_imm::<f64>(ops::Mul::mul),
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op => return Err(VmRunError::InvalidOpcode(op)),
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}
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}
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if TIMER_QUOTIENT != 0 {
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self.timer = self.timer.wrapping_add(1);
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if self.timer % TIMER_QUOTIENT == 0 {
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return Ok(VmRunOk::Timer);
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}
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}
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}
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}
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/// Decode instruction operands
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#[inline]
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unsafe fn decode<T: OpParam>(&mut self) -> T {
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let data = self.program.as_ptr().add(self.pc + 1).cast::<T>().read();
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self.pc += 1 + core::mem::size_of::<T>();
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data
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}
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/// Perform binary operating over two registers
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#[inline]
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unsafe fn binary_op<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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op(self.read_reg(a0).cast::<T>(), self.read_reg(a1).cast::<T>()),
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);
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}
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/// Perform binary operation over register and immediate
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#[inline]
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unsafe fn binary_op_imm<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
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let ParamBBD(tg, reg, imm) = self.decode();
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self.write_reg(
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tg,
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op(self.read_reg(reg).cast::<T>(), Value::from(imm).cast::<T>()),
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);
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}
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/// Perform binary operation over register and shift immediate
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#[inline]
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unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
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let ParamBBW(tg, reg, imm) = self.decode();
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self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm));
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}
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/// Jump at `#3` if ordering on `#0 <=> #1` is equal to expected
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#[inline]
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unsafe fn cond_jmp<T: ValueVariant + Ord>(&mut self, expected: Ordering) {
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let ParamBBD(a0, a1, ja) = self.decode();
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if self
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.read_reg(a0)
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.cast::<T>()
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.cmp(&self.read_reg(a1).cast::<T>())
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== expected
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{
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self.pc = ja as usize;
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}
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}
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/// Read register
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#[inline]
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unsafe fn read_reg(&self, n: u8) -> Value {
|
||||
*self.registers.get_unchecked(n as usize)
|
||||
}
|
||||
|
||||
/// Write a register.
|
||||
/// Writing to register 0 is no-op.
|
||||
#[inline]
|
||||
unsafe fn write_reg(&mut self, n: u8, value: impl Into<Value>) {
|
||||
if n != 0 {
|
||||
*self.registers.get_unchecked_mut(n as usize) = value.into();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Load/Store target/source register range bound checking
|
||||
#[inline]
|
||||
fn ldst_bound_check(reg: u8, size: u16) -> Result<(), VmRunError> {
|
||||
if usize::from(reg) * 8 + usize::from(size) > 2048 {
|
||||
Err(VmRunError::RegOutOfBounds)
|
||||
} else {
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
/// Virtual machine halt error
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[repr(u8)]
|
||||
pub enum VmRunError {
|
||||
/// Tried to execute invalid instruction
|
||||
InvalidOpcode(u8),
|
||||
|
||||
/// Unhandled load access exception
|
||||
LoadAccessEx(u64),
|
||||
|
||||
/// Unhandled store access exception
|
||||
StoreAccessEx(u64),
|
||||
|
||||
/// Register out-of-bounds access
|
||||
RegOutOfBounds,
|
||||
|
||||
/// Reached unreachable code
|
||||
Unreachable,
|
||||
}
|
||||
|
||||
/// Virtual machine halt ok
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
pub enum VmRunOk {
|
||||
/// Program has eached its end
|
||||
End,
|
||||
|
||||
/// Program was interrupted by a timer
|
||||
Timer,
|
||||
|
||||
/// Environment call
|
||||
Ecall,
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
use hbvm::vm::mem::{HandlePageFault, Memory, MemoryAccessReason, PageSize};
|
||||
|
||||
use {
|
||||
hbbytecode::valider::validate,
|
||||
hbvm::vm::Vm,
|
||||
hbvm::{
|
||||
mem::{HandlePageFault, Memory, MemoryAccessReason, PageSize},
|
||||
Vm,
|
||||
},
|
||||
std::io::{stdin, Read},
|
||||
};
|
||||
|
||||
|
|
@ -15,7 +16,7 @@ fn main() -> Result<(), Box<dyn std::error::Error>> {
|
|||
return Ok(());
|
||||
} else {
|
||||
unsafe {
|
||||
let mut vm = Vm::<_, 0>::new_unchecked(&prog, TestTrapHandler);
|
||||
let mut vm = Vm::<_, 0>::new_unchecked(&prog, TestTrapHandler, Default::default());
|
||||
let data = {
|
||||
let ptr = std::alloc::alloc_zeroed(std::alloc::Layout::from_size_align_unchecked(
|
||||
4096, 4096,
|
||||
|
|
@ -30,7 +31,7 @@ fn main() -> Result<(), Box<dyn std::error::Error>> {
|
|||
.map(
|
||||
data,
|
||||
0,
|
||||
hbvm::vm::mem::paging::Permission::Write,
|
||||
hbvm::mem::paging::Permission::Write,
|
||||
PageSize::Size4K,
|
||||
)
|
||||
.unwrap();
|
||||
|
|
|
|||
|
|
@ -7,28 +7,32 @@ mod pfhandler;
|
|||
pub use pfhandler::HandlePageFault;
|
||||
|
||||
use {
|
||||
self::paging::{PageTable, Permission, PtEntry},
|
||||
super::VmRunError,
|
||||
alloc::boxed::Box,
|
||||
core::mem::MaybeUninit,
|
||||
derive_more::Display,
|
||||
paging::{PageTable, Permission},
|
||||
};
|
||||
|
||||
#[cfg(feature = "alloc")]
|
||||
use {alloc::boxed::Box, paging::PtEntry};
|
||||
|
||||
/// HoleyBytes virtual memory
|
||||
#[derive(Clone, Debug)]
|
||||
pub struct Memory {
|
||||
/// Root page table
|
||||
root_pt: *mut PageTable,
|
||||
pub root_pt: *mut PageTable,
|
||||
}
|
||||
|
||||
#[cfg(feature = "alloc")]
|
||||
impl Default for Memory {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
root_pt: Box::into_raw(Box::default()),
|
||||
root_pt: Box::into_raw(Default::default()),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(feature = "alloc")]
|
||||
impl Drop for Memory {
|
||||
fn drop(&mut self) {
|
||||
let _ = unsafe { Box::from_raw(self.root_pt) };
|
||||
|
|
@ -42,6 +46,7 @@ impl Memory {
|
|||
/// - Your faith in the gods of UB
|
||||
/// - Addr-san claims it's fine but who knows is she isn't lying :ferrisSus:
|
||||
/// - Alright, Miri-sama is also fine with this, who knows why
|
||||
#[cfg(feature = "alloc")]
|
||||
pub unsafe fn map(
|
||||
&mut self,
|
||||
host: *mut u8,
|
||||
|
|
@ -107,6 +112,7 @@ impl Memory {
|
|||
///
|
||||
/// If errors, it only means there is no entry to unmap and in most cases
|
||||
/// just should be ignored.
|
||||
#[cfg(feature = "alloc")]
|
||||
pub fn unmap(&mut self, addr: u64) -> Result<(), NothingToUnmap> {
|
||||
let mut current_pt = self.root_pt;
|
||||
let mut page_tables = [core::ptr::null_mut(); 5];
|
||||
|
|
@ -1,446 +0,0 @@
|
|||
//! HoleyBytes Virtual Machine
|
||||
//!
|
||||
//! All unsafe code here should be sound, if input bytecode passes validation.
|
||||
|
||||
// # General safety notice:
|
||||
// - Validation has to assure there is 256 registers (r0 - r255)
|
||||
// - Instructions have to be valid as specified (values and sizes)
|
||||
// - Mapped pages should be at least 4 KiB
|
||||
|
||||
pub mod mem;
|
||||
pub mod value;
|
||||
|
||||
use {
|
||||
self::{mem::HandlePageFault, value::ValueVariant},
|
||||
core::{cmp::Ordering, ops},
|
||||
hbbytecode::{
|
||||
valider, OpParam, ParamBB, ParamBBB, ParamBBBB, ParamBBD, ParamBBDH, ParamBBW, ParamBD,
|
||||
},
|
||||
mem::Memory,
|
||||
value::Value,
|
||||
};
|
||||
|
||||
/// HoleyBytes Virtual Machine
|
||||
pub struct Vm<'a, PfHandler, const TIMER_QUOTIENT: usize> {
|
||||
/// Holds 256 registers
|
||||
///
|
||||
/// Writing to register 0 is considered undefined behaviour
|
||||
/// in terms of HoleyBytes program execution
|
||||
pub registers: [Value; 256],
|
||||
|
||||
/// Memory implementation
|
||||
pub memory: Memory,
|
||||
|
||||
/// Trap handler
|
||||
pub pfhandler: PfHandler,
|
||||
|
||||
/// Program counter
|
||||
pub pc: usize,
|
||||
|
||||
/// Program
|
||||
program: &'a [u8],
|
||||
|
||||
/// Cached program length (without unreachable end)
|
||||
program_len: usize,
|
||||
|
||||
/// Program timer
|
||||
timer: usize,
|
||||
}
|
||||
|
||||
impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
|
||||
Vm<'a, PfHandler, TIMER_QUOTIENT>
|
||||
{
|
||||
/// Create a new VM with program and trap handler
|
||||
///
|
||||
/// # Safety
|
||||
/// Program code has to be validated
|
||||
pub unsafe fn new_unchecked(program: &'a [u8], traph: PfHandler) -> Self {
|
||||
Self {
|
||||
registers: [Value::from(0_u64); 256],
|
||||
memory: Default::default(),
|
||||
pfhandler: traph,
|
||||
pc: 0,
|
||||
program_len: program.len() - 12,
|
||||
program,
|
||||
timer: 0,
|
||||
}
|
||||
}
|
||||
|
||||
/// Create a new VM with program and trap handler only if it passes validation
|
||||
pub fn new_validated(program: &'a [u8], traph: PfHandler) -> Result<Self, valider::Error> {
|
||||
valider::validate(program)?;
|
||||
Ok(unsafe { Self::new_unchecked(program, traph) })
|
||||
}
|
||||
|
||||
/// Execute program
|
||||
///
|
||||
/// Program can return [`VmRunError`] if a trap handling failed
|
||||
pub fn run(&mut self) -> Result<VmRunOk, VmRunError> {
|
||||
use hbbytecode::opcode::*;
|
||||
loop {
|
||||
// Check instruction boundary
|
||||
if self.pc >= self.program_len {
|
||||
return Ok(VmRunOk::End);
|
||||
}
|
||||
|
||||
// Big match
|
||||
//
|
||||
// Contribution guide:
|
||||
// - Zero register shall never be overwitten. It's value has to always be 0.
|
||||
// - Prefer `Self::read_reg` and `Self::write_reg` functions
|
||||
// - Extract parameters using `param!` macro
|
||||
// - Prioritise speed over code size
|
||||
// - Memory is cheap, CPUs not that much
|
||||
// - Do not heap allocate at any cost
|
||||
// - Yes, user-provided trap handler may allocate,
|
||||
// but that is not our »fault«.
|
||||
// - Unsafe is kinda must, but be sure you have validated everything
|
||||
// - Your contributions have to pass sanitizers and Miri
|
||||
// - Strictly follow the spec
|
||||
// - The spec does not specify how you perform actions, in what order,
|
||||
// just that the observable effects have to be performed in order and
|
||||
// correctly.
|
||||
// - Yes, we assume you run 64 bit CPU. Else ?conradluget a better CPU
|
||||
// sorry 8 bit fans, HBVM won't run on your Speccy :(
|
||||
unsafe {
|
||||
match *self.program.get_unchecked(self.pc) {
|
||||
UN => {
|
||||
self.decode::<()>();
|
||||
return Err(VmRunError::Unreachable);
|
||||
}
|
||||
NOP => self.decode::<()>(),
|
||||
ADD => self.binary_op(u64::wrapping_add),
|
||||
SUB => self.binary_op(u64::wrapping_sub),
|
||||
MUL => self.binary_op(u64::wrapping_mul),
|
||||
AND => self.binary_op::<u64>(ops::BitAnd::bitand),
|
||||
OR => self.binary_op::<u64>(ops::BitOr::bitor),
|
||||
XOR => self.binary_op::<u64>(ops::BitXor::bitxor),
|
||||
SL => self.binary_op(|l, r| u64::wrapping_shl(l, r as u32)),
|
||||
SR => self.binary_op(|l, r| u64::wrapping_shr(l, r as u32)),
|
||||
SRS => self.binary_op(|l, r| i64::wrapping_shl(l, r as u32)),
|
||||
CMP => {
|
||||
// Compare a0 <=> a1
|
||||
// < → -1
|
||||
// > → 1
|
||||
// = → 0
|
||||
|
||||
let ParamBBB(tg, a0, a1) = self.decode();
|
||||
self.write_reg(
|
||||
tg,
|
||||
self.read_reg(a0)
|
||||
.cast::<i64>()
|
||||
.cmp(&self.read_reg(a1).cast::<i64>())
|
||||
as i64,
|
||||
);
|
||||
}
|
||||
CMPU => {
|
||||
// Unsigned comparsion
|
||||
let ParamBBB(tg, a0, a1) = self.decode();
|
||||
self.write_reg(
|
||||
tg,
|
||||
self.read_reg(a0)
|
||||
.cast::<u64>()
|
||||
.cmp(&self.read_reg(a1).cast::<u64>())
|
||||
as i64,
|
||||
);
|
||||
}
|
||||
NOT => {
|
||||
// Logical negation
|
||||
let ParamBB(tg, a0) = self.decode();
|
||||
self.write_reg(tg, !self.read_reg(a0).cast::<u64>());
|
||||
}
|
||||
NEG => {
|
||||
// Bitwise negation
|
||||
let ParamBB(tg, a0) = self.decode();
|
||||
self.write_reg(
|
||||
tg,
|
||||
match self.read_reg(a0).cast::<u64>() {
|
||||
0 => 1_u64,
|
||||
_ => 0,
|
||||
},
|
||||
);
|
||||
}
|
||||
DIR => {
|
||||
// Fused Division-Remainder
|
||||
let ParamBBBB(dt, rt, a0, a1) = self.decode();
|
||||
let a0 = self.read_reg(a0).cast::<u64>();
|
||||
let a1 = self.read_reg(a1).cast::<u64>();
|
||||
self.write_reg(dt, a0.checked_div(a1).unwrap_or(u64::MAX));
|
||||
self.write_reg(rt, a0.checked_rem(a1).unwrap_or(u64::MAX));
|
||||
}
|
||||
ADDI => self.binary_op_imm(u64::wrapping_add),
|
||||
MULI => self.binary_op_imm(u64::wrapping_sub),
|
||||
ANDI => self.binary_op_imm::<u64>(ops::BitAnd::bitand),
|
||||
ORI => self.binary_op_imm::<u64>(ops::BitOr::bitor),
|
||||
XORI => self.binary_op_imm::<u64>(ops::BitXor::bitxor),
|
||||
SLI => self.binary_op_ims(u64::wrapping_shl),
|
||||
SRI => self.binary_op_ims(u64::wrapping_shr),
|
||||
SRSI => self.binary_op_ims(i64::wrapping_shr),
|
||||
CMPI => {
|
||||
let ParamBBD(tg, a0, imm) = self.decode();
|
||||
self.write_reg(
|
||||
tg,
|
||||
self.read_reg(a0)
|
||||
.cast::<i64>()
|
||||
.cmp(&Value::from(imm).cast::<i64>())
|
||||
as i64,
|
||||
);
|
||||
}
|
||||
CMPUI => {
|
||||
let ParamBBD(tg, a0, imm) = self.decode();
|
||||
self.write_reg(tg, self.read_reg(a0).cast::<u64>().cmp(&imm) as i64);
|
||||
}
|
||||
CP => {
|
||||
let ParamBB(tg, a0) = self.decode();
|
||||
self.write_reg(tg, self.read_reg(a0));
|
||||
}
|
||||
SWA => {
|
||||
// Swap registers
|
||||
let ParamBB(r0, r1) = self.decode();
|
||||
match (r0, r1) {
|
||||
(0, 0) => (),
|
||||
(dst, 0) | (0, dst) => self.write_reg(dst, 0_u64),
|
||||
(r0, r1) => {
|
||||
core::ptr::swap(
|
||||
self.registers.get_unchecked_mut(usize::from(r0)),
|
||||
self.registers.get_unchecked_mut(usize::from(r1)),
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
LI => {
|
||||
let ParamBD(tg, imm) = self.decode();
|
||||
self.write_reg(tg, imm);
|
||||
}
|
||||
LD => {
|
||||
// Load. If loading more than register size, continue on adjecent registers
|
||||
let ParamBBDH(dst, base, off, count) = self.decode();
|
||||
ldst_bound_check(dst, count)?;
|
||||
|
||||
let n: usize = match dst {
|
||||
0 => 1,
|
||||
_ => 0,
|
||||
};
|
||||
|
||||
self.memory.load(
|
||||
self.read_reg(base).cast::<u64>() + off + n as u64,
|
||||
self.registers.as_mut_ptr().add(usize::from(dst) + n).cast(),
|
||||
usize::from(count).saturating_sub(n),
|
||||
&mut self.pfhandler,
|
||||
)?;
|
||||
}
|
||||
ST => {
|
||||
// Store. Same rules apply as to LD
|
||||
let ParamBBDH(dst, base, off, count) = self.decode();
|
||||
ldst_bound_check(dst, count)?;
|
||||
|
||||
self.memory.store(
|
||||
self.read_reg(base).cast::<u64>() + off,
|
||||
self.registers.as_ptr().add(usize::from(dst)).cast(),
|
||||
count.into(),
|
||||
&mut self.pfhandler,
|
||||
)?;
|
||||
}
|
||||
BMC => {
|
||||
// Block memory copy
|
||||
let ParamBBD(src, dst, count) = self.decode();
|
||||
self.memory.block_copy(
|
||||
self.read_reg(src).cast::<u64>(),
|
||||
self.read_reg(dst).cast::<u64>(),
|
||||
count as _,
|
||||
&mut self.pfhandler,
|
||||
)?;
|
||||
}
|
||||
BRC => {
|
||||
// Block register copy
|
||||
let ParamBBB(src, dst, count) = self.decode();
|
||||
if src.checked_add(count).is_none() || dst.checked_add(count).is_none() {
|
||||
return Err(VmRunError::RegOutOfBounds);
|
||||
}
|
||||
|
||||
core::ptr::copy(
|
||||
self.registers.get_unchecked(usize::from(src)),
|
||||
self.registers.get_unchecked_mut(usize::from(dst)),
|
||||
usize::from(count),
|
||||
);
|
||||
}
|
||||
JAL => {
|
||||
// Jump and link. Save PC after this instruction to
|
||||
// specified register and jump to reg + offset.
|
||||
let ParamBBD(save, reg, offset) = self.decode();
|
||||
self.write_reg(save, self.pc as u64);
|
||||
self.pc = (self.read_reg(reg).cast::<u64>() + offset) as usize;
|
||||
}
|
||||
// Conditional jumps, jump only to immediates
|
||||
JEQ => self.cond_jmp::<u64>(Ordering::Equal),
|
||||
JNE => {
|
||||
let ParamBBD(a0, a1, jt) = self.decode();
|
||||
if self.read_reg(a0).cast::<u64>() != self.read_reg(a1).cast::<u64>() {
|
||||
self.pc = jt as usize;
|
||||
}
|
||||
}
|
||||
JLT => self.cond_jmp::<u64>(Ordering::Less),
|
||||
JGT => self.cond_jmp::<u64>(Ordering::Greater),
|
||||
JLTU => self.cond_jmp::<i64>(Ordering::Less),
|
||||
JGTU => self.cond_jmp::<i64>(Ordering::Greater),
|
||||
ECALL => {
|
||||
self.decode::<()>();
|
||||
|
||||
// So we don't get timer interrupt after ECALL
|
||||
if TIMER_QUOTIENT != 0 {
|
||||
self.timer = self.timer.wrapping_add(1);
|
||||
}
|
||||
return Ok(VmRunOk::Ecall);
|
||||
}
|
||||
ADDF => self.binary_op::<f64>(ops::Add::add),
|
||||
SUBF => self.binary_op::<f64>(ops::Sub::sub),
|
||||
MULF => self.binary_op::<f64>(ops::Mul::mul),
|
||||
DIRF => {
|
||||
let ParamBBBB(dt, rt, a0, a1) = self.decode();
|
||||
let a0 = self.read_reg(a0).cast::<f64>();
|
||||
let a1 = self.read_reg(a1).cast::<f64>();
|
||||
self.write_reg(dt, a0 / a1);
|
||||
self.write_reg(rt, a0 % a1);
|
||||
}
|
||||
FMAF => {
|
||||
let ParamBBBB(dt, a0, a1, a2) = self.decode();
|
||||
self.write_reg(
|
||||
dt,
|
||||
self.read_reg(a0).cast::<f64>() * self.read_reg(a1).cast::<f64>()
|
||||
+ self.read_reg(a2).cast::<f64>(),
|
||||
);
|
||||
}
|
||||
NEGF => {
|
||||
let ParamBB(dt, a0) = self.decode();
|
||||
self.write_reg(dt, -self.read_reg(a0).cast::<f64>());
|
||||
}
|
||||
ITF => {
|
||||
let ParamBB(dt, a0) = self.decode();
|
||||
self.write_reg(dt, self.read_reg(a0).cast::<i64>() as f64);
|
||||
}
|
||||
FTI => {
|
||||
let ParamBB(dt, a0) = self.decode();
|
||||
self.write_reg(dt, self.read_reg(a0).cast::<f64>() as i64);
|
||||
}
|
||||
ADDFI => self.binary_op_imm::<f64>(ops::Add::add),
|
||||
MULFI => self.binary_op_imm::<f64>(ops::Mul::mul),
|
||||
op => return Err(VmRunError::InvalidOpcode(op)),
|
||||
}
|
||||
}
|
||||
|
||||
if TIMER_QUOTIENT != 0 {
|
||||
self.timer = self.timer.wrapping_add(1);
|
||||
if self.timer % TIMER_QUOTIENT == 0 {
|
||||
return Ok(VmRunOk::Timer);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Decode instruction operands
|
||||
#[inline]
|
||||
unsafe fn decode<T: OpParam>(&mut self) -> T {
|
||||
let data = self.program.as_ptr().add(self.pc + 1).cast::<T>().read();
|
||||
self.pc += 1 + core::mem::size_of::<T>();
|
||||
data
|
||||
}
|
||||
|
||||
/// Perform binary operating over two registers
|
||||
#[inline]
|
||||
unsafe fn binary_op<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
|
||||
let ParamBBB(tg, a0, a1) = self.decode();
|
||||
self.write_reg(
|
||||
tg,
|
||||
op(self.read_reg(a0).cast::<T>(), self.read_reg(a1).cast::<T>()),
|
||||
);
|
||||
}
|
||||
|
||||
/// Perform binary operation over register and immediate
|
||||
#[inline]
|
||||
unsafe fn binary_op_imm<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
|
||||
let ParamBBD(tg, reg, imm) = self.decode();
|
||||
self.write_reg(
|
||||
tg,
|
||||
op(self.read_reg(reg).cast::<T>(), Value::from(imm).cast::<T>()),
|
||||
);
|
||||
}
|
||||
|
||||
/// Perform binary operation over register and shift immediate
|
||||
#[inline]
|
||||
unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
|
||||
let ParamBBW(tg, reg, imm) = self.decode();
|
||||
self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm));
|
||||
}
|
||||
|
||||
/// Jump at `#3` if ordering on `#0 <=> #1` is equal to expected
|
||||
#[inline]
|
||||
unsafe fn cond_jmp<T: ValueVariant + Ord>(&mut self, expected: Ordering) {
|
||||
let ParamBBD(a0, a1, ja) = self.decode();
|
||||
if self
|
||||
.read_reg(a0)
|
||||
.cast::<T>()
|
||||
.cmp(&self.read_reg(a1).cast::<T>())
|
||||
== expected
|
||||
{
|
||||
self.pc = ja as usize;
|
||||
}
|
||||
}
|
||||
|
||||
/// Read register
|
||||
#[inline]
|
||||
unsafe fn read_reg(&self, n: u8) -> Value {
|
||||
*self.registers.get_unchecked(n as usize)
|
||||
}
|
||||
|
||||
/// Write a register.
|
||||
/// Writing to register 0 is no-op.
|
||||
#[inline]
|
||||
unsafe fn write_reg(&mut self, n: u8, value: impl Into<Value>) {
|
||||
if n != 0 {
|
||||
*self.registers.get_unchecked_mut(n as usize) = value.into();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Load/Store target/source register range bound checking
|
||||
#[inline]
|
||||
fn ldst_bound_check(reg: u8, size: u16) -> Result<(), VmRunError> {
|
||||
if usize::from(reg) * 8 + usize::from(size) > 2048 {
|
||||
Err(VmRunError::RegOutOfBounds)
|
||||
} else {
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
/// Virtual machine halt error
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[repr(u8)]
|
||||
pub enum VmRunError {
|
||||
/// Tried to execute invalid instruction
|
||||
InvalidOpcode(u8),
|
||||
|
||||
/// Unhandled load access exception
|
||||
LoadAccessEx(u64),
|
||||
|
||||
/// Unhandled store access exception
|
||||
StoreAccessEx(u64),
|
||||
|
||||
/// Register out-of-bounds access
|
||||
RegOutOfBounds,
|
||||
|
||||
/// Reached unreachable code
|
||||
Unreachable,
|
||||
}
|
||||
|
||||
/// Virtual machine halt ok
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
pub enum VmRunOk {
|
||||
/// Program has eached its end
|
||||
End,
|
||||
|
||||
/// Program was interrupted by a timer
|
||||
Timer,
|
||||
|
||||
/// Environment call
|
||||
Ecall,
|
||||
}
|
||||
Loading…
Reference in a new issue