fixing some bugs and making the generic types work, well not quite

This commit is contained in:
Jakub Doka 2024-10-22 10:08:50 +02:00
parent 2aa5ba9abc
commit b0a85f44c9
No known key found for this signature in database
GPG key ID: C6E9A89936B8C143
16 changed files with 304 additions and 231 deletions

View file

@ -427,14 +427,14 @@ modify := fn($num: ^int): void {
MALLOC_SYS_CALL := 69 MALLOC_SYS_CALL := 69
FREE_SYS_CALL := 96 FREE_SYS_CALL := 96
malloc := fn(size: uint, align: uint): ^void return @eca(MALLOC_SYS_CALL, size, align) malloc := fn(size: int, align: int): ^void return @eca(MALLOC_SYS_CALL, size, align)
free := fn(ptr: ^void, size: uint, align: uint): void return @eca(FREE_SYS_CALL, ptr, size, align) free := fn(ptr: ^void, size: int, align: int): void return @eca(FREE_SYS_CALL, ptr, size, align)
Vec := fn($Elem: type): type { Vec := fn($Elem: type): type {
return struct { return struct {
data: ^Elem, data: ^Elem,
len: uint, len: int,
cap: uint, cap: int,
} }
} }
@ -455,7 +455,7 @@ push := fn($Elem: type, vec: ^Vec(Elem), value: Elem): ^Elem {
} }
new_alloc := @as(^Elem, @bitcast(malloc(vec.cap * @sizeof(Elem), @alignof(Elem)))) new_alloc := @as(^Elem, @bitcast(malloc(vec.cap * @sizeof(Elem), @alignof(Elem))))
if new_alloc == 0 return 0 if new_alloc == 0 return @bitcast(0)
src_cursor := vec.data src_cursor := vec.data
dst_cursor := new_alloc dst_cursor := new_alloc
@ -481,7 +481,7 @@ push := fn($Elem: type, vec: ^Vec(Elem), value: Elem): ^Elem {
main := fn(): int { main := fn(): int {
vec := new(int) vec := new(int)
push(int, &vec, 69) _f := push(int, &vec, 69)
res := *vec.data res := *vec.data
deinit(int, &vec) deinit(int, &vec)
return res return res

View file

@ -1013,7 +1013,8 @@ trait TypeParser {
.map_or(ArrayLen::MAX, |expr| self.eval_const(file, expr, ty::Id::U32) as _); .map_or(ArrayLen::MAX, |expr| self.eval_const(file, expr, ty::Id::U32) as _);
self.tys().make_array(ty, len) self.tys().make_array(ty, len)
} }
Expr::Struct { pos, fields, packed, .. } => { Expr::Struct { pos, fields, packed, captured, .. } => {
assert!(captured.is_empty());
let sym = SymKey::Struct(file, pos); let sym = SymKey::Struct(file, pos);
let tys = self.tys(); let tys = self.tys();
if let Some(&ty) = tys.syms.get(sym, &tys.ins) { if let Some(&ty) = tys.syms.get(sym, &tys.ins) {

View file

@ -25,7 +25,7 @@ use {
}, },
hashbrown::hash_map, hashbrown::hash_map,
regalloc2::VReg, regalloc2::VReg,
std::panic, std::{borrow::ToOwned, panic},
}; };
const VOID: Nid = 0; const VOID: Nid = 0;
@ -1186,6 +1186,9 @@ impl ItemCtx {
} }
Kind::Return => { Kind::Return => {
match retl { match retl {
PLoc::Reg(r, size) if sig.ret.loc(tys) == Loc::Stack => {
self.emit(instrs::ld(r, atr(allocs[0]), 0, size))
}
PLoc::None | PLoc::Reg(..) => {} PLoc::None | PLoc::Reg(..) => {}
PLoc::WideReg(r, size) => { PLoc::WideReg(r, size) => {
self.emit(instrs::ld(r, atr(allocs[0]), 0, size)) self.emit(instrs::ld(r, atr(allocs[0]), 0, size))
@ -1307,7 +1310,7 @@ impl ItemCtx {
offset = value as Offset; offset = value as Offset;
} }
let size = tys.size_of(node.ty); let size = tys.size_of(node.ty);
if size <= 8 { if node.ty.loc(tys) != Loc::Stack {
let (base, offset) = match fuc.nodes[region].kind { let (base, offset) = match fuc.nodes[region].kind {
Kind::Stck => (reg::STACK_PTR, fuc.nodes[region].offset + offset), Kind::Stck => (reg::STACK_PTR, fuc.nodes[region].offset + offset),
_ => (atr(allocs[1]), offset), _ => (atr(allocs[1]), offset),
@ -1323,22 +1326,25 @@ impl ItemCtx {
if fuc.nodes[region].kind == (Kind::BinOp { op: TokenKind::Add }) if fuc.nodes[region].kind == (Kind::BinOp { op: TokenKind::Add })
&& let Kind::CInt { value } = && let Kind::CInt { value } =
fuc.nodes[fuc.nodes[region].inputs[2]].kind fuc.nodes[fuc.nodes[region].inputs[2]].kind
&& size <= 8 && node.ty.loc(tys) == Loc::Reg
{ {
region = fuc.nodes[region].inputs[1]; region = fuc.nodes[region].inputs[1];
offset = value as Offset; offset = value as Offset;
} }
let nd = &fuc.nodes[region]; let nd = &fuc.nodes[region];
let (base, offset, src) = match nd.kind { let (base, offset, src) = match nd.kind {
Kind::Stck if size <= 8 => { Kind::Stck if node.ty.loc(tys) == Loc::Reg => {
(reg::STACK_PTR, nd.offset + offset, allocs[0]) (reg::STACK_PTR, nd.offset + offset, allocs[0])
} }
_ => (atr(allocs[0]), offset, allocs[1]), _ => (atr(allocs[0]), offset, allocs[1]),
}; };
if size > 8 {
self.emit(instrs::bmc(atr(src), base, size)); match node.ty.loc(tys) {
} else { Loc::Reg => self.emit(instrs::st(atr(src), base, offset as _, size)),
self.emit(instrs::st(atr(src), base, offset as _, size)); Loc::Stack => {
debug_assert_eq!(offset, 0);
self.emit(instrs::bmc(atr(src), base, size))
}
} }
} }
Kind::Start Kind::Start
@ -1365,6 +1371,8 @@ impl ItemCtx {
self.nodes.basic_blocks(); self.nodes.basic_blocks();
self.nodes.graphviz(tys, files); self.nodes.graphviz(tys, files);
debug_assert!(self.code.is_empty());
'_open_function: { '_open_function: {
self.emit(instrs::addi64(reg::STACK_PTR, reg::STACK_PTR, 0)); self.emit(instrs::addi64(reg::STACK_PTR, reg::STACK_PTR, 0));
self.emit(instrs::st(reg::RET_ADDR, reg::STACK_PTR, 0, 0)); self.emit(instrs::st(reg::RET_ADDR, reg::STACK_PTR, 0, 0));
@ -1421,9 +1429,9 @@ impl ItemCtx {
} }
(0, stack) => { (0, stack) => {
write_reloc(&mut self.code, 3, -stack, 8); write_reloc(&mut self.code, 3, -stack, 8);
stripped_prelude_size = instrs::addi64(0, 0, 0).0; stripped_prelude_size = instrs::st(0, 0, 0, 0).0;
let end = stripped_prelude_size + instrs::st(0, 0, 0, 0).0; let end = instrs::addi64(0, 0, 0).0 + instrs::st(0, 0, 0, 0).0;
self.code.drain(stripped_prelude_size..end); self.code.drain(instrs::addi64(0, 0, 0).0..end);
self.emit(instrs::addi64(reg::STACK_PTR, reg::STACK_PTR, stack as _)); self.emit(instrs::addi64(reg::STACK_PTR, reg::STACK_PTR, stack as _));
break '_close_function; break '_close_function;
} }
@ -1585,12 +1593,15 @@ impl TypeParser for Codegen<'_> {
} }
fn eval_const(&mut self, file: FileId, expr: &Expr, ret: ty::Id) -> u64 { fn eval_const(&mut self, file: FileId, expr: &Expr, ret: ty::Id) -> u64 {
let vars = self.ci.scope.vars.clone();
self.pool.push_ci(file, Some(ret), self.tasks.len(), &mut self.ci); self.pool.push_ci(file, Some(ret), self.tasks.len(), &mut self.ci);
self.ci.scope.vars = vars;
let prev_err_len = self.errors.borrow().len(); let prev_err_len = self.errors.borrow().len();
self.expr(&Expr::Return { pos: expr.pos(), val: Some(expr) }); self.expr(&Expr::Return { pos: expr.pos(), val: Some(expr) });
self.ci.scope.vars = vec![];
self.ci.finalize(); self.ci.finalize();
if self.errors.borrow().len() == prev_err_len { if self.errors.borrow().len() == prev_err_len {
@ -2002,8 +2013,13 @@ impl<'a> Codegen<'a> {
Some(self.ci.nodes.new_node_lit(val.ty, Kind::UnOp { op }, [VOID, val.id])) Some(self.ci.nodes.new_node_lit(val.ty, Kind::UnOp { op }, [VOID, val.id]))
} }
Expr::BinOp { left, op: TokenKind::Decl, right } => { Expr::BinOp { left, op: TokenKind::Decl, right } => {
let mut right = self.raw_expr(right)?; let mut right = self.expr(right)?;
self.strip_var(&mut right); if right.ty.loc(&self.tys) == Loc::Stack {
let stck = self.ci.nodes.new_node_nop(right.ty, Kind::Stck, [VOID, MEM]);
self.store_mem(stck, right.id);
right.id = stck;
right.ptr = true;
}
self.assign_pattern(left, right); self.assign_pattern(left, right);
Some(Value::VOID) Some(Value::VOID)
} }
@ -2483,6 +2499,10 @@ impl<'a> Codegen<'a> {
} }
} }
} }
Expr::Struct { .. } => {
let value = self.ty(expr).repr() as i64;
Some(self.ci.nodes.new_node_lit(ty::Id::TYPE, Kind::CInt { value }, [VOID]))
}
Expr::Ctor { pos, ty, fields, .. } => { Expr::Ctor { pos, ty, fields, .. } => {
let Some(sty) = ty.map(|ty| self.ty(ty)).or(ctx.ty) else { let Some(sty) = ty.map(|ty| self.ty(ty)).or(ctx.ty) else {
self.report( self.report(
@ -2996,7 +3016,7 @@ impl<'a> Codegen<'a> {
} }
let value = self.ci.nodes.new_node_nop(ty, Kind::Arg, [VOID]); let value = self.ci.nodes.new_node_nop(ty, Kind::Arg, [VOID]);
self.ci.nodes.lock(value); self.ci.nodes.lock(value);
let ptr = self.tys.size_of(ty) > 8; let ptr = ty.loc(&self.tys) == Loc::Stack;
self.ci.scope.vars.push(Variable { id: arg.id, value, ty, ptr }); self.ci.scope.vars.push(Variable { id: arg.id, value, ty, ptr });
} }
@ -3076,12 +3096,22 @@ impl<'a> Codegen<'a> {
expected: ty::Id, expected: ty::Id,
hint: impl fmt::Display, hint: impl fmt::Display,
) -> bool { ) -> bool {
if let Some(upcasted) = src.ty.try_upcast(expected, ty::TyCheck::BinOp) if let Some(upcasted) = src.ty.try_upcast(expected, ty::TyCheck::Assign)
&& upcasted == expected && upcasted == expected
{ {
if src.ty != upcasted { if src.ty != upcasted {
debug_assert!(src.ty.is_integer()); debug_assert!(
debug_assert!(upcasted.is_integer()); src.ty.is_integer() || src.ty == ty::Id::NEVER,
"{} {}",
self.ty_display(src.ty),
self.ty_display(upcasted)
);
debug_assert!(
upcasted.is_integer() || src.ty == ty::Id::NEVER,
"{} {}",
self.ty_display(src.ty),
self.ty_display(upcasted)
);
src.ty = upcasted; src.ty = upcasted;
src.id = self.ci.nodes.new_node(upcasted, Kind::Extend, [VOID, src.id]); src.id = self.ci.nodes.new_node(upcasted, Kind::Extend, [VOID, src.id]);
} }
@ -3293,6 +3323,9 @@ impl<'a> Function<'a> {
Kind::Return => { Kind::Return => {
let ops = match self.tys.parama(self.sig.ret).0 { let ops = match self.tys.parama(self.sig.ret).0 {
PLoc::None => vec![], PLoc::None => vec![],
PLoc::Reg(..) if self.sig.ret.loc(self.tys) == Loc::Stack => {
vec![self.urg(self.nodes[node.inputs[1]].inputs[1])]
}
PLoc::Reg(r, ..) => { PLoc::Reg(r, ..) => {
vec![regalloc2::Operand::reg_fixed_use( vec![regalloc2::Operand::reg_fixed_use(
self.rg(node.inputs[1]), self.rg(node.inputs[1]),
@ -3330,10 +3363,17 @@ impl<'a> Function<'a> {
self.nodes[nid].ralloc_backref = self.add_block(nid); self.nodes[nid].ralloc_backref = self.add_block(nid);
let (_, mut parama) = self.tys.parama(self.sig.ret); let (_, mut parama) = self.tys.parama(self.sig.ret);
for (ti, arg) in
self.sig.args.range().zip(self.nodes[VOID].clone().outputs.into_iter().skip(2)) let argc = self.sig.args.range().len()
{ - self.tys.ins.args[self.sig.args.range()]
let ty = self.tys.ins.args[ti]; .iter()
.filter(|&&ty| ty == ty::Id::TYPE)
.count()
* 2;
#[allow(clippy::unnecessary_to_owned)]
for arg in self.nodes[VOID].outputs[2..][..argc].to_owned() {
let ty = self.nodes[arg].ty;
match parama.next(ty, self.tys) { match parama.next(ty, self.tys) {
PLoc::None => {} PLoc::None => {}
PLoc::Reg(r, _) | PLoc::WideReg(r, _) | PLoc::Ref(r, _) => { PLoc::Reg(r, _) | PLoc::WideReg(r, _) | PLoc::Ref(r, _) => {
@ -3359,8 +3399,9 @@ impl<'a> Function<'a> {
Kind::BinOp { op: TokenKind::Add } Kind::BinOp { op: TokenKind::Add }
if self.nodes.is_const(node.inputs[2]) if self.nodes.is_const(node.inputs[2])
&& node.outputs.iter().all(|&n| { && node.outputs.iter().all(|&n| {
matches!(self.nodes[n].kind, Kind::Stre | Kind::Load) (matches!(self.nodes[n].kind, Kind::Stre if self.nodes[n].inputs[2] == nid)
&& self.tys.size_of(self.nodes[n].ty) <= 8 || matches!(self.nodes[n].kind, Kind::Load if self.nodes[n].inputs[1] == nid))
&& self.nodes[n].ty.loc(self.tys) == Loc::Reg
}) => }) =>
{ {
self.nodes.lock(nid) self.nodes.lock(nid)
@ -3480,13 +3521,14 @@ impl<'a> Function<'a> {
self.add_instr(nid, ops); self.add_instr(nid, ops);
} }
Kind::Phi | Kind::Arg | Kind::Mem => {} Kind::Phi | Kind::Arg | Kind::Mem => {}
Kind::Load { .. } if matches!(self.tys.size_of(node.ty), 0 | 9..) => { Kind::Load { .. } if node.ty.loc(self.tys) == Loc::Stack => {
self.nodes.lock(nid) self.nodes.lock(nid)
} }
Kind::Load { .. } => { Kind::Load { .. } => {
let mut region = node.inputs[1]; let mut region = node.inputs[1];
if self.nodes[region].kind == (Kind::BinOp { op: TokenKind::Add }) if self.nodes[region].kind == (Kind::BinOp { op: TokenKind::Add })
&& self.nodes.is_const(self.nodes[region].inputs[2]) && self.nodes.is_const(self.nodes[region].inputs[2])
&& node.ty.loc(self.tys) == Loc::Reg
{ {
region = self.nodes[region].inputs[1] region = self.nodes[region].inputs[1]
} }
@ -3501,11 +3543,12 @@ impl<'a> Function<'a> {
let mut region = node.inputs[2]; let mut region = node.inputs[2];
if self.nodes[region].kind == (Kind::BinOp { op: TokenKind::Add }) if self.nodes[region].kind == (Kind::BinOp { op: TokenKind::Add })
&& self.nodes.is_const(self.nodes[region].inputs[2]) && self.nodes.is_const(self.nodes[region].inputs[2])
&& node.ty.loc(self.tys) == Loc::Reg
{ {
region = self.nodes[region].inputs[1] region = self.nodes[region].inputs[1]
} }
let ops = match self.nodes[region].kind { let ops = match self.nodes[region].kind {
_ if self.tys.size_of(node.ty) > 8 => { _ if node.ty.loc(self.tys) == Loc::Stack => {
vec![self.urg(region), self.urg(self.nodes[node.inputs[1]].inputs[1])] vec![self.urg(region), self.urg(self.nodes[node.inputs[1]].inputs[1])]
} }
Kind::Stck => vec![self.urg(node.inputs[1])], Kind::Stck => vec![self.urg(node.inputs[1])],
@ -3590,9 +3633,11 @@ impl regalloc2::Function for Function<'_> {
} }
fn inst_clobbers(&self, insn: regalloc2::Inst) -> regalloc2::PRegSet { fn inst_clobbers(&self, insn: regalloc2::Inst) -> regalloc2::PRegSet {
if matches!(self.nodes[self.instrs[insn.index()].nid].kind, Kind::Call { .. }) { let node = &self.nodes[self.instrs[insn.index()].nid];
if matches!(node.kind, Kind::Call { .. }) {
let mut set = regalloc2::PRegSet::default(); let mut set = regalloc2::PRegSet::default();
for i in 2..13 { let returns = !matches!(self.tys.parama(node.ty).0, PLoc::None);
for i in 1 + returns as usize..13 {
set.add(regalloc2::PReg::new(i, regalloc2::RegClass::Int)); set.add(regalloc2::PReg::new(i, regalloc2::RegClass::Int));
} }
set set

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@ -238,9 +238,6 @@ impl Deref for Vc {
type Target = [Nid]; type Target = [Nid];
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
if self.as_slice().iter().position(|&i| i == 1) == Some(2) {
log::info!("foo {}", std::backtrace::Backtrace::capture());
}
self.as_slice() self.as_slice()
} }
} }

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@ -1,6 +1,6 @@
main: main:
ADDI64 r254, r254, -108d ADDI64 r254, r254, -152d
ST r31, r254, 28a, 80h ST r31, r254, 56a, 96h
LI64 r32, 4d LI64 r32, 4d
LI64 r33, 1d LI64 r33, 1d
LI64 r34, 2d LI64 r34, 2d
@ -9,19 +9,23 @@ main:
LI64 r37, 0d LI64 r37, 0d
ADDI64 r2, r254, 0d ADDI64 r2, r254, 0d
ADDI64 r38, r254, 24d ADDI64 r38, r254, 24d
ST r37, r254, 24a, 1h ADDI64 r39, r254, 48d
ST r37, r254, 25a, 1h ADDI64 r40, r254, 52d
ST r35, r254, 26a, 1h ST r37, r254, 52a, 1h
ST r33, r254, 27a, 1h ST r37, r254, 53a, 1h
ST r36, r254, 0a, 8h ST r35, r254, 54a, 1h
ST r34, r254, 8a, 8h ST r33, r254, 55a, 1h
ST r32, r254, 16a, 8h BMC r40, r39, 4h
ST r36, r254, 24a, 8h
ST r34, r254, 32a, 8h
ST r32, r254, 40a, 8h
BMC r38, r2, 24h
JAL r31, r0, :pass JAL r31, r0, :pass
LD r39, r254, 27a, 1h LD r41, r254, 51a, 1h
ANDI r40, r39, 255d ANDI r42, r41, 255d
ADD64 r1, r1, r40 ADD64 r1, r1, r42
LD r31, r254, 28a, 80h LD r31, r254, 56a, 96h
ADDI64 r254, r254, 108d ADDI64 r254, r254, 152d
JALA r0, r31, 0a JALA r0, r31, 0a
pass: pass:
LD r3, r2, 8a, 8h LD r3, r2, 8a, 8h
@ -32,6 +36,6 @@ pass:
ADD64 r11, r3, r9 ADD64 r11, r3, r9
ADD64 r1, r8, r11 ADD64 r1, r8, r11
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 348 code size: 380
ret: 8 ret: 8
status: Ok(()) status: Ok(())

View file

@ -1,52 +1,53 @@
main: main:
ADDI64 r254, r254, -24d ADDI64 r254, r254, -36d
LI64 r9, 2d LI64 r8, 2d
LI64 r8, 0d LI64 r7, 0d
LI64 r6, 0d LI64 r6, 0d
LI64 r7, 255d LI64 r9, 255d
ADDI64 r10, r254, 0d ADDI64 r1, r254, 0d
ADDI64 r10, r254, 8d ADDI64 r10, r254, 12d
ST r7, r254, 8a, 1h ADDI64 r11, r254, 20d
ST r6, r254, 9a, 1h ST r9, r254, 20a, 1h
ST r6, r254, 10a, 1h ST r6, r254, 21a, 1h
ST r7, r254, 11a, 1h ST r6, r254, 22a, 1h
LD r3, r254, 8a, 4h ST r9, r254, 23a, 1h
ADDI64 r12, r254, 12d ADDI64 r12, r254, 24d
ST r3, r254, 12a, 4h ADDI64 r9, r12, 4d
ST r8, r254, 0a, 4h BMC r11, r12, 4h
ST r9, r254, 4a, 4h ST r7, r254, 12a, 4h
LD r12, r254, 0a, 8h ST r8, r254, 16a, 4h
ST r12, r254, 16a, 8h BMC r10, r9, 8h
LD r3, r254, 20a, 4h BMC r12, r1, 12h
ANDI r3, r3, 4294967295d LD r4, r254, 8a, 4h
ANDI r9, r9, 4294967295d ANDI r4, r4, 4294967295d
JEQ r3, r9, :0 ANDI r8, r8, 4294967295d
JEQ r4, r8, :0
LI64 r1, 0d LI64 r1, 0d
JMP :1 JMP :1
0: LD r9, r254, 16a, 4h 0: LD r10, r254, 4a, 4h
ANDI r9, r9, 4294967295d ANDI r10, r10, 4294967295d
ANDI r8, r8, 4294967295d ANDI r7, r7, 4294967295d
JEQ r9, r8, :2 JEQ r10, r7, :2
LI64 r1, 64d LI64 r1, 64d
JMP :1 JMP :1
2: LD r3, r254, 15a, 1h 2: LD r4, r254, 3a, 1h
ANDI r6, r4, 255d
LD r3, r254, 2a, 1h
ANDI r5, r3, 255d ANDI r5, r3, 255d
LD r2, r254, 14a, 1h LD r2, r254, 1a, 1h
ANDI r4, r2, 255d ANDI r4, r2, 255d
LD r1, r254, 13a, 1h LD r12, r254, 0a, 1h
ANDI r3, r1, 255d ANDI r3, r12, 255d
LD r11, r254, 12a, 1h LD r1, r254, 8a, 4h
ANDI r2, r11, 255d LD r2, r254, 4a, 4h
LD r12, r254, 20a, 4h ADD32 r7, r1, r2
LD r1, r254, 16a, 4h ADD32 r8, r7, r3
ADD32 r6, r12, r1 ADD32 r12, r8, r4
ADD32 r7, r6, r2 ADD32 r4, r12, r5
ADD32 r11, r7, r3 ADD32 r8, r4, r6
ADD32 r3, r11, r4 ANDI r1, r8, 4294967295d
ADD32 r7, r3, r5 1: ADDI64 r254, r254, 36d
ANDI r1, r7, 4294967295d
1: ADDI64 r254, r254, 24d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 507 code size: 492
ret: 512 ret: 512
status: Ok(()) status: Ok(())

View file

@ -1,19 +1,23 @@
main: main:
ADDI64 r254, r254, -16d ADDI64 r254, r254, -31d
LI64 r6, 6d
LI64 r5, 5d LI64 r5, 5d
LI64 r7, 20d LI64 r7, 20d
LI64 r2, 1d LI64 r2, 1d
LI64 r4, 10d LI64 r9, 10d
LI64 r6, 6d ADDI64 r8, r254, 15d
ADDI64 r8, r254, 0d ST r9, r254, 15a, 8h
ST r4, r254, 0a, 8h ST r7, r254, 23a, 8h
ST r7, r254, 8a, 8h
LD r3, r8, 0a, 16h LD r3, r8, 0a, 16h
ECA ECA
LRA r5, r0, :arbitrary text
LI64 r1, 0d LI64 r1, 0d
ADDI64 r254, r254, 16d ADDI64 r8, r254, 0d
BMC r5, r8, 15h
ADDI64 r254, r254, 31d
JALA r0, r31, 0a JALA r0, r31, 0a
ev: Ecall ev: Ecall
code size: 152 code size: 190
ret: 0 ret: 0
status: Ok(()) status: Ok(())

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@ -1,20 +1,22 @@
main: main:
ADDI64 r254, r254, -128d ADDI64 r254, r254, -256d
LI64 r6, 69d LI64 r7, 69d
LI64 r5, 128d LI64 r6, 128d
LI64 r7, 0d LI64 r8, 0d
ADDI64 r4, r254, 0d ADDI64 r5, r254, 0d
2: JLTS r7, r5, :0 ADDI64 r9, r254, 128d
LD r2, r254, 42a, 1h BMC r9, r5, 128h
ANDI r1, r2, 255d 2: JLTS r8, r6, :0
LD r5, r254, 42a, 1h
ANDI r1, r5, 255d
JMP :1 JMP :1
0: ADDI64 r8, r7, 1d 0: ADDI64 r9, r8, 1d
ADD64 r3, r7, r4 ADD64 r8, r8, r5
ST r6, r3, 0a, 1h ST r7, r8, 0a, 1h
CP r7, r8 CP r8, r9
JMP :2 JMP :2
1: ADDI64 r254, r254, 128d 1: ADDI64 r254, r254, 256d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 152 code size: 168
ret: 69 ret: 69
status: Ok(()) status: Ok(())

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@ -30,41 +30,44 @@ line:
JMP :0 JMP :0
0: JALA r0, r31, 0a 0: JALA r0, r31, 0a
main: main:
ADDI64 r254, r254, -160d ADDI64 r254, r254, -184d
ST r31, r254, 96a, 64h ST r31, r254, 96a, 88h
LI64 r32, 10d LI64 r32, 10d
LI64 r1, 0d LI64 r33, 0d
ADDI64 r33, r254, 48d ADDI64 r34, r254, 48d
ADDI64 r34, r254, 64d ADDI64 r35, r254, 64d
ADDI64 r35, r254, 80d ADDI64 r36, r254, 80d
ST r1, r254, 80a, 8h LD r37, r254, 96a, 0h
ST r1, r254, 88a, 8h ST r33, r254, 80a, 8h
ST r1, r254, 64a, 8h ST r33, r254, 88a, 8h
ST r1, r254, 72a, 8h ST r33, r254, 64a, 8h
ST r1, r254, 48a, 8h ST r33, r254, 72a, 8h
ST r1, r254, 56a, 8h ST r33, r254, 48a, 8h
ST r33, r254, 56a, 8h
CP r8, r32 CP r8, r32
LD r2, r35, 0a, 16h LD r2, r36, 0a, 16h
LD r4, r34, 0a, 16h LD r4, r35, 0a, 16h
LD r6, r33, 0a, 16h LD r6, r34, 0a, 16h
JAL r31, r0, :line JAL r31, r0, :line
ADDI64 r36, r254, 0d ADDI64 r38, r254, 0d
ADDI64 r37, r254, 16d ADDI64 r39, r254, 16d
ADDI64 r38, r254, 32d ADDI64 r40, r254, 32d
ST r1, r254, 32a, 8h LD r41, r254, 48a, 0h
ST r1, r254, 40a, 8h ST r33, r254, 32a, 8h
ST r1, r254, 16a, 8h ST r33, r254, 40a, 8h
ST r1, r254, 24a, 8h ST r33, r254, 16a, 8h
ST r1, r254, 0a, 8h ST r33, r254, 24a, 8h
ST r1, r254, 8a, 8h ST r33, r254, 0a, 8h
ST r33, r254, 8a, 8h
CP r8, r32 CP r8, r32
LD r2, r38, 0a, 16h LD r2, r40, 0a, 16h
LD r4, r37, 0a, 16h LD r4, r39, 0a, 16h
LD r6, r36, 0a, 16h LD r6, r38, 0a, 16h
JAL r31, r0, :rect_line JAL r31, r0, :rect_line
JAL r31, r0, :example JAL r31, r0, :example
LD r31, r254, 96a, 64h CP r1, r33
ADDI64 r254, r254, 160d LD r31, r254, 96a, 88h
ADDI64 r254, r254, 184d
JALA r0, r31, 0a JALA r0, r31, 0a
rect_line: rect_line:
ST r2, r254, 0a, 16h ST r2, r254, 0a, 16h
@ -86,6 +89,6 @@ rect_line:
2: ADDI64 r9, r9, 1d 2: ADDI64 r9, r9, 1d
JMP :4 JMP :4
1: JALA r0, r31, 0a 1: JALA r0, r31, 0a
code size: 857 code size: 886
ret: 4 ret: 0
status: Ok(()) status: Ok(())

View file

@ -31,23 +31,25 @@ fib_iter:
JMP :2 JMP :2
1: JALA r0, r31, 0a 1: JALA r0, r31, 0a
main: main:
ADDI64 r254, r254, -50d ADDI64 r254, r254, -60d
ST r31, r254, 2a, 48h ST r31, r254, 4a, 56h
LI64 r32, 10d LI64 r32, 10d
ADDI64 r33, r254, 0d ADDI64 r33, r254, 0d
ST r32, r254, 0a, 1h ADDI64 r34, r254, 2d
ST r32, r254, 1a, 1h ST r32, r254, 2a, 1h
LD r34, r254, 0a, 1h ST r32, r254, 3a, 1h
ANDI r2, r34, 255d BMC r34, r33, 2h
LD r35, r254, 0a, 1h
ANDI r2, r35, 255d
JAL r31, r0, :fib JAL r31, r0, :fib
CP r35, r1 CP r36, r1
LD r36, r254, 1a, 1h LD r37, r254, 1a, 1h
ANDI r2, r36, 255d ANDI r2, r37, 255d
JAL r31, r0, :fib_iter JAL r31, r0, :fib_iter
SUB64 r1, r35, r1 SUB64 r1, r36, r1
LD r31, r254, 2a, 48h LD r31, r254, 4a, 56h
ADDI64 r254, r254, 50d ADDI64 r254, r254, 60d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 376 code size: 392
ret: 0 ret: 0
status: Ok(()) status: Ok(())

View file

@ -1,26 +1,29 @@
main: main:
ADDI64 r254, r254, -120d ADDI64 r254, r254, -176d
ST r31, r254, 64a, 56h ST r31, r254, 112a, 64h
LI64 r32, 3d LI64 r32, 3d
LI64 r33, 1d LI64 r33, 1d
LI64 r34, 4d LI64 r34, 4d
ADDI64 r35, r254, 0d ADDI64 r35, r254, 24d
ADDI64 r36, r254, 24d ADDI64 r36, r254, 48d
ST r34, r254, 24a, 8h ADDI64 r37, r254, 72d
ST r33, r254, 32a, 8h ST r34, r254, 72a, 8h
ADDI64 r2, r254, 40d ST r33, r254, 80a, 8h
BMC r36, r2, 16h ADDI64 r2, r254, 88d
ST r32, r254, 56a, 8h BMC r37, r2, 16h
ST r32, r254, 104a, 8h
BMC r2, r36, 24h
CP r1, r35 CP r1, r35
JAL r31, r0, :odher_pass JAL r31, r0, :odher_pass
LD r37, r254, 16a, 8h ADDI64 r2, r254, 0d
JNE r37, r32, :0 BMC r35, r2, 24h
CP r2, r35 LD r38, r254, 16a, 8h
JNE r38, r32, :0
JAL r31, r0, :pass JAL r31, r0, :pass
JMP :1 JMP :1
0: LI64 r1, 0d 0: LI64 r1, 0d
1: LD r31, r254, 64a, 56h 1: LD r31, r254, 112a, 64h
ADDI64 r254, r254, 120d ADDI64 r254, r254, 176d
JALA r0, r31, 0a JALA r0, r31, 0a
odher_pass: odher_pass:
BMC r2, r1, 24h BMC r2, r1, 24h
@ -30,6 +33,6 @@ pass:
LD r5, r2, 0a, 8h LD r5, r2, 0a, 8h
SUB64 r1, r5, r4 SUB64 r1, r5, r4
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 284 code size: 313
ret: 3 ret: 3
status: Ok(()) status: Ok(())

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@ -1,8 +1,12 @@
main: main:
ADDI64 r254, r254, -4d
LRA r1, r0, :MAGENTA LRA r1, r0, :MAGENTA
LD r3, r1, 2a, 1h ADDI64 r3, r254, 0d
ANDI r1, r3, 255d BMC r1, r3, 4h
LD r6, r254, 2a, 1h
ANDI r1, r6, 255d
ADDI64 r254, r254, 4d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 54 code size: 92
ret: 205 ret: 205
status: Ok(()) status: Ok(())

View file

@ -1,30 +1,32 @@
main: main:
ADDI64 r254, r254, -10240d ADDI64 r254, r254, -20480d
LI64 r7, 64d LI64 r8, 64d
LI64 r5, 1024d LI64 r6, 1024d
LI64 r9, 1d LI64 r10, 1d
LI64 r8, 0d LI64 r9, 0d
ADDI64 r6, r254, 0d ADDI64 r7, r254, 0d
4: JLTS r8, r5, :0 ADDI64 r11, r254, 10240d
LI64 r7, 10d BMC r11, r7, 10240h
CP r8, r9 4: JLTS r9, r6, :0
3: JLTS r8, r7, :1 LI64 r8, 10d
LD r9, r254, 2048a, 1h CP r11, r10
ANDI r1, r9, 255d 3: JLTS r11, r8, :1
LD r12, r254, 2048a, 1h
ANDI r1, r12, 255d
JMP :2 JMP :2
1: ADD64 r3, r8, r9 1: ADD64 r9, r11, r10
MUL64 r2, r8, r5 MUL64 r5, r11, r6
ADD64 r4, r2, r6 ADD64 r11, r5, r7
BMC r6, r4, 1024h BMC r7, r11, 1024h
CP r8, r3 CP r11, r9
JMP :3 JMP :3
0: ADD64 r2, r8, r9 0: ADD64 r5, r9, r10
ADD64 r12, r8, r6 ADD64 r3, r9, r7
ST r7, r12, 0a, 1h ST r8, r3, 0a, 1h
CP r8, r2 CP r9, r5
JMP :4 JMP :4
2: ADDI64 r254, r254, 10240d 2: ADDI64 r254, r254, 20480d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 198 code size: 214
ret: 64 ret: 64
status: Ok(()) status: Ok(())

View file

@ -1,43 +1,48 @@
main: main:
ADDI64 r254, r254, -56d ADDI64 r254, r254, -80d
ST r31, r254, 16a, 40h ST r31, r254, 32a, 48h
LI64 r4, 0d LI64 r4, 0d
ADDI64 r32, r254, 0d ADDI64 r32, r254, 16d
CP r3, r4 CP r3, r4
JAL r31, r0, :maina JAL r31, r0, :maina
ST r1, r254, 0a, 16h ST r1, r254, 16a, 16h
LD r33, r254, 12a, 1h ADDI64 r33, r254, 0d
LD r34, r254, 3a, 1h BMC r32, r33, 16h
SUB8 r35, r34, r33 LD r34, r254, 12a, 1h
ANDI r1, r35, 255d LD r35, r254, 3a, 1h
LD r31, r254, 16a, 40h SUB8 r36, r35, r34
ADDI64 r254, r254, 56d ANDI r1, r36, 255d
LD r31, r254, 32a, 48h
ADDI64 r254, r254, 80d
JALA r0, r31, 0a JALA r0, r31, 0a
maina: maina:
ADDI64 r254, r254, -100d ADDI64 r254, r254, -120d
ST r31, r254, 28a, 72h ST r31, r254, 40a, 80h
ADDI64 r32, r254, 24d ADDI64 r32, r254, 36d
JAL r31, r0, :small_struct JAL r31, r0, :small_struct
LI64 r33, 1d LI64 r33, 1d
LI64 r34, 3d LI64 r34, 3d
LI64 r35, 0d LI64 r35, 0d
ADDI64 r36, r254, 0d ADDI64 r36, r254, 0d
ADDI64 r37, r254, 16d ADDI64 r37, r36, 8d
ST r35, r254, 16a, 1h ADDI64 r38, r254, 16d
ST r35, r254, 17a, 1h ADDI64 r39, r254, 24d
ST r35, r254, 18a, 1h ADDI64 r40, r254, 32d
ST r34, r254, 19a, 1h BMC r32, r40, 4h
ST r33, r254, 20a, 1h ST r35, r254, 24a, 1h
ST r35, r254, 21a, 1h ST r35, r254, 25a, 1h
ST r35, r254, 22a, 1h ST r35, r254, 26a, 1h
ST r35, r254, 23a, 1h ST r34, r254, 27a, 1h
LD r38, r254, 16a, 8h ST r33, r254, 28a, 1h
ST r38, r254, 0a, 8h ST r35, r254, 29a, 1h
LD r39, r254, 16a, 8h ST r35, r254, 30a, 1h
ST r39, r254, 8a, 8h ST r35, r254, 31a, 1h
BMC r39, r38, 8h
BMC r39, r36, 8h
BMC r38, r37, 8h
LD r1, r36, 0a, 16h LD r1, r36, 0a, 16h
LD r31, r254, 28a, 72h LD r31, r254, 40a, 80h
ADDI64 r254, r254, 100d ADDI64 r254, r254, 120d
JALA r0, r31, 0a JALA r0, r31, 0a
small_struct: small_struct:
ADDI64 r254, r254, -4d ADDI64 r254, r254, -4d
@ -45,9 +50,9 @@ small_struct:
ADDI64 r3, r254, 0d ADDI64 r3, r254, 0d
ST r2, r254, 0a, 2h ST r2, r254, 0a, 2h
ST r2, r254, 2a, 2h ST r2, r254, 2a, 2h
LD r1, r254, 0a, 4h LD r1, r3, 0a, 4h
ADDI64 r254, r254, 4d ADDI64 r254, r254, 4d
JALA r0, r31, 0a JALA r0, r31, 0a
code size: 543 code size: 560
ret: 2 ret: 2
status: Ok(()) status: Ok(())

View file

@ -1,7 +1,7 @@
imports_granularity = "One" imports_granularity = "One"
group_imports = "One" group_imports = "One"
reorder_impl_items = true reorder_impl_items = true
unstable_features = false unstable_features = true
overflow_delimited_expr = true overflow_delimited_expr = true
use_small_heuristics = "Max" use_small_heuristics = "Max"
use_field_init_shorthand = true use_field_init_shorthand = true