making the instruction scheduling smarter
the instructions that are only depended by phis are pushed to the end of the block, which usually saves copy instructions Signed-off-by: Jakub Doka <jakub.doka2@gmail.com>
This commit is contained in:
parent
a8aba7e7c2
commit
cfd3eac0a8
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@ -295,9 +295,7 @@ impl Nodes {
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continue;
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}
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let mut cursor = buf.len();
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for &o in outputs.iter().filter(|&&n| n == o) {
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buf.push(o);
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}
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while let Some(&n) = buf.get(cursor) {
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for &i in &self[n].inputs[1..] {
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if fromc == self[i].inputs.first()
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@ -308,15 +306,17 @@ impl Nodes {
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})
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&& seen.set(i)
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{
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for &o in outputs.iter().filter(|&&n| n == i) {
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buf.push(o);
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}
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buf.push(i);
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}
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}
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cursor += 1;
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}
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}
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buf[1..].sort_by_key(|&n| {
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self[n].has_no_value() || !self[n].outputs.iter().all(|&o| self[o].kind == Kind::Phi)
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});
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debug_assert_eq!(
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outputs.iter().filter(|&&n| !seen.get(n)).copied().collect::<Vec<_>>(),
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vec![],
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@ -48,10 +48,9 @@ main:
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JMP :1
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6: CP r1, r0
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JMP :1
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5: ADDI64 r34, r32, 16d
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ST r0, r32, 0a, 8h
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5: ST r0, r32, 0a, 8h
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ST r0, r32, 8a, 8h
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CP r32, r34
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ADDI64 r32, r32, 16d
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JMP :7
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3: JAL r31, r0, :new_stru
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ST r1, r32, 0a, 16h
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@ -67,6 +66,6 @@ new_stru:
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LD r1, r254, 0a, 16h
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ADDI64 r254, r254, 16d
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JALA r0, r31, 0a
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code size: 658
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code size: 655
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ret: 0
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status: Ok(())
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@ -1,10 +1,10 @@
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continue_and_state_change:
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CP r13, r2
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CP r15, r0
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LI64 r16, 3d
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LI64 r14, 4d
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LI64 r17, 2d
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LI64 r18, 10d
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CP r15, r0
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LI64 r14, 4d
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6: JLTU r13, r18, :0
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JMP :1
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0: JNE r13, r17, :2
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@ -112,51 +112,49 @@ new:
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push:
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ADDI64 r254, r254, -80d
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ST r31, r254, 0a, 80h
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CP r38, r2
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CP r39, r3
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LI64 r37, 1d
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LD r33, r38, 8a, 8h
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LD r32, r38, 16a, 8h
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CP r36, r2
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CP r37, r3
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LI64 r35, 1d
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LD r33, r36, 8a, 8h
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LD r32, r36, 16a, 8h
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JNE r32, r33, :0
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JNE r32, r0, :1
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CP r32, r37
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CP r32, r35
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JMP :2
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1: MULI64 r32, r32, 2d
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2: CP r2, r32
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CP r3, r37
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CP r3, r35
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JAL r31, r0, :malloc
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ST r32, r38, 16a, 8h
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CP r35, r1
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JNE r35, r0, :3
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ST r32, r36, 16a, 8h
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CP r34, r1
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JNE r34, r0, :3
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CP r1, r0
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JMP :4
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3: LD r32, r38, 0a, 8h
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ADD64 r40, r33, r32
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CP r34, r35
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7: LD r33, r38, 0a, 8h
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LD r36, r38, 8a, 8h
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JNE r40, r32, :5
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JEQ r36, r0, :6
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CP r2, r33
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CP r3, r36
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CP r4, r37
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3: LD r32, r36, 0a, 8h
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ADD64 r38, r33, r32
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CP r33, r34
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7: LD r39, r36, 0a, 8h
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LD r40, r36, 8a, 8h
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JNE r38, r32, :5
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JEQ r40, r0, :6
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CP r2, r39
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CP r3, r40
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CP r4, r35
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JAL r31, r0, :free
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JMP :6
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6: ST r35, r38, 0a, 8h
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6: ST r34, r36, 0a, 8h
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JMP :0
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5: ADDI64 r36, r34, 1d
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ADDI64 r33, r32, 1d
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LD r32, r32, 0a, 1h
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ST r32, r34, 0a, 1h
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CP r32, r33
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CP r34, r36
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JMP :7
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0: LD r32, r38, 8a, 8h
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LD r33, r38, 0a, 8h
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ADD64 r33, r32, r33
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5: LD r39, r32, 0a, 1h
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ST r39, r33, 0a, 1h
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ADD64 r32, r32, r37
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ST r32, r38, 8a, 8h
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ADDI64 r33, r33, 1d
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ADDI64 r32, r32, 1d
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JMP :7
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0: LD r32, r36, 8a, 8h
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LD r33, r36, 0a, 8h
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ADD64 r33, r32, r33
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ST r37, r33, 0a, 1h
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ADD64 r32, r32, r35
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ST r32, r36, 8a, 8h
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CP r1, r33
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4: LD r31, r254, 0a, 80h
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ADDI64 r254, r254, 80d
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push:
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ADDI64 r254, r254, -88d
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ST r31, r254, 0a, 88h
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CP r38, r2
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CP r39, r3
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LI64 r37, 1d
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LD r33, r38, 8a, 8h
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LD r32, r38, 16a, 8h
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CP r36, r2
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CP r37, r3
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LI64 r35, 1d
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LD r33, r36, 8a, 8h
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LD r32, r36, 16a, 8h
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JNE r32, r33, :0
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JNE r32, r0, :1
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CP r32, r37
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CP r32, r35
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JMP :2
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1: MULI64 r32, r32, 2d
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2: LI64 r40, 8d
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MUL64 r34, r32, r40
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2: LI64 r38, 8d
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MUL64 r34, r32, r38
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CP r2, r34
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CP r3, r40
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CP r3, r38
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JAL r31, r0, :malloc
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ST r32, r38, 16a, 8h
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CP r35, r1
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JNE r35, r0, :3
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ST r32, r36, 16a, 8h
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CP r34, r1
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JNE r34, r0, :3
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CP r1, r0
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JMP :4
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3: MULI64 r33, r33, 8d
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LD r32, r38, 0a, 8h
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ADD64 r41, r32, r33
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CP r34, r35
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7: LD r33, r38, 0a, 8h
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LD r36, r38, 8a, 8h
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JNE r41, r32, :5
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JEQ r36, r0, :6
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MUL64 r32, r36, r40
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CP r2, r33
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LD r32, r36, 0a, 8h
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ADD64 r39, r32, r33
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CP r33, r34
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7: LD r40, r36, 0a, 8h
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LD r41, r36, 8a, 8h
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JNE r39, r32, :5
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JEQ r41, r0, :6
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MUL64 r32, r41, r38
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CP r2, r40
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CP r3, r32
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CP r4, r40
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CP r4, r38
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JAL r31, r0, :free
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JMP :6
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6: ST r35, r38, 0a, 8h
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6: ST r34, r36, 0a, 8h
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JMP :0
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5: ADDI64 r36, r34, 8d
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ADDI64 r33, r32, 8d
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LD r32, r32, 0a, 8h
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ST r32, r34, 0a, 8h
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CP r32, r33
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CP r34, r36
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5: LD r40, r32, 0a, 8h
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ST r40, r33, 0a, 8h
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ADDI64 r33, r33, 8d
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ADDI64 r32, r32, 8d
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JMP :7
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0: LD r32, r38, 8a, 8h
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0: LD r32, r36, 8a, 8h
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MULI64 r33, r32, 8d
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LD r34, r38, 0a, 8h
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LD r34, r36, 0a, 8h
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ADD64 r33, r34, r33
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ST r39, r33, 0a, 8h
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ADD64 r32, r32, r37
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ST r32, r38, 8a, 8h
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ST r37, r33, 0a, 8h
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ADD64 r32, r32, r35
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ST r32, r36, 8a, 8h
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CP r1, r33
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4: LD r31, r254, 0a, 88h
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ADDI64 r254, r254, 88d
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JALA r0, r31, 0a
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code size: 1635
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code size: 1623
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ret: 69
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status: Ok(())
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@ -1,21 +1,20 @@
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main:
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ADDI64 r254, r254, -128d
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ADDI64 r15, r254, 0d
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LI8 r16, 69b
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LI64 r17, 128d
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ADDI64 r14, r254, 0d
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LI8 r15, 69b
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LI64 r16, 128d
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CP r13, r0
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2: LD r14, r254, 42a, 1h
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JLTU r13, r17, :0
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ANDI r13, r14, 255d
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2: LD r17, r254, 42a, 1h
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JLTU r13, r16, :0
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ANDI r13, r17, 255d
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CP r1, r13
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JMP :1
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0: ADDI64 r14, r13, 1d
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ADD64 r13, r15, r13
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ST r16, r13, 0a, 1h
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CP r13, r14
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0: ADD64 r17, r14, r13
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ST r15, r17, 0a, 1h
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ADDI64 r13, r13, 1d
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JMP :2
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1: ADDI64 r254, r254, 128d
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JALA r0, r31, 0a
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code size: 141
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code size: 138
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ret: 69
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status: Ok(())
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@ -59,9 +59,9 @@ put_filled_rect:
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LD r14, r14, 0a, 8h
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ADD64 r26, r14, r26
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LD r28, r15, 0a, 8h
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MUL64 r15, r27, r25
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ADD64 r14, r14, r15
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ADD64 r15, r28, r26
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MUL64 r25, r27, r25
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ADD64 r14, r14, r25
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ADD64 r14, r28, r14
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3: JGTU r13, r20, :0
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JNE r13, r20, :1
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@ -12,8 +12,8 @@ create_back_buffer:
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0: LI8 r34, 255b
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CP r2, r34
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JAL r31, r0, :request_page
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SUB64 r32, r32, r33
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CP r35, r1
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SUB64 r32, r32, r33
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5: JGTS r32, r0, :2
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CP r1, r35
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JMP :1
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@ -11,9 +11,9 @@ main:
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JALA r0, r31, 0a
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sqrt:
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CP r14, r2
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CP r17, r0
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LI64 r16, 15d
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LI64 r15, 32768d
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CP r17, r0
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CP r13, r17
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3: JNE r15, r17, :0
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CP r1, r13
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@ -1,45 +1,44 @@
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main:
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ADDI64 r254, r254, -40d
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LI64 r17, 1d
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LI64 r16, 1d
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LI64 r15, 4d
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ADDI64 r17, r254, 0d
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CP r14, r0
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ADDI64 r18, r254, 0d
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CP r13, r14
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6: JNE r13, r15, :0
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ADDI64 r19, r254, 32d
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LI64 r20, 2d
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ADDI64 r18, r254, 32d
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LI64 r19, 2d
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CP r13, r14
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4: LD r15, r254, 16a, 8h
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JNE r13, r17, :1
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JNE r13, r16, :1
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CP r1, r15
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JMP :2
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1: ADD64 r16, r13, r17
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SUB64 r15, r20, r16
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MUL64 r21, r15, r20
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MUL64 r22, r13, r20
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1: ADD64 r15, r13, r16
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SUB64 r20, r19, r15
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MUL64 r20, r20, r19
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MUL64 r21, r13, r19
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CP r13, r14
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5: JNE r13, r20, :3
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CP r13, r16
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JMP :4
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3: ADD64 r15, r13, r17
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ADD64 r23, r22, r13
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ADD64 r13, r21, r13
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MULI64 r23, r23, 8d
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MULI64 r13, r13, 8d
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ADD64 r23, r18, r23
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ADD64 r13, r18, r13
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BMC r23, r19, 8h
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BMC r13, r23, 8h
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BMC r19, r13, 8h
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5: JNE r13, r19, :3
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CP r13, r15
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JMP :4
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3: ADD64 r22, r21, r13
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ADD64 r23, r20, r13
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MULI64 r22, r22, 8d
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MULI64 r23, r23, 8d
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ADD64 r22, r17, r22
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ADD64 r23, r17, r23
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BMC r22, r18, 8h
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BMC r23, r22, 8h
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BMC r18, r23, 8h
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ADD64 r13, r13, r16
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JMP :5
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0: MULI64 r16, r13, 8d
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ADD64 r16, r18, r16
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ST r13, r16, 0a, 8h
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ADD64 r13, r13, r17
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0: MULI64 r18, r13, 8d
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ADD64 r18, r17, r18
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ST r13, r18, 0a, 8h
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ADD64 r13, r13, r16
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JMP :6
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2: ADDI64 r254, r254, 40d
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JALA r0, r31, 0a
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code size: 267
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code size: 264
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ret: 0
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status: Ok(())
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@ -1,28 +1,26 @@
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main:
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ADDI64 r254, r254, -10240d
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LI8 r15, 64b
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LI64 r16, 1024d
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LI8 r14, 64b
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LI64 r15, 1024d
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ADDI64 r16, r254, 0d
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CP r13, r0
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ADDI64 r17, r254, 0d
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4: JLTU r13, r16, :0
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ADDI64 r13, r17, 1024d
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ADDI64 r15, r17, 10240d
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3: LD r14, r254, 2048a, 1h
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JLTU r13, r15, :1
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ANDI r13, r14, 255d
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4: JLTU r13, r15, :0
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ADDI64 r14, r16, 10240d
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ADDI64 r13, r16, 1024d
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3: LD r15, r254, 2048a, 1h
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JLTU r13, r14, :1
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ANDI r13, r15, 255d
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CP r1, r13
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JMP :2
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1: ADDI64 r14, r13, 1024d
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BMC r17, r13, 1024h
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CP r13, r14
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1: BMC r16, r13, 1024h
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ADDI64 r13, r13, 1024d
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JMP :3
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0: ADDI64 r14, r13, 1d
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ADD64 r13, r17, r13
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ST r15, r13, 0a, 1h
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CP r13, r14
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0: ADD64 r17, r16, r13
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ST r14, r17, 0a, 1h
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ADDI64 r13, r13, 1d
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JMP :4
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2: ADDI64 r254, r254, 10240d
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JALA r0, r31, 0a
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code size: 192
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code size: 186
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ret: 64
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status: Ok(())
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@ -1,10 +1,10 @@
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main:
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ADDI64 r254, r254, -64d
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ST r31, r254, 0a, 64h
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CP r34, r0
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LI64 r37, 65536d
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LI8 r35, 1b
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CP r36, r0
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CP r34, r0
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LI8 r35, 1b
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CP r32, r36
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7: JAL r31, r0, :opaque
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CP r33, r1
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