Move
This commit is contained in:
ondra05
parent
bd9b4e0364
commit
d4b2a1a266
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@ -1,7 +1,7 @@
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//! Block memory copier state machine
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//! Block memory copier state machine
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use {
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use {
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super::{Memory, MemoryAccessReason, VmRunError},
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super::{Memory, mem::MemoryAccessReason, VmRunError},
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core::{mem::MaybeUninit, task::Poll},
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core::{mem::MaybeUninit, task::Poll},
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};
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};
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@ -108,7 +108,7 @@ unsafe fn act(
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// Load to buffer
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// Load to buffer
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memory
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memory
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.load(src, buf, count)
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.load(src, buf, count)
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.map_err(|super::LoadError(addr)| BlkCopyError::Access {
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.map_err(|super::mem::LoadError(addr)| BlkCopyError::Access {
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access_reason: MemoryAccessReason::Load,
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access_reason: MemoryAccessReason::Load,
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addr,
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addr,
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})?;
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})?;
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@ -116,7 +116,7 @@ unsafe fn act(
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// Store from buffer
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// Store from buffer
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memory
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memory
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.store(dst, buf, count)
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.store(dst, buf, count)
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.map_err(|super::StoreError(addr)| BlkCopyError::Access {
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.map_err(|super::mem::StoreError(addr)| BlkCopyError::Access {
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access_reason: MemoryAccessReason::Store,
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access_reason: MemoryAccessReason::Store,
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addr,
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addr,
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})?;
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})?;
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459
hbvm/src/lib.rs
459
hbvm/src/lib.rs
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@ -14,6 +14,8 @@
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#![cfg_attr(feature = "nightly", feature(fn_align))]
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#![cfg_attr(feature = "nightly", feature(fn_align))]
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#![warn(missing_docs, clippy::missing_docs_in_private_items)]
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#![warn(missing_docs, clippy::missing_docs_in_private_items)]
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use mem::Memory;
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#[cfg(feature = "alloc")]
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#[cfg(feature = "alloc")]
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extern crate alloc;
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extern crate alloc;
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@ -21,16 +23,9 @@ pub mod mem;
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pub mod value;
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pub mod value;
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mod bmc;
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mod bmc;
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mod vmrun;
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use {
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use {bmc::BlockCopier, value::Value};
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bmc::BlockCopier,
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core::{cmp::Ordering, mem::size_of, ops},
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derive_more::Display,
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hbbytecode::{
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ParamBB, ParamBBB, ParamBBBB, ParamBBD, ParamBBDH, ParamBBW, ParamBD, ProgramVal,
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},
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value::{Value, ValueVariant},
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};
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/// HoleyBytes Virtual Machine
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/// HoleyBytes Virtual Machine
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pub struct Vm<Mem, const TIMER_QUOTIENT: usize> {
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pub struct Vm<Mem, const TIMER_QUOTIENT: usize> {
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@ -70,389 +65,6 @@ where
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copier: None,
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copier: None,
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}
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}
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}
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}
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/// Execute program
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///
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/// Program can return [`VmRunError`] if a trap handling failed
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#[cfg_attr(feature = "nightly", repr(align(4096)))]
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pub fn run(&mut self) -> Result<VmRunOk, VmRunError> {
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use hbbytecode::opcode::*;
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loop {
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// Big match
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//
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// Contribution guide:
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// - Zero register shall never be overwitten. It's value has to always be 0.
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// - Prefer `Self::read_reg` and `Self::write_reg` functions
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// - Extract parameters using `param!` macro
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// - Prioritise speed over code size
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// - Memory is cheap, CPUs not that much
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// - Do not heap allocate at any cost
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// - Yes, user-provided trap handler may allocate,
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// but that is not our »fault«.
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// - Unsafe is kinda must, but be sure you have validated everything
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// - Your contributions have to pass sanitizers and Miri
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// - Strictly follow the spec
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// - The spec does not specify how you perform actions, in what order,
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// just that the observable effects have to be performed in order and
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// correctly.
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// - Yes, we assume you run 64 bit CPU. Else ?conradluget a better CPU
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// sorry 8 bit fans, HBVM won't run on your Speccy :(
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unsafe {
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match self
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.memory
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.prog_read::<u8>(self.pc as _)
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.ok_or(VmRunError::ProgramFetchLoadEx(self.pc as _))?
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{
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UN => {
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self.decode::<()>();
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return Err(VmRunError::Unreachable);
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}
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TX => {
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self.decode::<()>();
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return Ok(VmRunOk::End);
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}
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NOP => self.decode::<()>(),
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ADD => self.binary_op(u64::wrapping_add),
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SUB => self.binary_op(u64::wrapping_sub),
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MUL => self.binary_op(u64::wrapping_mul),
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AND => self.binary_op::<u64>(ops::BitAnd::bitand),
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OR => self.binary_op::<u64>(ops::BitOr::bitor),
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XOR => self.binary_op::<u64>(ops::BitXor::bitxor),
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SL => self.binary_op(|l, r| u64::wrapping_shl(l, r as u32)),
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SR => self.binary_op(|l, r| u64::wrapping_shr(l, r as u32)),
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SRS => self.binary_op(|l, r| i64::wrapping_shl(l, r as u32)),
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CMP => {
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// Compare a0 <=> a1
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// < → -1
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// > → 1
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// = → 0
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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.cast::<i64>()
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.cmp(&self.read_reg(a1).cast::<i64>())
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as i64,
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);
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}
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CMPU => {
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// Unsigned comparsion
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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.cast::<u64>()
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.cmp(&self.read_reg(a1).cast::<u64>())
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as i64,
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);
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}
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NOT => {
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// Logical negation
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(tg, !self.read_reg(a0).cast::<u64>());
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}
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NEG => {
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// Bitwise negation
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(
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tg,
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match self.read_reg(a0).cast::<u64>() {
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0 => 1_u64,
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_ => 0,
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},
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);
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}
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DIR => {
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// Fused Division-Remainder
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let ParamBBBB(dt, rt, a0, a1) = self.decode();
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let a0 = self.read_reg(a0).cast::<u64>();
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let a1 = self.read_reg(a1).cast::<u64>();
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self.write_reg(dt, a0.checked_div(a1).unwrap_or(u64::MAX));
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self.write_reg(rt, a0.checked_rem(a1).unwrap_or(u64::MAX));
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}
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ADDI => self.binary_op_imm(u64::wrapping_add),
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MULI => self.binary_op_imm(u64::wrapping_sub),
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ANDI => self.binary_op_imm::<u64>(ops::BitAnd::bitand),
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ORI => self.binary_op_imm::<u64>(ops::BitOr::bitor),
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XORI => self.binary_op_imm::<u64>(ops::BitXor::bitxor),
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SLI => self.binary_op_ims(u64::wrapping_shl),
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SRI => self.binary_op_ims(u64::wrapping_shr),
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SRSI => self.binary_op_ims(i64::wrapping_shr),
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CMPI => {
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let ParamBBD(tg, a0, imm) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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.cast::<i64>()
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.cmp(&Value::from(imm).cast::<i64>())
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as i64,
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);
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}
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CMPUI => {
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let ParamBBD(tg, a0, imm) = self.decode();
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self.write_reg(tg, self.read_reg(a0).cast::<u64>().cmp(&imm) as i64);
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}
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CP => {
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(tg, self.read_reg(a0));
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}
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SWA => {
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// Swap registers
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let ParamBB(r0, r1) = self.decode();
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match (r0, r1) {
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(0, 0) => (),
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(dst, 0) | (0, dst) => self.write_reg(dst, 0_u64),
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(r0, r1) => {
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core::ptr::swap(
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self.registers.get_unchecked_mut(usize::from(r0)),
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self.registers.get_unchecked_mut(usize::from(r1)),
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);
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}
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}
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}
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LI => {
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let ParamBD(tg, imm) = self.decode();
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self.write_reg(tg, imm);
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}
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LD => {
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// Load. If loading more than register size, continue on adjecent registers
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let ParamBBDH(dst, base, off, count) = self.decode();
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let n: u8 = match dst {
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0 => 1,
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_ => 0,
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};
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self.memory.load(
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self.ldst_addr_uber(dst, base, off, count, n)?,
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self.registers
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.as_mut_ptr()
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.add(usize::from(dst) + usize::from(n))
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.cast(),
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usize::from(count).saturating_sub(n.into()),
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)?;
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}
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ST => {
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// Store. Same rules apply as to LD
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let ParamBBDH(dst, base, off, count) = self.decode();
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self.memory.store(
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self.ldst_addr_uber(dst, base, off, count, 0)?,
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self.registers.as_ptr().add(usize::from(dst)).cast(),
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count.into(),
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)?;
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}
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BMC => {
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// Block memory copy
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match if let Some(copier) = &mut self.copier {
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// There is some copier, poll.
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copier.poll(&mut self.memory)
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} else {
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// There is none, make one!
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let ParamBBD(src, dst, count) = self.decode();
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// So we are still on BMC on next cycle
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self.pc -= size_of::<ParamBBD>() + 1;
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self.copier = Some(BlockCopier::new(
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self.read_reg(src).cast(),
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self.read_reg(dst).cast(),
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count as _,
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));
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self.copier
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.as_mut()
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.unwrap_unchecked() // SAFETY: We just assigned there
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.poll(&mut self.memory)
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} {
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// We are done, shift program counter
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core::task::Poll::Ready(Ok(())) => {
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self.copier = None;
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self.pc += size_of::<ParamBBD>() + 1;
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}
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// Error, shift program counter (for consistency)
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// and yield error
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core::task::Poll::Ready(Err(e)) => {
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self.pc += size_of::<ParamBBD>() + 1;
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return Err(e.into());
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}
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// Not done yet, proceed to next cycle
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core::task::Poll::Pending => (),
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}
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}
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BRC => {
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// Block register copy
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let ParamBBB(src, dst, count) = self.decode();
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if src.checked_add(count).is_none() || dst.checked_add(count).is_none() {
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return Err(VmRunError::RegOutOfBounds);
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}
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core::ptr::copy(
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self.registers.get_unchecked(usize::from(src)),
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self.registers.get_unchecked_mut(usize::from(dst)),
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usize::from(count),
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);
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}
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JAL => {
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// Jump and link. Save PC after this instruction to
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// specified register and jump to reg + offset.
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let ParamBBD(save, reg, offset) = self.decode();
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self.write_reg(save, self.pc as u64);
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self.pc =
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(self.read_reg(reg).cast::<u64>().saturating_add(offset)) as usize;
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}
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// Conditional jumps, jump only to immediates
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JEQ => self.cond_jmp::<u64>(Ordering::Equal),
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JNE => {
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let ParamBBD(a0, a1, jt) = self.decode();
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if self.read_reg(a0).cast::<u64>() != self.read_reg(a1).cast::<u64>() {
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self.pc = jt as usize;
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}
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}
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JLT => self.cond_jmp::<u64>(Ordering::Less),
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JGT => self.cond_jmp::<u64>(Ordering::Greater),
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JLTU => self.cond_jmp::<i64>(Ordering::Less),
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JGTU => self.cond_jmp::<i64>(Ordering::Greater),
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ECALL => {
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self.decode::<()>();
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// So we don't get timer interrupt after ECALL
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if TIMER_QUOTIENT != 0 {
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self.timer = self.timer.wrapping_add(1);
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}
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return Ok(VmRunOk::Ecall);
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}
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ADDF => self.binary_op::<f64>(ops::Add::add),
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SUBF => self.binary_op::<f64>(ops::Sub::sub),
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MULF => self.binary_op::<f64>(ops::Mul::mul),
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DIRF => {
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let ParamBBBB(dt, rt, a0, a1) = self.decode();
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let a0 = self.read_reg(a0).cast::<f64>();
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let a1 = self.read_reg(a1).cast::<f64>();
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self.write_reg(dt, a0 / a1);
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self.write_reg(rt, a0 % a1);
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}
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FMAF => {
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let ParamBBBB(dt, a0, a1, a2) = self.decode();
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self.write_reg(
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dt,
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self.read_reg(a0).cast::<f64>() * self.read_reg(a1).cast::<f64>()
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+ self.read_reg(a2).cast::<f64>(),
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);
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}
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NEGF => {
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let ParamBB(dt, a0) = self.decode();
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self.write_reg(dt, -self.read_reg(a0).cast::<f64>());
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}
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ITF => {
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let ParamBB(dt, a0) = self.decode();
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self.write_reg(dt, self.read_reg(a0).cast::<i64>() as f64);
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}
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FTI => {
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let ParamBB(dt, a0) = self.decode();
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self.write_reg(dt, self.read_reg(a0).cast::<f64>() as i64);
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}
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ADDFI => self.binary_op_imm::<f64>(ops::Add::add),
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MULFI => self.binary_op_imm::<f64>(ops::Mul::mul),
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op => return Err(VmRunError::InvalidOpcode(op)),
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}
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}
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|
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if TIMER_QUOTIENT != 0 {
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self.timer = self.timer.wrapping_add(1);
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if self.timer % TIMER_QUOTIENT == 0 {
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return Ok(VmRunOk::Timer);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Decode instruction operands
|
|
||||||
#[inline(always)]
|
|
||||||
unsafe fn decode<T: ProgramVal>(&mut self) -> T {
|
|
||||||
let pc1 = self.pc + 1;
|
|
||||||
let data = self.memory.prog_read_unchecked::<T>(pc1 as _);
|
|
||||||
self.pc += 1 + size_of::<T>();
|
|
||||||
data
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Perform binary operating over two registers
|
|
||||||
#[inline(always)]
|
|
||||||
unsafe fn binary_op<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
|
|
||||||
let ParamBBB(tg, a0, a1) = self.decode();
|
|
||||||
self.write_reg(
|
|
||||||
tg,
|
|
||||||
op(self.read_reg(a0).cast::<T>(), self.read_reg(a1).cast::<T>()),
|
|
||||||
);
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Perform binary operation over register and immediate
|
|
||||||
#[inline(always)]
|
|
||||||
unsafe fn binary_op_imm<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
|
|
||||||
let ParamBBD(tg, reg, imm) = self.decode();
|
|
||||||
self.write_reg(
|
|
||||||
tg,
|
|
||||||
op(self.read_reg(reg).cast::<T>(), Value::from(imm).cast::<T>()),
|
|
||||||
);
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Perform binary operation over register and shift immediate
|
|
||||||
#[inline(always)]
|
|
||||||
unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
|
|
||||||
let ParamBBW(tg, reg, imm) = self.decode();
|
|
||||||
self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm));
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Jump at `#3` if ordering on `#0 <=> #1` is equal to expected
|
|
||||||
#[inline(always)]
|
|
||||||
unsafe fn cond_jmp<T: ValueVariant + Ord>(&mut self, expected: Ordering) {
|
|
||||||
let ParamBBD(a0, a1, ja) = self.decode();
|
|
||||||
if self
|
|
||||||
.read_reg(a0)
|
|
||||||
.cast::<T>()
|
|
||||||
.cmp(&self.read_reg(a1).cast::<T>())
|
|
||||||
== expected
|
|
||||||
{
|
|
||||||
self.pc = ja as usize;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Read register
|
|
||||||
#[inline(always)]
|
|
||||||
unsafe fn read_reg(&self, n: u8) -> Value {
|
|
||||||
*self.registers.get_unchecked(n as usize)
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Write a register.
|
|
||||||
/// Writing to register 0 is no-op.
|
|
||||||
#[inline(always)]
|
|
||||||
unsafe fn write_reg(&mut self, n: u8, value: impl Into<Value>) {
|
|
||||||
if n != 0 {
|
|
||||||
*self.registers.get_unchecked_mut(n as usize) = value.into();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Load / Store Address check-computation überfunction
|
|
||||||
#[inline(always)]
|
|
||||||
unsafe fn ldst_addr_uber(
|
|
||||||
&self,
|
|
||||||
dst: u8,
|
|
||||||
base: u8,
|
|
||||||
offset: u64,
|
|
||||||
size: u16,
|
|
||||||
adder: u8,
|
|
||||||
) -> Result<u64, VmRunError> {
|
|
||||||
let reg = dst.checked_add(adder).ok_or(VmRunError::RegOutOfBounds)?;
|
|
||||||
|
|
||||||
if usize::from(reg) * 8 + usize::from(size) > 2048 {
|
|
||||||
Err(VmRunError::RegOutOfBounds)
|
|
||||||
} else {
|
|
||||||
self.read_reg(base)
|
|
||||||
.cast::<u64>()
|
|
||||||
.checked_add(offset)
|
|
||||||
.and_then(|x| x.checked_add(adder.into()))
|
|
||||||
.ok_or(VmRunError::AddrOutOfBounds)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Virtual machine halt error
|
/// Virtual machine halt error
|
||||||
|
|
@ -493,66 +105,3 @@ pub enum VmRunOk {
|
||||||
/// Environment call
|
/// Environment call
|
||||||
Ecall,
|
Ecall,
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Load-store memory access
|
|
||||||
pub trait Memory {
|
|
||||||
/// Load data from memory on address
|
|
||||||
///
|
|
||||||
/// # Safety
|
|
||||||
/// - Shall not overrun the buffer
|
|
||||||
unsafe fn load(&mut self, addr: u64, target: *mut u8, count: usize) -> Result<(), LoadError>;
|
|
||||||
|
|
||||||
/// Store data to memory on address
|
|
||||||
///
|
|
||||||
/// # Safety
|
|
||||||
/// - Shall not overrun the buffer
|
|
||||||
unsafe fn store(
|
|
||||||
&mut self,
|
|
||||||
addr: u64,
|
|
||||||
source: *const u8,
|
|
||||||
count: usize,
|
|
||||||
) -> Result<(), StoreError>;
|
|
||||||
|
|
||||||
/// Read from program memory to execute
|
|
||||||
///
|
|
||||||
/// # Safety
|
|
||||||
/// - Data read have to be valid
|
|
||||||
unsafe fn prog_read<T: ProgramVal>(&mut self, addr: u64) -> Option<T>;
|
|
||||||
|
|
||||||
/// Read from program memory to exectue
|
|
||||||
///
|
|
||||||
/// # Safety
|
|
||||||
/// - You have to be really sure that these bytes are there, understand?
|
|
||||||
unsafe fn prog_read_unchecked<T: ProgramVal>(&mut self, addr: u64) -> T;
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Unhandled load access trap
|
|
||||||
#[derive(Clone, Copy, Display, Debug, PartialEq, Eq)]
|
|
||||||
#[display(fmt = "Load access error at address {_0:#x}")]
|
|
||||||
pub struct LoadError(pub u64);
|
|
||||||
|
|
||||||
/// Unhandled store access trap
|
|
||||||
#[derive(Clone, Copy, Display, Debug, PartialEq, Eq)]
|
|
||||||
#[display(fmt = "Store access error at address {_0:#x}")]
|
|
||||||
pub struct StoreError(pub u64);
|
|
||||||
|
|
||||||
/// Reason to access memory
|
|
||||||
#[derive(Clone, Copy, Display, Debug, PartialEq, Eq)]
|
|
||||||
pub enum MemoryAccessReason {
|
|
||||||
/// Memory was accessed for load (read)
|
|
||||||
Load,
|
|
||||||
/// Memory was accessed for store (write)
|
|
||||||
Store,
|
|
||||||
}
|
|
||||||
|
|
||||||
impl From<LoadError> for VmRunError {
|
|
||||||
fn from(value: LoadError) -> Self {
|
|
||||||
Self::LoadAccessEx(value.0)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl From<StoreError> for VmRunError {
|
|
||||||
fn from(value: StoreError) -> Self {
|
|
||||||
Self::StoreAccessEx(value.0)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,11 @@
|
||||||
use {
|
use {
|
||||||
hbbytecode::valider::validate,
|
hbbytecode::valider::validate,
|
||||||
hbvm::{
|
hbvm::{
|
||||||
mem::softpaging::{paging::PageTable, HandlePageFault, PageSize, SoftPagedMem},
|
mem::{
|
||||||
MemoryAccessReason, Vm,
|
softpaging::{paging::PageTable, HandlePageFault, PageSize, SoftPagedMem},
|
||||||
|
MemoryAccessReason,
|
||||||
|
},
|
||||||
|
Vm,
|
||||||
},
|
},
|
||||||
std::io::{stdin, Read},
|
std::io::{stdin, Read},
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -1,3 +1,68 @@
|
||||||
//! Memory implementations
|
//! Memory implementations
|
||||||
|
|
||||||
|
use {derive_more::Display, hbbytecode::ProgramVal};
|
||||||
|
|
||||||
pub mod softpaging;
|
pub mod softpaging;
|
||||||
|
|
||||||
|
/// Load-store memory access
|
||||||
|
pub trait Memory {
|
||||||
|
/// Load data from memory on address
|
||||||
|
///
|
||||||
|
/// # Safety
|
||||||
|
/// - Shall not overrun the buffer
|
||||||
|
unsafe fn load(&mut self, addr: u64, target: *mut u8, count: usize) -> Result<(), LoadError>;
|
||||||
|
|
||||||
|
/// Store data to memory on address
|
||||||
|
///
|
||||||
|
/// # Safety
|
||||||
|
/// - Shall not overrun the buffer
|
||||||
|
unsafe fn store(
|
||||||
|
&mut self,
|
||||||
|
addr: u64,
|
||||||
|
source: *const u8,
|
||||||
|
count: usize,
|
||||||
|
) -> Result<(), StoreError>;
|
||||||
|
|
||||||
|
/// Read from program memory to execute
|
||||||
|
///
|
||||||
|
/// # Safety
|
||||||
|
/// - Data read have to be valid
|
||||||
|
unsafe fn prog_read<T: ProgramVal>(&mut self, addr: u64) -> Option<T>;
|
||||||
|
|
||||||
|
/// Read from program memory to exectue
|
||||||
|
///
|
||||||
|
/// # Safety
|
||||||
|
/// - You have to be really sure that these bytes are there, understand?
|
||||||
|
unsafe fn prog_read_unchecked<T: ProgramVal>(&mut self, addr: u64) -> T;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Unhandled load access trap
|
||||||
|
#[derive(Clone, Copy, Display, Debug, PartialEq, Eq)]
|
||||||
|
#[display(fmt = "Load access error at address {_0:#x}")]
|
||||||
|
pub struct LoadError(pub u64);
|
||||||
|
|
||||||
|
/// Unhandled store access trap
|
||||||
|
#[derive(Clone, Copy, Display, Debug, PartialEq, Eq)]
|
||||||
|
#[display(fmt = "Store access error at address {_0:#x}")]
|
||||||
|
pub struct StoreError(pub u64);
|
||||||
|
|
||||||
|
/// Reason to access memory
|
||||||
|
#[derive(Clone, Copy, Display, Debug, PartialEq, Eq)]
|
||||||
|
pub enum MemoryAccessReason {
|
||||||
|
/// Memory was accessed for load (read)
|
||||||
|
Load,
|
||||||
|
/// Memory was accessed for store (write)
|
||||||
|
Store,
|
||||||
|
}
|
||||||
|
|
||||||
|
impl From<LoadError> for crate::VmRunError {
|
||||||
|
fn from(value: LoadError) -> Self {
|
||||||
|
Self::LoadAccessEx(value.0)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
impl From<StoreError> for crate::VmRunError {
|
||||||
|
fn from(value: StoreError) -> Self {
|
||||||
|
Self::StoreAccessEx(value.0)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -12,7 +12,7 @@ pub mod paging;
|
||||||
pub mod mapping;
|
pub mod mapping;
|
||||||
|
|
||||||
use {
|
use {
|
||||||
crate::{LoadError, Memory, MemoryAccessReason, StoreError},
|
super::{LoadError, Memory, MemoryAccessReason, StoreError},
|
||||||
lookup::{AddrPageLookupError, AddrPageLookupOk, AddrPageLookuper},
|
lookup::{AddrPageLookupError, AddrPageLookupOk, AddrPageLookuper},
|
||||||
paging::{PageTable, Permission},
|
paging::{PageTable, Permission},
|
||||||
};
|
};
|
||||||
|
|
|
||||||
404
hbvm/src/vmrun.rs
Normal file
404
hbvm/src/vmrun.rs
Normal file
|
|
@ -0,0 +1,404 @@
|
||||||
|
//! Welcome to the land of The Great Dispatch Loop
|
||||||
|
//!
|
||||||
|
//! Have fun
|
||||||
|
|
||||||
|
use {
|
||||||
|
super::{
|
||||||
|
bmc::BlockCopier,
|
||||||
|
mem::Memory,
|
||||||
|
value::{Value, ValueVariant},
|
||||||
|
Vm, VmRunError, VmRunOk,
|
||||||
|
},
|
||||||
|
core::{cmp::Ordering, mem::size_of, ops},
|
||||||
|
hbbytecode::{
|
||||||
|
ParamBB, ParamBBB, ParamBBBB, ParamBBD, ParamBBDH, ParamBBW, ParamBD, ProgramVal,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
impl<Mem, const TIMER_QUOTIENT: usize> Vm<Mem, TIMER_QUOTIENT>
|
||||||
|
where
|
||||||
|
Mem: Memory,
|
||||||
|
{
|
||||||
|
/// Execute program
|
||||||
|
///
|
||||||
|
/// Program can return [`VmRunError`] if a trap handling failed
|
||||||
|
#[cfg_attr(feature = "nightly", repr(align(4096)))]
|
||||||
|
pub fn run(&mut self) -> Result<VmRunOk, VmRunError> {
|
||||||
|
use hbbytecode::opcode::*;
|
||||||
|
loop {
|
||||||
|
// Big match
|
||||||
|
//
|
||||||
|
// Contribution guide:
|
||||||
|
// - Zero register shall never be overwitten. It's value has to always be 0.
|
||||||
|
// - Prefer `Self::read_reg` and `Self::write_reg` functions
|
||||||
|
// - Extract parameters using `param!` macro
|
||||||
|
// - Prioritise speed over code size
|
||||||
|
// - Memory is cheap, CPUs not that much
|
||||||
|
// - Do not heap allocate at any cost
|
||||||
|
// - Yes, user-provided trap handler may allocate,
|
||||||
|
// but that is not our »fault«.
|
||||||
|
// - Unsafe is kinda must, but be sure you have validated everything
|
||||||
|
// - Your contributions have to pass sanitizers and Miri
|
||||||
|
// - Strictly follow the spec
|
||||||
|
// - The spec does not specify how you perform actions, in what order,
|
||||||
|
// just that the observable effects have to be performed in order and
|
||||||
|
// correctly.
|
||||||
|
// - Yes, we assume you run 64 bit CPU. Else ?conradluget a better CPU
|
||||||
|
// sorry 8 bit fans, HBVM won't run on your Speccy :(
|
||||||
|
unsafe {
|
||||||
|
match self
|
||||||
|
.memory
|
||||||
|
.prog_read::<u8>(self.pc as _)
|
||||||
|
.ok_or(VmRunError::ProgramFetchLoadEx(self.pc as _))?
|
||||||
|
{
|
||||||
|
UN => {
|
||||||
|
self.decode::<()>();
|
||||||
|
return Err(VmRunError::Unreachable);
|
||||||
|
}
|
||||||
|
TX => {
|
||||||
|
self.decode::<()>();
|
||||||
|
return Ok(VmRunOk::End);
|
||||||
|
}
|
||||||
|
NOP => self.decode::<()>(),
|
||||||
|
ADD => self.binary_op(u64::wrapping_add),
|
||||||
|
SUB => self.binary_op(u64::wrapping_sub),
|
||||||
|
MUL => self.binary_op(u64::wrapping_mul),
|
||||||
|
AND => self.binary_op::<u64>(ops::BitAnd::bitand),
|
||||||
|
OR => self.binary_op::<u64>(ops::BitOr::bitor),
|
||||||
|
XOR => self.binary_op::<u64>(ops::BitXor::bitxor),
|
||||||
|
SL => self.binary_op(|l, r| u64::wrapping_shl(l, r as u32)),
|
||||||
|
SR => self.binary_op(|l, r| u64::wrapping_shr(l, r as u32)),
|
||||||
|
SRS => self.binary_op(|l, r| i64::wrapping_shl(l, r as u32)),
|
||||||
|
CMP => {
|
||||||
|
// Compare a0 <=> a1
|
||||||
|
// < → -1
|
||||||
|
// > → 1
|
||||||
|
// = → 0
|
||||||
|
|
||||||
|
let ParamBBB(tg, a0, a1) = self.decode();
|
||||||
|
self.write_reg(
|
||||||
|
tg,
|
||||||
|
self.read_reg(a0)
|
||||||
|
.cast::<i64>()
|
||||||
|
.cmp(&self.read_reg(a1).cast::<i64>())
|
||||||
|
as i64,
|
||||||
|
);
|
||||||
|
}
|
||||||
|
CMPU => {
|
||||||
|
// Unsigned comparsion
|
||||||
|
let ParamBBB(tg, a0, a1) = self.decode();
|
||||||
|
self.write_reg(
|
||||||
|
tg,
|
||||||
|
self.read_reg(a0)
|
||||||
|
.cast::<u64>()
|
||||||
|
.cmp(&self.read_reg(a1).cast::<u64>())
|
||||||
|
as i64,
|
||||||
|
);
|
||||||
|
}
|
||||||
|
NOT => {
|
||||||
|
// Logical negation
|
||||||
|
let ParamBB(tg, a0) = self.decode();
|
||||||
|
self.write_reg(tg, !self.read_reg(a0).cast::<u64>());
|
||||||
|
}
|
||||||
|
NEG => {
|
||||||
|
// Bitwise negation
|
||||||
|
let ParamBB(tg, a0) = self.decode();
|
||||||
|
self.write_reg(
|
||||||
|
tg,
|
||||||
|
match self.read_reg(a0).cast::<u64>() {
|
||||||
|
0 => 1_u64,
|
||||||
|
_ => 0,
|
||||||
|
},
|
||||||
|
);
|
||||||
|
}
|
||||||
|
DIR => {
|
||||||
|
// Fused Division-Remainder
|
||||||
|
let ParamBBBB(dt, rt, a0, a1) = self.decode();
|
||||||
|
let a0 = self.read_reg(a0).cast::<u64>();
|
||||||
|
let a1 = self.read_reg(a1).cast::<u64>();
|
||||||
|
self.write_reg(dt, a0.checked_div(a1).unwrap_or(u64::MAX));
|
||||||
|
self.write_reg(rt, a0.checked_rem(a1).unwrap_or(u64::MAX));
|
||||||
|
}
|
||||||
|
ADDI => self.binary_op_imm(u64::wrapping_add),
|
||||||
|
MULI => self.binary_op_imm(u64::wrapping_sub),
|
||||||
|
ANDI => self.binary_op_imm::<u64>(ops::BitAnd::bitand),
|
||||||
|
ORI => self.binary_op_imm::<u64>(ops::BitOr::bitor),
|
||||||
|
XORI => self.binary_op_imm::<u64>(ops::BitXor::bitxor),
|
||||||
|
SLI => self.binary_op_ims(u64::wrapping_shl),
|
||||||
|
SRI => self.binary_op_ims(u64::wrapping_shr),
|
||||||
|
SRSI => self.binary_op_ims(i64::wrapping_shr),
|
||||||
|
CMPI => {
|
||||||
|
let ParamBBD(tg, a0, imm) = self.decode();
|
||||||
|
self.write_reg(
|
||||||
|
tg,
|
||||||
|
self.read_reg(a0)
|
||||||
|
.cast::<i64>()
|
||||||
|
.cmp(&Value::from(imm).cast::<i64>())
|
||||||
|
as i64,
|
||||||
|
);
|
||||||
|
}
|
||||||
|
CMPUI => {
|
||||||
|
let ParamBBD(tg, a0, imm) = self.decode();
|
||||||
|
self.write_reg(tg, self.read_reg(a0).cast::<u64>().cmp(&imm) as i64);
|
||||||
|
}
|
||||||
|
CP => {
|
||||||
|
let ParamBB(tg, a0) = self.decode();
|
||||||
|
self.write_reg(tg, self.read_reg(a0));
|
||||||
|
}
|
||||||
|
SWA => {
|
||||||
|
// Swap registers
|
||||||
|
let ParamBB(r0, r1) = self.decode();
|
||||||
|
match (r0, r1) {
|
||||||
|
(0, 0) => (),
|
||||||
|
(dst, 0) | (0, dst) => self.write_reg(dst, 0_u64),
|
||||||
|
(r0, r1) => {
|
||||||
|
core::ptr::swap(
|
||||||
|
self.registers.get_unchecked_mut(usize::from(r0)),
|
||||||
|
self.registers.get_unchecked_mut(usize::from(r1)),
|
||||||
|
);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
LI => {
|
||||||
|
let ParamBD(tg, imm) = self.decode();
|
||||||
|
self.write_reg(tg, imm);
|
||||||
|
}
|
||||||
|
LD => {
|
||||||
|
// Load. If loading more than register size, continue on adjecent registers
|
||||||
|
let ParamBBDH(dst, base, off, count) = self.decode();
|
||||||
|
let n: u8 = match dst {
|
||||||
|
0 => 1,
|
||||||
|
_ => 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
self.memory.load(
|
||||||
|
self.ldst_addr_uber(dst, base, off, count, n)?,
|
||||||
|
self.registers
|
||||||
|
.as_mut_ptr()
|
||||||
|
.add(usize::from(dst) + usize::from(n))
|
||||||
|
.cast(),
|
||||||
|
usize::from(count).saturating_sub(n.into()),
|
||||||
|
)?;
|
||||||
|
}
|
||||||
|
ST => {
|
||||||
|
// Store. Same rules apply as to LD
|
||||||
|
let ParamBBDH(dst, base, off, count) = self.decode();
|
||||||
|
self.memory.store(
|
||||||
|
self.ldst_addr_uber(dst, base, off, count, 0)?,
|
||||||
|
self.registers.as_ptr().add(usize::from(dst)).cast(),
|
||||||
|
count.into(),
|
||||||
|
)?;
|
||||||
|
}
|
||||||
|
BMC => {
|
||||||
|
// Block memory copy
|
||||||
|
match if let Some(copier) = &mut self.copier {
|
||||||
|
// There is some copier, poll.
|
||||||
|
copier.poll(&mut self.memory)
|
||||||
|
} else {
|
||||||
|
// There is none, make one!
|
||||||
|
let ParamBBD(src, dst, count) = self.decode();
|
||||||
|
|
||||||
|
// So we are still on BMC on next cycle
|
||||||
|
self.pc -= size_of::<ParamBBD>() + 1;
|
||||||
|
|
||||||
|
self.copier = Some(BlockCopier::new(
|
||||||
|
self.read_reg(src).cast(),
|
||||||
|
self.read_reg(dst).cast(),
|
||||||
|
count as _,
|
||||||
|
));
|
||||||
|
|
||||||
|
self.copier
|
||||||
|
.as_mut()
|
||||||
|
.unwrap_unchecked() // SAFETY: We just assigned there
|
||||||
|
.poll(&mut self.memory)
|
||||||
|
} {
|
||||||
|
// We are done, shift program counter
|
||||||
|
core::task::Poll::Ready(Ok(())) => {
|
||||||
|
self.copier = None;
|
||||||
|
self.pc += size_of::<ParamBBD>() + 1;
|
||||||
|
}
|
||||||
|
// Error, shift program counter (for consistency)
|
||||||
|
// and yield error
|
||||||
|
core::task::Poll::Ready(Err(e)) => {
|
||||||
|
self.pc += size_of::<ParamBBD>() + 1;
|
||||||
|
return Err(e.into());
|
||||||
|
}
|
||||||
|
// Not done yet, proceed to next cycle
|
||||||
|
core::task::Poll::Pending => (),
|
||||||
|
}
|
||||||
|
}
|
||||||
|
BRC => {
|
||||||
|
// Block register copy
|
||||||
|
let ParamBBB(src, dst, count) = self.decode();
|
||||||
|
if src.checked_add(count).is_none() || dst.checked_add(count).is_none() {
|
||||||
|
return Err(VmRunError::RegOutOfBounds);
|
||||||
|
}
|
||||||
|
|
||||||
|
core::ptr::copy(
|
||||||
|
self.registers.get_unchecked(usize::from(src)),
|
||||||
|
self.registers.get_unchecked_mut(usize::from(dst)),
|
||||||
|
usize::from(count),
|
||||||
|
);
|
||||||
|
}
|
||||||
|
JAL => {
|
||||||
|
// Jump and link. Save PC after this instruction to
|
||||||
|
// specified register and jump to reg + offset.
|
||||||
|
let ParamBBD(save, reg, offset) = self.decode();
|
||||||
|
self.write_reg(save, self.pc as u64);
|
||||||
|
self.pc =
|
||||||
|
(self.read_reg(reg).cast::<u64>().saturating_add(offset)) as usize;
|
||||||
|
}
|
||||||
|
// Conditional jumps, jump only to immediates
|
||||||
|
JEQ => self.cond_jmp::<u64>(Ordering::Equal),
|
||||||
|
JNE => {
|
||||||
|
let ParamBBD(a0, a1, jt) = self.decode();
|
||||||
|
if self.read_reg(a0).cast::<u64>() != self.read_reg(a1).cast::<u64>() {
|
||||||
|
self.pc = jt as usize;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
JLT => self.cond_jmp::<u64>(Ordering::Less),
|
||||||
|
JGT => self.cond_jmp::<u64>(Ordering::Greater),
|
||||||
|
JLTU => self.cond_jmp::<i64>(Ordering::Less),
|
||||||
|
JGTU => self.cond_jmp::<i64>(Ordering::Greater),
|
||||||
|
ECALL => {
|
||||||
|
self.decode::<()>();
|
||||||
|
|
||||||
|
// So we don't get timer interrupt after ECALL
|
||||||
|
if TIMER_QUOTIENT != 0 {
|
||||||
|
self.timer = self.timer.wrapping_add(1);
|
||||||
|
}
|
||||||
|
return Ok(VmRunOk::Ecall);
|
||||||
|
}
|
||||||
|
ADDF => self.binary_op::<f64>(ops::Add::add),
|
||||||
|
SUBF => self.binary_op::<f64>(ops::Sub::sub),
|
||||||
|
MULF => self.binary_op::<f64>(ops::Mul::mul),
|
||||||
|
DIRF => {
|
||||||
|
let ParamBBBB(dt, rt, a0, a1) = self.decode();
|
||||||
|
let a0 = self.read_reg(a0).cast::<f64>();
|
||||||
|
let a1 = self.read_reg(a1).cast::<f64>();
|
||||||
|
self.write_reg(dt, a0 / a1);
|
||||||
|
self.write_reg(rt, a0 % a1);
|
||||||
|
}
|
||||||
|
FMAF => {
|
||||||
|
let ParamBBBB(dt, a0, a1, a2) = self.decode();
|
||||||
|
self.write_reg(
|
||||||
|
dt,
|
||||||
|
self.read_reg(a0).cast::<f64>() * self.read_reg(a1).cast::<f64>()
|
||||||
|
+ self.read_reg(a2).cast::<f64>(),
|
||||||
|
);
|
||||||
|
}
|
||||||
|
NEGF => {
|
||||||
|
let ParamBB(dt, a0) = self.decode();
|
||||||
|
self.write_reg(dt, -self.read_reg(a0).cast::<f64>());
|
||||||
|
}
|
||||||
|
ITF => {
|
||||||
|
let ParamBB(dt, a0) = self.decode();
|
||||||
|
self.write_reg(dt, self.read_reg(a0).cast::<i64>() as f64);
|
||||||
|
}
|
||||||
|
FTI => {
|
||||||
|
let ParamBB(dt, a0) = self.decode();
|
||||||
|
self.write_reg(dt, self.read_reg(a0).cast::<f64>() as i64);
|
||||||
|
}
|
||||||
|
ADDFI => self.binary_op_imm::<f64>(ops::Add::add),
|
||||||
|
MULFI => self.binary_op_imm::<f64>(ops::Mul::mul),
|
||||||
|
op => return Err(VmRunError::InvalidOpcode(op)),
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if TIMER_QUOTIENT != 0 {
|
||||||
|
self.timer = self.timer.wrapping_add(1);
|
||||||
|
if self.timer % TIMER_QUOTIENT == 0 {
|
||||||
|
return Ok(VmRunOk::Timer);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Decode instruction operands
|
||||||
|
#[inline(always)]
|
||||||
|
unsafe fn decode<T: ProgramVal>(&mut self) -> T {
|
||||||
|
let pc1 = self.pc + 1;
|
||||||
|
let data = self.memory.prog_read_unchecked::<T>(pc1 as _);
|
||||||
|
self.pc += 1 + size_of::<T>();
|
||||||
|
data
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Perform binary operating over two registers
|
||||||
|
#[inline(always)]
|
||||||
|
unsafe fn binary_op<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
|
||||||
|
let ParamBBB(tg, a0, a1) = self.decode();
|
||||||
|
self.write_reg(
|
||||||
|
tg,
|
||||||
|
op(self.read_reg(a0).cast::<T>(), self.read_reg(a1).cast::<T>()),
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Perform binary operation over register and immediate
|
||||||
|
#[inline(always)]
|
||||||
|
unsafe fn binary_op_imm<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
|
||||||
|
let ParamBBD(tg, reg, imm) = self.decode();
|
||||||
|
self.write_reg(
|
||||||
|
tg,
|
||||||
|
op(self.read_reg(reg).cast::<T>(), Value::from(imm).cast::<T>()),
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Perform binary operation over register and shift immediate
|
||||||
|
#[inline(always)]
|
||||||
|
unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
|
||||||
|
let ParamBBW(tg, reg, imm) = self.decode();
|
||||||
|
self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm));
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Jump at `#3` if ordering on `#0 <=> #1` is equal to expected
|
||||||
|
#[inline(always)]
|
||||||
|
unsafe fn cond_jmp<T: ValueVariant + Ord>(&mut self, expected: Ordering) {
|
||||||
|
let ParamBBD(a0, a1, ja) = self.decode();
|
||||||
|
if self
|
||||||
|
.read_reg(a0)
|
||||||
|
.cast::<T>()
|
||||||
|
.cmp(&self.read_reg(a1).cast::<T>())
|
||||||
|
== expected
|
||||||
|
{
|
||||||
|
self.pc = ja as usize;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Read register
|
||||||
|
#[inline(always)]
|
||||||
|
unsafe fn read_reg(&self, n: u8) -> Value {
|
||||||
|
*self.registers.get_unchecked(n as usize)
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Write a register.
|
||||||
|
/// Writing to register 0 is no-op.
|
||||||
|
#[inline(always)]
|
||||||
|
unsafe fn write_reg(&mut self, n: u8, value: impl Into<Value>) {
|
||||||
|
if n != 0 {
|
||||||
|
*self.registers.get_unchecked_mut(n as usize) = value.into();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Load / Store Address check-computation überfunction
|
||||||
|
#[inline(always)]
|
||||||
|
unsafe fn ldst_addr_uber(
|
||||||
|
&self,
|
||||||
|
dst: u8,
|
||||||
|
base: u8,
|
||||||
|
offset: u64,
|
||||||
|
size: u16,
|
||||||
|
adder: u8,
|
||||||
|
) -> Result<u64, VmRunError> {
|
||||||
|
let reg = dst.checked_add(adder).ok_or(VmRunError::RegOutOfBounds)?;
|
||||||
|
|
||||||
|
if usize::from(reg) * 8 + usize::from(size) > 2048 {
|
||||||
|
Err(VmRunError::RegOutOfBounds)
|
||||||
|
} else {
|
||||||
|
self.read_reg(base)
|
||||||
|
.cast::<u64>()
|
||||||
|
.checked_add(offset)
|
||||||
|
.and_then(|x| x.checked_add(adder.into()))
|
||||||
|
.ok_or(VmRunError::AddrOutOfBounds)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
Loading…
Reference in a new issue