updates spec
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ondra05
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@ -35,40 +35,40 @@ constmod!(pub opcode(u8) {
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NEG = 13, "BB; #0 ← ~#1";
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NOT = 14, "BB; #0 ← !#1";
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ADDI = 18, "BBD; #0 ← #1 + imm #2";
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MULI = 19, "BBD; #0 ← #1 × imm #2";
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ANDI = 20, "BBD; #0 ← #1 & imm #2";
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ORI = 21, "BBD; #0 ← #1 | imm #2";
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XORI = 22, "BBD; #0 ← #1 ^ imm #2";
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SLI = 23, "BBD; #0 ← #1 « imm #2";
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SRI = 24, "BBD; #0 ← #1 » imm #2";
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SRSI = 25, "BBD; #0 ← #1 » imm #2 (signed)";
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CMPI = 26, "BBD; #0 ← #1 <=> imm #2";
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CMPUI = 27, "BBD; #0 ← #1 <=> imm #2 (unsigned)";
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ADDI = 15, "BBD; #0 ← #1 + imm #2";
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MULI = 16, "BBD; #0 ← #1 × imm #2";
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ANDI = 17, "BBD; #0 ← #1 & imm #2";
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ORI = 18, "BBD; #0 ← #1 | imm #2";
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XORI = 19, "BBD; #0 ← #1 ^ imm #2";
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SLI = 20, "BBD; #0 ← #1 « imm #2";
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SRI = 21, "BBD; #0 ← #1 » imm #2";
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SRSI = 22, "BBD; #0 ← #1 » imm #2 (signed)";
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CMPI = 23, "BBD; #0 ← #1 <=> imm #2";
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CMPUI = 24, "BBD; #0 ← #1 <=> imm #2 (unsigned)";
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CP = 28, "BB; Copy #0 ← #1";
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SWA = 29, "BB; Swap #0 and #1";
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LI = 30, "BD; #0 ← imm #1";
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LD = 31, "BBDB; #0 ← [#1 + imm #3], imm #4 bytes, overflowing";
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ST = 32, "BBDB; [#1 + imm #3] ← #0, imm #4 bytes, overflowing";
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BMC = 33, "BBD; [#0] ← [#1], imm #2 bytes";
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BRC = 34, "BBB; #0 ← #1, imm #2 registers";
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CP = 25, "BB; Copy #0 ← #1";
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SWA = 26, "BB; Swap #0 and #1";
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LI = 27, "BD; #0 ← imm #1";
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LD = 28, "BBDB; #0 ← [#1 + imm #3], imm #4 bytes, overflowing";
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ST = 29, "BBDB; [#1 + imm #3] ← #0, imm #4 bytes, overflowing";
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BMC = 30, "BBD; [#0] ← [#1], imm #2 bytes";
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BRC = 31, "BBB; #0 ← #1, imm #2 registers";
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JMP = 35, "BD; Unconditional jump [#0 + imm #1]";
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JEQ = 36, "BBD; if #0 = #1 → jump imm #2";
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JNE = 37, "BBD; if #0 ≠ #1 → jump imm #2";
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JLT = 38, "BBD; if #0 < #1 → jump imm #2";
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JGT = 39, "BBD; if #0 > #1 → jump imm #2";
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JLTU = 40, "BBD; if #0 < #1 → jump imm #2 (unsigned)";
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JGTU = 41, "BBD; if #0 > #1 → jump imm #2 (unsigned)";
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ECALL = 42, "N; Issue system call";
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JMP = 32, "BD; Unconditional jump [#0 + imm #1]";
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JEQ = 33, "BBD; if #0 = #1 → jump imm #2";
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JNE = 34, "BBD; if #0 ≠ #1 → jump imm #2";
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JLT = 35, "BBD; if #0 < #1 → jump imm #2";
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JGT = 36, "BBD; if #0 > #1 → jump imm #2";
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JLTU = 37, "BBD; if #0 < #1 → jump imm #2 (unsigned)";
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JGTU = 38, "BBD; if #0 > #1 → jump imm #2 (unsigned)";
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ECALL = 39, "N; Issue system call";
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ADDF = 43, "BBB; #0 ← #1 +. #2";
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MULF = 44, "BBB; #0 ← #1 +. #2";
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DIRF = 45, "BBBB; #0 ← #2 / #3, #1 ← #2 % #3";
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ADDF = 40, "BBB; #0 ← #1 +. #2";
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MULF = 41, "BBB; #0 ← #1 +. #2";
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DIRF = 42, "BBBB; #0 ← #2 / #3, #1 ← #2 % #3";
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ADDFI = 46, "BBD; #0 ← #1 +. imm #2";
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MULFI = 47, "BBD; #0 ← #1 *. imm #2";
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ADDFI = 43, "BBD; #0 ← #1 +. imm #2";
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MULFI = 44, "BBD; #0 ← #1 *. imm #2";
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});
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#[repr(packed)]
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60
spec.md
60
spec.md
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@ -93,22 +93,22 @@
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| Opcode | Name | Action |
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|:------:|:----:|:-----------------------:|
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| 18 | ADDI | Wrapping addition |
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| 19 | MULI | Wrapping subtraction |
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| 20 | ANDI | Bitand |
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| 21 | ORI | Bitor |
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| 22 | XORI | Bitxor |
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| 23 | SLI | Unsigned left bitshift |
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| 24 | SRI | Unsigned right bitshift |
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| 25 | SRSI | Signed right bitshift |
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| 15 | ADDI | Wrapping addition |
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| 16 | MULI | Wrapping subtraction |
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| 17 | ANDI | Bitand |
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| 18 | ORI | Bitor |
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| 19 | XORI | Bitxor |
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| 20 | SLI | Unsigned left bitshift |
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| 21 | SRI | Unsigned right bitshift |
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| 22 | SRSI | Signed right bitshift |
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### Comparsion
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- Comparsion is the same as when RRR type
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| Opcode | Name | Action |
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|:------:|:-----:|:-------------------:|
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| 26 | CMPI | Signed comparsion |
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| 27 | CMPUI | Unsigned comparsion |
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| 23 | CMPI | Signed comparsion |
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| 24 | CMPUI | Unsigned comparsion |
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## Register value set / copy
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@ -118,7 +118,7 @@
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| Opcode | Name | Action |
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|:------:|:----:|:------:|
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| 28 | CP | Copy |
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| 25 | CP | Copy |
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### Swap
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- Type BB
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@ -126,7 +126,7 @@
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| Opcode | Name | Action |
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|:------:|:----:|:------:|
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| 29 | SWA | Swap |
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| 26 | SWA | Swap |
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### Load immediate
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- Type BD
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@ -134,7 +134,7 @@
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| Opcode | Name | Action |
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|:------:|:----:|:--------------:|
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| 30 | LI | Load immediate |
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| 27 | LI | Load immediate |
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## Memory operations
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- Type BBDH
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@ -143,8 +143,8 @@
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### Load / Store
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| Opcode | Name | Action |
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|:------:|:----:|:---------------------------------------:|
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| 31 | LD | `#0 ← [#1 + imm #3], copy imm #4 bytes` |
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| 32 | ST | `[#1 + imm #3] ← #0, copy imm #4 bytes` |
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| 28 | LD | `#0 ← [#1 + imm #3], copy imm #4 bytes` |
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| 29 | ST | `[#1 + imm #3] ← #0, copy imm #4 bytes` |
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## Block copy
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- Block copy source and target can overlap
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@ -154,7 +154,7 @@
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| Opcode | Name | Action |
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|:------:|:----:|:--------------------------------:|
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| 33 | BMC | `[#0] ← [#1], copy imm #2 bytes` |
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| 30 | BMC | `[#0] ← [#1], copy imm #2 bytes` |
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### Register copy
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- Type BBB
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@ -162,7 +162,7 @@
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| Opcode | Name | Action |
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|:------:|:----:|:--------------------------------:|
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| 34 | BRC | `#0 ← #1, copy imm #2 registers` |
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| 31 | BRC | `#0 ← #1, copy imm #2 registers` |
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## Control flow
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@ -171,7 +171,7 @@
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| Opcode | Name | Action |
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|:------:|:----:|:---------------------:|
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| 35 | JMP | Jump at `#0 + imm #1` |
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| 32 | JMP | Jump at `#0 + imm #1` |
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### Conditional jumps
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- Type BBD
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@ -179,19 +179,19 @@
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| Opcode | Name | Comparsion |
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|:------:|:----:|:------------:|
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| 36 | JEQ | = |
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| 37 | JNE | ≠ |
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| 38 | JLT | < (signed) |
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| 39 | JGT | > (signed) |
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| 40 | JLTU | < (unsigned) |
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| 41 | JGTU | > (unsigned) |
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| 33 | JEQ | = |
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| 34 | JNE | ≠ |
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| 35 | JLT | < (signed) |
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| 36 | JGT | > (signed) |
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| 37 | JLTU | < (unsigned) |
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| 38 | JGTU | > (unsigned) |
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### Environment call
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- Type N
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| Opcode | Name | Action |
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|:------:|:-----:|:-------------------------------------:|
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| 42 | ECALL | Cause an trap to the host environment |
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| 39 | ECALL | Cause an trap to the host environment |
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## Floating point operations
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- Type BBB
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@ -199,15 +199,15 @@
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| Opcode | Name | Action |
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|:------:|:----:|:--------------:|
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| 43 | ADDF | Addition |
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| 44 | MULF | Multiplication |
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| 40 | ADDF | Addition |
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| 41 | MULF | Multiplication |
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### Division-remainder
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- Type BBBB
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| Opcode | Name | Action |
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|:------:|:----:|:--------------------------------------:|
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| 45 | DIRF | Same flow applies as for integer `DIR` |
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| 42 | DIRF | Same flow applies as for integer `DIR` |
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## Floating point immediate operations
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- Type BBD
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@ -215,8 +215,8 @@
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| Opcode | Name | Action |
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|:------:|:-----:|:--------------:|
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| 46 | ADDFI | Addition |
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| 47 | MULFI | Multiplication |
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| 43 | ADDFI | Addition |
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| 44 | MULFI | Multiplication |
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# Registers
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- There is 255 registers + one zero register (with index 0)
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