sb0[]-[]:
0: iCall { func: 1 }:[Def: v3i fixed(p1i)]
1: iCInt { value: 0 }:[Def: v6i reg]
2: iCInt { value: 30 }:[Def: v5i reg]
3: iCInt { value: 100 }:[Def: v4i reg]
4: iLoop:[]
eb0[VReg(vreg = 6, class = Int), VReg(vreg = 6, class = Int), VReg(vreg = 6, class = Int)]-[Block(1)]:
sb1[VReg(vreg = 18, class = Int), VReg(vreg = 8, class = Int), VReg(vreg = 15, class = Int)]-[Block(0), Block(11)]:
5: iIf:[Use: v8i reg, Use: v5i reg]
eb1[]-[Block(2), Block(10)]:
sb2[]-[Block(1)]:
6: iBinOp { op: Add }:[Def: v19i reg, Use: v18i reg]
7: iCall { func: 2 }:[Def: v20i fixed(p1i), Use: v6i fixed(p2i), Use: v19i fixed(p3i), Use: v5i fixed(p4i)]
8: iIf:[Use: v20i reg, Use: v15i reg]
eb2[]-[Block(3), Block(4)]:
sb3[]-[Block(2)]:
9: iReturn:[Use: v6i fixed(p1i)]
eb3[]-[]:
sb4[]-[Block(2)]:
10: iIf:[Use: v19i reg, Use: v4i reg]
eb4[]-[Block(5), Block(9)]:
sb5[]-[Block(4)]:
11: iLoop:[]
eb5[VReg(vreg = 19, class = Int)]-[Block(6)]:
sb6[VReg(vreg = 36, class = Int)]-[Block(5), Block(7)]:
12: iIf:[Use: v4i reg, Use: v36i reg]
eb6[]-[Block(7), Block(8)]:
sb7[]-[Block(6)]:
13: iBinOp { op: Add }:[Def: v41i reg, Use: v36i reg]
14: iLoop:[]
eb7[VReg(vreg = 41, class = Int)]-[Block(6)]:
sb8[]-[Block(6)]:
15: iReturn:[Use: v15i fixed(p1i)]
eb8[]-[]:
sb9[]-[Block(4)]:
16: iRegion:[]
eb9[VReg(vreg = 6, class = Int), VReg(vreg = 19, class = Int), VReg(vreg = 15, class = Int)]-[Block(11)]:
sb10[]-[Block(1)]:
17: iBinOp { op: Add }:[Def: v16i reg, Use: v15i reg]
18: iBinOp { op: Add }:[Def: v14i reg, Use: v8i reg]
19: iRegion:[]
eb10[VReg(vreg = 14, class = Int), VReg(vreg = 18, class = Int), VReg(vreg = 16, class = Int)]-[Block(11)]:
sb11[VReg(vreg = 32, class = Int), VReg(vreg = 33, class = Int), VReg(vreg = 34, class = Int)]-[Block(10), Block(9)]:
20: iLoop:[]
eb11[VReg(vreg = 33, class = Int), VReg(vreg = 32, class = Int), VReg(vreg = 34, class = Int)]-[Block(1)]: