#![no_std]

macro_rules! constmod {
    ($vis:vis $mname:ident($repr:ty) {
        $(#![doc = $mdoc:literal])?
        $($cname:ident = $val:expr $(,$doc:literal)?;)*
    }) => {
        $(#[doc = $mdoc])?
        $vis mod $mname {
            $(
                $(#[doc = $doc])?
                pub const $cname: $repr = $val;
            )*
        }
    };
}

constmod!(pub opcode(u8) {
    //! Opcode constant module

    NOP = 0, "N; Do nothing";

    ADD  = 1,  "RRR; #0 ← #1 + #2";
    SUB  = 2,  "RRR; #0 ← #1 - #2";
    MUL  = 3,  "RRR; #0 ← #1 × #2";
    DIV  = 4,  "RRR; #0 ← #1 ÷ #2";
    REM  = 5,  "RRR; #0 ← #1 % #2";
    AND  = 6,  "RRR; #0 ← #1 & #2";
    OR   = 7,  "RRR; #0 ← #1 | #2";
    XOR  = 8,  "RRR; #0 ← #1 ^ #2";
    SL   = 9,  "RRR; #0 ← #1 « #2";
    SR   = 10, "RRR; #0 ← #1 » #2";
    SRS  = 11, "RRR; #0 ← #1 » #2 (signed)";
    CMP  = 12, "RRR; #0 ← #1 <=> #2";
    CMPU = 13, "RRR; #0 ← #1 <=> #2 (unsigned)";
    NOT  = 14, "RR;  #0 ← !#1";

    ADDF  = 15, "RRR; #0 ← #1 +. #2";
    SUBF  = 16, "RRR; #0 ← #1 +. #2";
    MULF  = 17, "RRR; #0 ← #1 +. #2";
    DIVF  = 18, "RRR; #0 ← #1 +. #2";
    ADDI  = 19, "RRI; #0 ← #1 + imm #2";
    MULI  = 20, "RRI; #0 ← #1 × imm #2";
    REMI  = 21, "RRI; #0 ← #1 % imm #2";
    ANDI  = 22, "RRI; #0 ← #1 & imm #2";
    ORI   = 23, "RRI; #0 ← #1 | imm #2";
    XORI  = 24, "RRI; #0 ← #1 ^ imm #2";
    SLI   = 25, "RRI; #0 ← #1 « imm #2";
    SRI   = 26, "RRI; #0 ← #1 » imm #2";
    SRSI  = 27, "RRI; #0 ← #1 » imm #2 (signed)";
    CMPI  = 28, "RRI; #0 ← #1 <=> imm #2";
    CMPUI = 29, "RRI; #0 ← #1 <=> imm #2 (unsigned)";

    ADDFI = 30, "RRI; #0 ← #1 +. imm #2";
    MULFI = 31, "RRI; #0 ← #1 *. imm #2";

    CP = 32, "RR;  Copy #0 ← #1";
    LI = 33, "RI;  Load immediate, #0 ← imm #1";
    LB = 34, "RRI; Load byte (8 bits), #0 ← [#1 + imm #2]";
    LD = 35, "RRI; Load doublet (16 bits)";
    LQ = 36, "RRI; Load quadlet (32 bits)";
    LO = 37, "RRI; Load octlet (64 bits)";
    SB = 38, "RRI; Store byte, [#1 + imm #2] ← #0";
    SD = 39, "RRI; Store doublet";
    SQ = 40, "RRI; Store quadlet";
    SO = 41, "RRI; Store octlet";

    JMP   = 42, "RI;  Unconditional jump [#0 + imm #1]";
    JEQ   = 43, "RRI; if #0 = #1 → jump imm #2";
    JNE   = 44, "RRI; if #0 ≠ #1 → jump imm #2";
    JLT   = 45, "RRI; if #0 < #1 → jump imm #2";
    JGT   = 46, "RRI; if #0 > #1 → jump imm #2";
    JLTU  = 47, "RRI; if #0 < #1 → jump imm #2 (unsigned)";
    JGTU  = 48, "RRI; if #0 > #1 → jump imm #2 (unsigned)";
    RET   = 49, "N; Return";
    ECALL = 50, "N; Issue system call";
});

/// Register-register-register instruction parameter
#[repr(packed)]
pub struct ParamRRR(pub u8, pub u8, pub u8);

/// Register-register-immediate intruction parameter
#[repr(packed)]
pub struct ParamRRI(pub u8, pub u8, pub u64);

/// Register-register instruction parameter
#[repr(packed)]
pub struct ParamRR(pub u8, pub u8);

/// Register-immediate instruction parameter
#[repr(packed)]
pub struct ParamRI(pub u8, pub u64);

/// # Safety
/// Has to be valid to be decoded from bytecode.
pub unsafe trait OpParam {}
unsafe impl OpParam for ParamRRR {}
unsafe impl OpParam for ParamRRI {}
unsafe impl OpParam for ParamRR {}
unsafe impl OpParam for ParamRI {}
unsafe impl OpParam for u64 {}
unsafe impl OpParam for () {}