forked from AbleOS/holey-bytes
509 lines
20 KiB
Rust
509 lines
20 KiB
Rust
//! HoleyBytes Virtual Machine
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//!
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//! # Alloc feature
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//! - Enabled by default
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//! - Provides [`mem::Memory`] mapping / unmapping, as well as
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//! [`Default`] and [`Drop`] implementation
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// # General safety notice:
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// - Validation has to assure there is 256 registers (r0 - r255)
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// - Instructions have to be valid as specified (values and sizes)
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// - Mapped pages should be at least 4 KiB
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#![no_std]
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#![cfg_attr(feature = "nightly", feature(fn_align))]
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#[cfg(feature = "alloc")]
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extern crate alloc;
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pub mod mem;
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pub mod value;
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use {
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core::{cmp::Ordering, mem::size_of, ops},
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hbbytecode::{
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valider, OpParam, ParamBB, ParamBBB, ParamBBBB, ParamBBD, ParamBBDH, ParamBBW, ParamBD,
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},
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mem::{bmc::BlockCopier, HandlePageFault, Memory},
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value::{Value, ValueVariant},
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};
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/// HoleyBytes Virtual Machine
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pub struct Vm<'a, PfHandler, const TIMER_QUOTIENT: usize> {
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/// Holds 256 registers
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///
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/// Writing to register 0 is considered undefined behaviour
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/// in terms of HoleyBytes program execution
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pub registers: [Value; 256],
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/// Memory implementation
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pub memory: Memory,
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/// Trap handler
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pub pfhandler: PfHandler,
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/// Program counter
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pub pc: usize,
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/// Program
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program: &'a [u8],
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/// Cached program length (without unreachable end)
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program_len: usize,
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/// Program timer
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timer: usize,
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/// Saved block copier
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copier: Option<BlockCopier>,
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}
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impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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Vm<'a, PfHandler, TIMER_QUOTIENT>
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{
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/// Create a new VM with program and trap handler
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///
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/// # Safety
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/// Program code has to be validated
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pub unsafe fn new_unchecked(program: &'a [u8], traph: PfHandler, memory: Memory) -> Self {
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Self {
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registers: [Value::from(0_u64); 256],
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memory,
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pfhandler: traph,
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pc: 0,
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program_len: program.len() - 12,
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program,
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timer: 0,
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copier: None,
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}
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}
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/// Create a new VM with program and trap handler only if it passes validation
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pub fn new_validated(
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program: &'a [u8],
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traph: PfHandler,
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memory: Memory,
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) -> Result<Self, valider::Error> {
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valider::validate(program)?;
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Ok(unsafe { Self::new_unchecked(program, traph, memory) })
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}
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/// Execute program
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///
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/// Program can return [`VmRunError`] if a trap handling failed
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#[cfg_attr(feature = "nightly", repr(align(4096)))]
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pub fn run(&mut self) -> Result<VmRunOk, VmRunError> {
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use hbbytecode::opcode::*;
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loop {
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// Check instruction boundary
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if self.pc >= self.program_len {
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return Ok(VmRunOk::End);
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}
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// Big match
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//
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// Contribution guide:
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// - Zero register shall never be overwitten. It's value has to always be 0.
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// - Prefer `Self::read_reg` and `Self::write_reg` functions
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// - Extract parameters using `param!` macro
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// - Prioritise speed over code size
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// - Memory is cheap, CPUs not that much
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// - Do not heap allocate at any cost
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// - Yes, user-provided trap handler may allocate,
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// but that is not our »fault«.
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// - Unsafe is kinda must, but be sure you have validated everything
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// - Your contributions have to pass sanitizers and Miri
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// - Strictly follow the spec
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// - The spec does not specify how you perform actions, in what order,
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// just that the observable effects have to be performed in order and
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// correctly.
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// - Yes, we assume you run 64 bit CPU. Else ?conradluget a better CPU
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// sorry 8 bit fans, HBVM won't run on your Speccy :(
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unsafe {
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match *self.program.get_unchecked(self.pc) {
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UN => {
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self.decode::<()>();
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return Err(VmRunError::Unreachable);
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}
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NOP => self.decode::<()>(),
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ADD => self.binary_op(u64::wrapping_add),
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SUB => self.binary_op(u64::wrapping_sub),
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MUL => self.binary_op(u64::wrapping_mul),
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AND => self.binary_op::<u64>(ops::BitAnd::bitand),
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OR => self.binary_op::<u64>(ops::BitOr::bitor),
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XOR => self.binary_op::<u64>(ops::BitXor::bitxor),
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SL => self.binary_op(|l, r| u64::wrapping_shl(l, r as u32)),
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SR => self.binary_op(|l, r| u64::wrapping_shr(l, r as u32)),
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SRS => self.binary_op(|l, r| i64::wrapping_shl(l, r as u32)),
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CMP => {
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// Compare a0 <=> a1
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// < → -1
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// > → 1
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// = → 0
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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.cast::<i64>()
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.cmp(&self.read_reg(a1).cast::<i64>())
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as i64,
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);
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}
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CMPU => {
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// Unsigned comparsion
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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.cast::<u64>()
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.cmp(&self.read_reg(a1).cast::<u64>())
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as i64,
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);
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}
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NOT => {
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// Logical negation
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(tg, !self.read_reg(a0).cast::<u64>());
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}
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NEG => {
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// Bitwise negation
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(
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tg,
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match self.read_reg(a0).cast::<u64>() {
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0 => 1_u64,
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_ => 0,
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},
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);
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}
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DIR => {
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// Fused Division-Remainder
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let ParamBBBB(dt, rt, a0, a1) = self.decode();
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let a0 = self.read_reg(a0).cast::<u64>();
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let a1 = self.read_reg(a1).cast::<u64>();
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self.write_reg(dt, a0.checked_div(a1).unwrap_or(u64::MAX));
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self.write_reg(rt, a0.checked_rem(a1).unwrap_or(u64::MAX));
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}
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ADDI => self.binary_op_imm(u64::wrapping_add),
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MULI => self.binary_op_imm(u64::wrapping_sub),
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ANDI => self.binary_op_imm::<u64>(ops::BitAnd::bitand),
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ORI => self.binary_op_imm::<u64>(ops::BitOr::bitor),
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XORI => self.binary_op_imm::<u64>(ops::BitXor::bitxor),
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SLI => self.binary_op_ims(u64::wrapping_shl),
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SRI => self.binary_op_ims(u64::wrapping_shr),
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SRSI => self.binary_op_ims(i64::wrapping_shr),
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CMPI => {
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let ParamBBD(tg, a0, imm) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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.cast::<i64>()
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.cmp(&Value::from(imm).cast::<i64>())
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as i64,
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);
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}
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CMPUI => {
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let ParamBBD(tg, a0, imm) = self.decode();
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self.write_reg(tg, self.read_reg(a0).cast::<u64>().cmp(&imm) as i64);
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}
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CP => {
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let ParamBB(tg, a0) = self.decode();
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self.write_reg(tg, self.read_reg(a0));
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}
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SWA => {
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// Swap registers
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let ParamBB(r0, r1) = self.decode();
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match (r0, r1) {
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(0, 0) => (),
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(dst, 0) | (0, dst) => self.write_reg(dst, 0_u64),
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(r0, r1) => {
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core::ptr::swap(
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self.registers.get_unchecked_mut(usize::from(r0)),
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self.registers.get_unchecked_mut(usize::from(r1)),
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);
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}
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}
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}
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LI => {
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let ParamBD(tg, imm) = self.decode();
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self.write_reg(tg, imm);
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}
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LD => {
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// Load. If loading more than register size, continue on adjecent registers
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let ParamBBDH(dst, base, off, count) = self.decode();
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let n: u8 = match dst {
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0 => 1,
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_ => 0,
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};
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self.memory.load(
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self.ldst_addr_uber(dst, base, off, count, n)?,
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self.registers
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.as_mut_ptr()
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.add(usize::from(dst) + usize::from(n))
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.cast(),
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usize::from(count).saturating_sub(n.into()),
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&mut self.pfhandler,
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)?;
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}
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ST => {
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// Store. Same rules apply as to LD
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let ParamBBDH(dst, base, off, count) = self.decode();
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self.memory.store(
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self.ldst_addr_uber(dst, base, off, count, 0)?,
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self.registers.as_ptr().add(usize::from(dst)).cast(),
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count.into(),
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&mut self.pfhandler,
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)?;
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}
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BMC => {
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// Block memory copy
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match if let Some(copier) = &mut self.copier {
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// There is some copier, poll.
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copier.poll(&mut self.memory, &mut self.pfhandler)
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} else {
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// There is none, make one!
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let ParamBBD(src, dst, count) = self.decode();
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// So we are still on BMC on next cycle
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self.pc -= size_of::<ParamBBD>() + 1;
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self.copier = Some(BlockCopier::new(
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self.read_reg(src).cast(),
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self.read_reg(dst).cast(),
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count as _,
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));
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self.copier
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.as_mut()
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.unwrap_unchecked() // SAFETY: We just assigned there
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.poll(&mut self.memory, &mut self.pfhandler)
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} {
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// We are done, shift program counter
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core::task::Poll::Ready(Ok(())) => {
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self.copier = None;
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self.pc += size_of::<ParamBBD>() + 1;
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}
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// Error, shift program counter (for consistency)
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// and yield error
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core::task::Poll::Ready(Err(e)) => {
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self.pc += size_of::<ParamBBD>() + 1;
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return Err(e.into());
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}
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// Not done yet, proceed to next cycle
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core::task::Poll::Pending => (),
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}
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}
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BRC => {
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// Block register copy
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let ParamBBB(src, dst, count) = self.decode();
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if src.checked_add(count).is_none() || dst.checked_add(count).is_none() {
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return Err(VmRunError::RegOutOfBounds);
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}
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core::ptr::copy(
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self.registers.get_unchecked(usize::from(src)),
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self.registers.get_unchecked_mut(usize::from(dst)),
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usize::from(count),
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);
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}
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JAL => {
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// Jump and link. Save PC after this instruction to
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// specified register and jump to reg + offset.
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let ParamBBD(save, reg, offset) = self.decode();
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self.write_reg(save, self.pc as u64);
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self.pc =
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(self.read_reg(reg).cast::<u64>().saturating_add(offset)) as usize;
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}
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// Conditional jumps, jump only to immediates
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JEQ => self.cond_jmp::<u64>(Ordering::Equal),
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JNE => {
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let ParamBBD(a0, a1, jt) = self.decode();
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if self.read_reg(a0).cast::<u64>() != self.read_reg(a1).cast::<u64>() {
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self.pc = jt as usize;
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}
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}
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JLT => self.cond_jmp::<u64>(Ordering::Less),
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JGT => self.cond_jmp::<u64>(Ordering::Greater),
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JLTU => self.cond_jmp::<i64>(Ordering::Less),
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JGTU => self.cond_jmp::<i64>(Ordering::Greater),
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ECALL => {
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self.decode::<()>();
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// So we don't get timer interrupt after ECALL
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if TIMER_QUOTIENT != 0 {
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self.timer = self.timer.wrapping_add(1);
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}
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return Ok(VmRunOk::Ecall);
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}
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ADDF => self.binary_op::<f64>(ops::Add::add),
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SUBF => self.binary_op::<f64>(ops::Sub::sub),
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MULF => self.binary_op::<f64>(ops::Mul::mul),
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DIRF => {
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let ParamBBBB(dt, rt, a0, a1) = self.decode();
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let a0 = self.read_reg(a0).cast::<f64>();
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let a1 = self.read_reg(a1).cast::<f64>();
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self.write_reg(dt, a0 / a1);
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self.write_reg(rt, a0 % a1);
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}
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FMAF => {
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let ParamBBBB(dt, a0, a1, a2) = self.decode();
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self.write_reg(
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dt,
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self.read_reg(a0).cast::<f64>() * self.read_reg(a1).cast::<f64>()
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+ self.read_reg(a2).cast::<f64>(),
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);
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}
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NEGF => {
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let ParamBB(dt, a0) = self.decode();
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self.write_reg(dt, -self.read_reg(a0).cast::<f64>());
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}
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ITF => {
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let ParamBB(dt, a0) = self.decode();
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self.write_reg(dt, self.read_reg(a0).cast::<i64>() as f64);
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}
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FTI => {
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let ParamBB(dt, a0) = self.decode();
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self.write_reg(dt, self.read_reg(a0).cast::<f64>() as i64);
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}
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ADDFI => self.binary_op_imm::<f64>(ops::Add::add),
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MULFI => self.binary_op_imm::<f64>(ops::Mul::mul),
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op => return Err(VmRunError::InvalidOpcode(op)),
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}
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}
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if TIMER_QUOTIENT != 0 {
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self.timer = self.timer.wrapping_add(1);
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if self.timer % TIMER_QUOTIENT == 0 {
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return Ok(VmRunOk::Timer);
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}
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}
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}
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}
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/// Decode instruction operands
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#[inline]
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unsafe fn decode<T: OpParam>(&mut self) -> T {
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let data = self.program.as_ptr().add(self.pc + 1).cast::<T>().read();
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self.pc += 1 + size_of::<T>();
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data
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}
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/// Perform binary operating over two registers
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#[inline]
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unsafe fn binary_op<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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op(self.read_reg(a0).cast::<T>(), self.read_reg(a1).cast::<T>()),
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);
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}
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/// Perform binary operation over register and immediate
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#[inline]
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unsafe fn binary_op_imm<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
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let ParamBBD(tg, reg, imm) = self.decode();
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self.write_reg(
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tg,
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op(self.read_reg(reg).cast::<T>(), Value::from(imm).cast::<T>()),
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);
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}
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/// Perform binary operation over register and shift immediate
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#[inline]
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unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
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let ParamBBW(tg, reg, imm) = self.decode();
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self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm));
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}
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/// Jump at `#3` if ordering on `#0 <=> #1` is equal to expected
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#[inline]
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unsafe fn cond_jmp<T: ValueVariant + Ord>(&mut self, expected: Ordering) {
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let ParamBBD(a0, a1, ja) = self.decode();
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if self
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.read_reg(a0)
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.cast::<T>()
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.cmp(&self.read_reg(a1).cast::<T>())
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== expected
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{
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self.pc = ja as usize;
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}
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}
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/// Read register
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#[inline]
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unsafe fn read_reg(&self, n: u8) -> Value {
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*self.registers.get_unchecked(n as usize)
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}
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/// Write a register.
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/// Writing to register 0 is no-op.
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#[inline]
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unsafe fn write_reg(&mut self, n: u8, value: impl Into<Value>) {
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if n != 0 {
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*self.registers.get_unchecked_mut(n as usize) = value.into();
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}
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}
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/// Load / Store Address check-computation überfunction
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#[inline]
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unsafe fn ldst_addr_uber(
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&self,
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dst: u8,
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base: u8,
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offset: u64,
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size: u16,
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adder: u8,
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) -> Result<u64, VmRunError> {
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let reg = dst.checked_add(adder).ok_or(VmRunError::RegOutOfBounds)?;
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if usize::from(reg) * 8 + usize::from(size) > 2048 {
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Err(VmRunError::RegOutOfBounds)
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} else {
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self.read_reg(base)
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.cast::<u64>()
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.checked_add(offset)
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.and_then(|x| x.checked_add(adder.into()))
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.ok_or(VmRunError::AddrOutOfBounds)
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}
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}
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}
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/// Virtual machine halt error
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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#[repr(u8)]
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pub enum VmRunError {
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/// Tried to execute invalid instruction
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InvalidOpcode(u8),
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/// Unhandled load access exception
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LoadAccessEx(u64),
|
|
|
|
/// Unhandled store access exception
|
|
StoreAccessEx(u64),
|
|
|
|
/// Register out-of-bounds access
|
|
RegOutOfBounds,
|
|
|
|
/// Address out-of-bounds
|
|
AddrOutOfBounds,
|
|
|
|
/// Reached unreachable code
|
|
Unreachable,
|
|
}
|
|
|
|
/// Virtual machine halt ok
|
|
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
|
pub enum VmRunOk {
|
|
/// Program has eached its end
|
|
End,
|
|
|
|
/// Program was interrupted by a timer
|
|
Timer,
|
|
|
|
/// Environment call
|
|
Ecall,
|
|
}
|