forked from AbleOS/holey-bytes
fixing another problem with rescheduling
This commit is contained in:
parent
0d87bf8f09
commit
3c86eafe72
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@ -1465,6 +1465,19 @@ main := fn(): uint {
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}
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}
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```
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```
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#### global_variable_wiredness
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```hb
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ports := false
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inb := fn(): uint return 0
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main := fn(): void {
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if ports {
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ports = inb() == 0x0
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}
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}
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```
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### Just Testing Optimizations
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### Just Testing Optimizations
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#### null_check_test
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#### null_check_test
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@ -4874,6 +4874,7 @@ mod tests {
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writing_into_string;
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writing_into_string;
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request_page;
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request_page;
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tests_ptr_to_ptr_copy;
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tests_ptr_to_ptr_copy;
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global_variable_wiredness;
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// Just Testing Optimizations;
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// Just Testing Optimizations;
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const_folding_with_arg;
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const_folding_with_arg;
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@ -236,7 +236,12 @@ impl Backend for HbvmBackend {
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if !matches!(nodes[stck].kind, Kind::Stck | Kind::Arg) {
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if !matches!(nodes[stck].kind, Kind::Stck | Kind::Arg) {
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debug_assert_matches!(
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debug_assert_matches!(
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nodes[stck].kind,
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nodes[stck].kind,
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Kind::Phi | Kind::Return | Kind::Load | Kind::Call { .. } | Kind::Stre
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Kind::Phi
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| Kind::Return
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| Kind::Load
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| Kind::Call { .. }
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| Kind::Stre
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| Kind::Join
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);
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);
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continue;
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continue;
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}
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}
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@ -334,40 +339,18 @@ impl Backend for HbvmBackend {
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impl Nodes {
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impl Nodes {
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fn reschedule_block(&mut self, from: Nid, outputs: &mut Vc) {
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fn reschedule_block(&mut self, from: Nid, outputs: &mut Vc) {
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// NOTE: this code is horible
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// NOTE: this code is horible
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let from = Some(&from);
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let fromc = Some(&from);
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let mut buf = Vec::with_capacity(outputs.len());
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let mut buf = Vec::with_capacity(outputs.len());
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let mut seen = BitSet::default();
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let mut seen = BitSet::default();
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seen.clear(self.values.len());
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seen.clear(self.values.len());
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for &o in outputs.iter() {
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for &o in outputs.iter() {
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if !self.is_cfg(o) {
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if (!self.is_cfg(o)
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continue;
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&& self[o].outputs.iter().any(|&oi| {
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}
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self[oi].kind != Kind::Phi && self[oi].inputs.first() == fromc && !seen.get(oi)
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}))
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seen.set(o);
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|| !seen.set(o)
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let mut cursor = buf.len();
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buf.push(o);
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while let Some(&n) = buf.get(cursor) {
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for &i in &self[n].inputs[1..] {
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if from == self[i].inputs.first()
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&& self[i]
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.outputs
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.iter()
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.all(|&o| self[o].inputs.first() != from || seen.get(o))
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&& seen.set(i)
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{
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{
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for &o in outputs.iter().filter(|&&n| n == i) {
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buf.push(o);
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}
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}
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}
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cursor += 1;
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}
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}
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for &o in outputs.iter() {
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if !seen.set(o) {
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continue;
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continue;
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}
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}
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let mut cursor = buf.len();
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let mut cursor = buf.len();
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@ -376,11 +359,12 @@ impl Nodes {
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}
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}
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while let Some(&n) = buf.get(cursor) {
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while let Some(&n) = buf.get(cursor) {
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for &i in &self[n].inputs[1..] {
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for &i in &self[n].inputs[1..] {
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if from == self[i].inputs.first()
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if fromc == self[i].inputs.first()
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&& self[i]
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&& self[i].outputs.iter().all(|&o| {
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.outputs
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self[o].kind == Kind::Phi
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.iter()
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|| self[o].inputs.first() != fromc
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.all(|&o| self[o].inputs.first() != from || seen.get(o))
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|| seen.get(o)
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})
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&& seen.set(i)
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&& seen.set(i)
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{
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{
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for &o in outputs.iter().filter(|&&n| n == i) {
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for &o in outputs.iter().filter(|&&n| n == i) {
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@ -392,7 +376,18 @@ impl Nodes {
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}
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}
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}
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}
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buf.sort_by_key(|&n| !self.is_cfg(n));
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debug_assert_eq!(
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outputs.iter().filter(|&&n| !seen.get(n)).copied().collect::<Vec<_>>(),
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vec![],
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"{:?} {from:?} {:?}",
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outputs
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.iter()
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.filter(|&&n| !seen.get(n))
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.copied()
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.map(|n| (n, &self[n]))
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.collect::<Vec<_>>(),
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self[from]
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);
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if outputs.len() != buf.len() {
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if outputs.len() != buf.len() {
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panic!("{:?} {:?}", outputs, buf);
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panic!("{:?} {:?}", outputs, buf);
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23
lang/tests/son_tests_global_variable_wiredness.txt
Normal file
23
lang/tests/son_tests_global_variable_wiredness.txt
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@ -0,0 +1,23 @@
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inb:
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LI64 r1, 0d
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JALA r0, r31, 0a
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main:
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ADDI64 r254, r254, -40d
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ST r31, r254, 0a, 40h
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LRA r32, r0, :ports
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LD r33, r32, 0a, 1h
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ANDI r33, r33, 255d
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JNE r33, r0, :0
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JMP :1
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0: JAL r31, r0, :inb
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LI64 r34, 0d
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CMPU r35, r1, r34
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CMPUI r35, r35, 0d
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NOT r35, r35
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ST r35, r32, 0a, 1h
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1: LD r31, r254, 0a, 40h
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ADDI64 r254, r254, 40d
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JALA r0, r31, 0a
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code size: 178
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ret: 0
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status: Ok(())
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@ -50,18 +50,20 @@ optional:
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JALA r0, r31, 0a
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JALA r0, r31, 0a
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optionala:
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optionala:
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ADDI64 r254, r254, -48d
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ADDI64 r254, r254, -48d
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ADDI64 r5, r254, 0d
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ADDI64 r5, r254, 8d
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ADDI64 r4, r254, 16d
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ADDI64 r4, r254, 16d
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ST r5, r254, 16a, 8h
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ST r5, r254, 16a, 8h
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LI64 r9, 1d
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LI64 r9, 1d
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ST r9, r254, 24a, 8h
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ST r9, r254, 24a, 8h
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ADDI64 r12, r254, 8d
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ADDI64 r12, r254, 0d
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ST r12, r254, 32a, 8h
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ST r12, r254, 32a, 8h
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LI64 r11, 0d
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LI64 r11, 0d
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ST r11, r254, 0a, 8h
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ST r11, r254, 8a, 8h
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ST r11, r254, 40a, 8h
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ST r11, r254, 40a, 8h
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BMC r4, r1, 32h
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BMC r4, r1, 32h
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ADDI64 r254, r254, 48d
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ADDI64 r254, r254, 48d
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JALA r0, r31, 0a
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JALA r0, r31, 0a
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code size: 577
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code size: 603
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ret: 100
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ret: 100
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status: Ok(())
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status: Ok(())
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@ -0,0 +1,35 @@
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main:
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ADDI64 r254, r254, -72d
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ST r31, r254, 0a, 72h
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LI8 r32, 0b
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LI64 r33, 65536d
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LI8 r34, 1b
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LI64 r35, 0d
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CP r36, r35
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7: JAL r31, r0, :opaque
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JLTU r36, r1, :0
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JMP :1
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0: CP r37, r35
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8: JAL r31, r0, :opaque
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JLTU r37, r1, :2
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CP r38, r34
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JMP :3
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2: JNE r37, r33, :4
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CP r38, r32
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3: ANDI r39, r38, 255d
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JNE r39, r35, :5
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JMP :6
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5: ADDI64 r36, r36, 1d
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6: JMP :7
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4: ADDI64 r37, r37, 1d
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JMP :8
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1: LD r31, r254, 0a, 72h
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ADDI64 r254, r254, 72d
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JALA r0, r31, 0a
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opaque:
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LI64 r1, 2147483648d
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JALA r0, r31, 0a
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timed out
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code size: 218
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ret: 2147483648
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status: Ok(())
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0
offense.hb
Normal file
0
offense.hb
Normal file
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