forked from AbleOS/holey-bytes
fixing yet another edge case
This commit is contained in:
parent
c61efc3933
commit
b6274f3455
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@ -617,12 +617,14 @@ main := fn(): uint {
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#### storing_into_nullable_struct
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#### storing_into_nullable_struct
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```hb
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```hb
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StructA := struct {b: StructB}
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StructA := struct {b: StructB, c: ^uint, d: uint}
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StructB := struct {c: uint}
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StructB := struct {g: ^uint, c: StructC}
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StructC := struct {c: uint}
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optionala := fn(): ?StructA {
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optionala := fn(): ?StructA {
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return .(.(1))
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return .(.(&0, .(1)), &0, 0)
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}
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}
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Struct := struct {inner: uint}
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Struct := struct {inner: uint}
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@ -635,13 +637,17 @@ do_stuff := fn(arg: uint): uint {
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return arg
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return arg
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}
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}
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just_read := fn(s: StructA): void {
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}
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main := fn(): uint {
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main := fn(): uint {
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a := optionala()
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a := optionala()
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if a == null {
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if a == null {
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return 10
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return 10
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}
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}
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a.b = .(0)
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a.b.c = .(0)
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innera := do_stuff(a.b.c)
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just_read(a)
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innera := do_stuff(a.b.c.c)
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val := optional()
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val := optional()
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if val == null {
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if val == null {
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@ -1247,20 +1247,22 @@ impl Nodes {
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},
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},
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);
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);
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let size = tys.size_of(ty);
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let size = tys.size_of(ty);
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let mut offset = 0;
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loop {
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loop {
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break match s[region].kind {
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match s[region].kind {
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_ if region == loc => 0..size as usize,
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_ if region == loc => {
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break offset as usize..offset as usize + size as usize
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}
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Kind::Assert { kind: AssertKind::NullCheck, .. } => {
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Kind::Assert { kind: AssertKind::NullCheck, .. } => {
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region = s[region].inputs[2];
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region = s[region].inputs[2]
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continue;
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}
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}
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Kind::BinOp { op: TokenKind::Add | TokenKind::Sub }
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Kind::BinOp { op: TokenKind::Add | TokenKind::Sub }
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if let Kind::CInt { value } = s[s[region].inputs[2]].kind
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if let Kind::CInt { value } = s[s[region].inputs[2]].kind =>
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&& s[region].inputs[1] == loc =>
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{
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{
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value as usize..value as usize + size as usize
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offset += value;
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region = s[region].inputs[1];
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}
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}
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_ => 0..full_size as usize,
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_ => break 0..full_size as usize,
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};
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};
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}
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}
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}
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}
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@ -1280,6 +1282,8 @@ impl Nodes {
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if range.start >= load_range.end || range.end <= load_range.start {
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if range.start >= load_range.end || range.end <= load_range.start {
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cursor = self[cursor].inputs[3];
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cursor = self[cursor].inputs[3];
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} else {
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} else {
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let reg = self.aclass_index(self[cursor].inputs[2]).1;
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self[reg].peep_triggers.push(target);
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break;
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break;
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}
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}
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}
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}
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@ -4327,7 +4331,7 @@ impl<'a> Codegen<'a> {
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self.ci.nodes.basic_blocks();
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self.ci.nodes.basic_blocks();
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self.ci.nodes.graphviz(self.ty_display(ty::Id::VOID));
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self.ci.nodes.graphviz(self.ty_display(ty::Id::VOID));
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} else {
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} else {
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//self.ci.nodes.graphviz_in_browser(self.ty_display(ty::Id::VOID));
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self.ci.nodes.graphviz_in_browser(self.ty_display(ty::Id::VOID));
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}
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}
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self.errors.borrow().len() == prev_err_len
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self.errors.borrow().len() == prev_err_len
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@ -1,40 +1,42 @@
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do_stuff:
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do_stuff:
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CP r1, r2
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CP r1, r2
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JALA r0, r31, 0a
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JALA r0, r31, 0a
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just_read:
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JALA r0, r31, 0a
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main:
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main:
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ADDI64 r254, r254, -104d
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ADDI64 r254, r254, -120d
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ST r31, r254, 32a, 72h
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ST r31, r254, 48a, 72h
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ADDI64 r32, r254, 16d
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ADDI64 r32, r254, 16d
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CP r1, r32
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JAL r31, r0, :optionala
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JAL r31, r0, :optionala
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ST r1, r254, 16a, 16h
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CP r2, r32
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LI8 r33, 0b
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LI64 r33, 0d
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LD r34, r254, 16a, 1h
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LD r34, r254, 16a, 8h
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ANDI r34, r34, 255d
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ANDI r33, r33, 255d
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JNE r34, r33, :0
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JNE r34, r33, :0
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LI64 r1, 10d
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LI64 r1, 10d
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JMP :1
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JMP :1
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0: LI64 r35, 0d
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0: ST r33, r254, 24a, 8h
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ST r35, r254, 24a, 8h
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JAL r31, r0, :just_read
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LD r2, r254, 24a, 8h
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LD r2, r254, 24a, 8h
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JAL r31, r0, :do_stuff
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JAL r31, r0, :do_stuff
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CP r36, r1
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CP r35, r1
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ADDI64 r37, r254, 0d
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ADDI64 r36, r254, 0d
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JAL r31, r0, :optional
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JAL r31, r0, :optional
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ST r1, r254, 0a, 16h
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ST r1, r254, 0a, 16h
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LI8 r37, 0b
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LD r38, r254, 0a, 1h
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LD r38, r254, 0a, 1h
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ANDI r38, r38, 255d
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ANDI r38, r38, 255d
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ANDI r33, r33, 255d
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ANDI r37, r37, 255d
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JNE r38, r33, :2
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JNE r38, r37, :2
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LI64 r1, 20d
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LI64 r1, 20d
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JMP :1
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JMP :1
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2: LI64 r39, 100d
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2: LI64 r39, 100d
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ST r39, r254, 8a, 8h
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ST r39, r254, 8a, 8h
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LD r2, r254, 8a, 8h
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LD r2, r254, 8a, 8h
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JAL r31, r0, :do_stuff
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JAL r31, r0, :do_stuff
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ADD64 r1, r1, r36
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ADD64 r1, r1, r35
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1: LD r31, r254, 32a, 72h
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1: LD r31, r254, 48a, 72h
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ADDI64 r254, r254, 104d
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ADDI64 r254, r254, 120d
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JALA r0, r31, 0a
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JALA r0, r31, 0a
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optional:
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optional:
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ADDI64 r254, r254, -16d
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ADDI64 r254, r254, -16d
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@ -47,18 +49,22 @@ optional:
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ADDI64 r254, r254, 16d
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ADDI64 r254, r254, 16d
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JALA r0, r31, 0a
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JALA r0, r31, 0a
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optionala:
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optionala:
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ADDI64 r254, r254, -24d
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ADDI64 r254, r254, -56d
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ADDI64 r1, r254, 0d
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ADDI64 r7, r254, 0d
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LI64 r3, 1d
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LI64 r8, 1d
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LI8 r7, 1b
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ADDI64 r9, r254, 16d
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ADDI64 r6, r254, 8d
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ADDI64 r6, r254, 24d
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ST r3, r254, 0a, 8h
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ST r8, r254, 0a, 8h
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ST r7, r254, 8a, 1h
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ST r9, r254, 24a, 8h
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ADDI64 r11, r6, 8d
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ADDI64 r3, r6, 8d
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BMC r1, r11, 8h
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BMC r7, r3, 8h
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LD r1, r6, 0a, 16h
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ADDI64 r4, r254, 8d
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ADDI64 r254, r254, 24d
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ST r4, r254, 40a, 8h
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LI64 r2, 0d
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ST r2, r254, 48a, 8h
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BMC r6, r1, 32h
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ADDI64 r254, r254, 56d
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JALA r0, r31, 0a
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JALA r0, r31, 0a
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code size: 568
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code size: 604
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ret: 100
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ret: 100
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status: Ok(())
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status: Ok(())
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