forked from AbleOS/ableos
ATA device detection
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148c66eae2
commit
012452dec1
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@ -35,6 +35,8 @@ pub struct PciDeviceInfo {
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pub bus: u8,
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pub device_id: DeviceID,
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pub full_class: PciFullClass,
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pub command: u16,
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pub status: u16,
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pub prog_if: u8,
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pub rev_id: u8,
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pub header_type: u8,
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@ -52,6 +54,10 @@ impl PciDeviceInfo {
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pub fn subclass(&self) -> PciClass {
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PciClass::from_u8((self.full_class.as_u16() & 0xFF) as u8)
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}
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pub unsafe fn config_read(&self, func: u8, offset: u8) -> u32 {
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pci_config_read(self.bus, self.device, func, offset)
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}
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}
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impl Display for PciDeviceInfo {
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fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error> {
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@ -63,6 +69,11 @@ impl Display for PciDeviceInfo {
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self.device, self.bus, vendor_name, device_id,
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)?;
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writeln!(f, "{}", self.full_class)?;
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writeln!(
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f,
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" Command: {:b} | Status: {:b}",
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self.command, self.status
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)?;
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writeln!(f, " Revision ID: {}", self.rev_id)?;
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writeln!(f, " Prog IF: 0b{:b}", self.prog_if)?;
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writeln!(f, " Header type: 0x{:X}", self.header_type)?;
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@ -118,7 +129,10 @@ fn check_device(bus: u8, device: u8) -> Option<PciDeviceInfo> {
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return None;
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}
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let reg1 = unsafe { pci_config_read(bus, device, 0, 0x4) };
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let reg2 = unsafe { pci_config_read(bus, device, 0, 0x8) };
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let command = (reg1 & 0x0000FFFF) as u16;
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let status = ((reg1 >> 16) & 0x0000FFFF) as u16;
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let rev_id = (reg2 & 0x000000FF) as u8;
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let prog_if = ((reg2 >> 8) & 0x000000FF) as u8;
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let class = ((reg2 >> 16) & 0x0000FFFF) as u16;
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@ -158,6 +172,8 @@ fn check_device(bus: u8, device: u8) -> Option<PciDeviceInfo> {
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},
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// vendor_id,
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full_class: pci_class,
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command,
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status,
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prog_if,
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rev_id,
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header_type,
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@ -13,8 +13,7 @@ use x86_64::VirtAddr;
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use crate::arch::memory::BootInfoFrameAllocator;
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use super::port::Port;
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use super::{check_device, PciDeviceInfo};
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use super::{check_device, port::Port};
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const PRDT_START: u64 = 0x_ffff_ffff_0000_0000;
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const BUFFER_START: u64 = 0x_ffff_ffff_0000_1000;
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@ -29,8 +28,32 @@ const BMIDTP_OFFSET: u16 = 4;
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/// Bus Master IDE Secondary Offset
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const BMI_SECONDARY: u16 = 8;
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/// Primary command block offset
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const PRIMARY_COMMAND: u16 = 0x01F0;
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/// Secondary command block offset
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const SECONDARY_COMMAND: u16 = 0x0170;
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/// Drive/Head register offset
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const DRIVE_HEAD_OFFSET: u16 = 6;
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/// Command/status register offset
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const COMMAND_STATUS_OFFSET: u16 = 7;
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/// Secondary control block offset
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const SECONDARY_CONTROL: u16 = 0x0374;
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/// Primary control block offset
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const PRIMARY_CONTROL: u16 = 0x03F4;
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/// Alternative status offset
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const ALT_STATUS_OFFSET: u16 = 2;
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/// ATA identification command
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const CMD_IDENTIFY: u8 = 0xEC;
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pub struct Piix {
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device_info: PciDeviceInfo,
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ide_devices: Vec<IdeDevice>,
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prdt_frame: Option<PhysFrame>,
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buffer_frames: Option<Vec<PhysFrame>>,
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bmiba: u16,
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@ -41,10 +64,55 @@ impl Piix {
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pub fn new(bus: u8, device: u8) -> Option<Self> {
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let device_info = check_device(bus, device)?;
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trace!("device_info: {device_info}");
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let idetim = unsafe { device_info.config_read(0, 0x40) };
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trace!("idetim: {idetim:b}");
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// FIXME: enable the right bits in idetim (and sidetim) to use fast timings
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let mut ide_devices = Vec::with_capacity(4);
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for ch in 0..2 {
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let channel = if ch == 0 {
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Channel::Primary
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} else {
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Channel::Secondary
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};
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'drive: for dr in 0..2 {
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let drive = if dr == 0 { Drive::Master } else { Drive::Slave };
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unsafe {
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select_drive(drive, channel);
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let status = ata_send_command(CMD_IDENTIFY, channel);
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if status == 0 {
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continue; // If status = 0, no device
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}
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loop {
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let status = {
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let addr = if channel.secondary() {
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SECONDARY_COMMAND
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} else {
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PRIMARY_COMMAND
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} + COMMAND_STATUS_OFFSET;
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Port::<u8>::new(addr).read()
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};
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if status & 1 == 1 {
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// if error (bit 0), device is not ATA
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// FIXME: ATAPI devices
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continue 'drive;
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}
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if !((status >> 7) & 1 == 1) && (status >> 3) & 1 == 1 {
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// BSY cleared, DRQ set, everything is right
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break;
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}
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}
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}
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}
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}
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let bmiba = device_info.bars[4] & 0xFFFFFFFC;
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Some(Self {
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device_info,
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ide_devices,
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prdt_frame: None,
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buffer_frames: None,
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bmiba: bmiba.try_into().ok()?,
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@ -130,49 +198,170 @@ impl Piix {
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}
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unsafe {
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self.stop(false);
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self.set_read(false);
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self.clear_status(false);
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// (*bmiba).bmidtpp = self.prdt_frame.unwrap().start_address().as_u64().try_into()?;
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self.load_prdt(Channel::Primary);
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self.stop(Channel::Primary);
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self.set_read(Channel::Primary);
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self.clear_status(Channel::Primary);
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select_drive(Drive::Master, Channel::Primary);
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}
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Ok(())
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}
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unsafe fn stop(&self, secondary: bool) {
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let addr = if secondary { BMI_SECONDARY } else { 0 } + self.bmiba + BMIC_OFFSET;
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let mut bmic = Port::<u8>::new(addr).read();
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unsafe fn load_prdt(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIDTP_OFFSET;
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Port::<u32>::new(addr).write(
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self.prdt_frame
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.unwrap()
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.start_address()
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.as_u64()
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.try_into()
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.unwrap(),
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);
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}
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unsafe fn stop(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIC_OFFSET;
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let port: Port<u8> = Port::new(addr);
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let mut bmic = port.read();
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// stop ongoing transfer
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bmic &= !1;
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// write the new bmic
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Port::<u8>::new(addr).write(bmic);
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port.write(bmic);
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}
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unsafe fn set_read(&self, secondary: bool) {
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let addr = if secondary { BMI_SECONDARY } else { 0 } + self.bmiba + BMIC_OFFSET;
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let mut bmic = Port::<u8>::new(addr).read();
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unsafe fn set_read(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIC_OFFSET;
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let port: Port<u8> = Port::new(addr);
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let mut bmic = port.read();
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// mark bit 3 as 0 (read)
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bmic &= !(1 << 3);
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// write the new bmic
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Port::<u8>::new(addr).write(bmic);
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port.write(bmic);
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}
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unsafe fn set_write(&self, secondary: bool) {
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let addr = if secondary { BMI_SECONDARY } else { 0 } + self.bmiba + BMIC_OFFSET;
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let mut bmic = Port::<u8>::new(addr).read();
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unsafe fn set_write(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIC_OFFSET;
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let port: Port<u8> = Port::new(addr);
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let mut bmic = port.read();
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// mark bit 3 as 1 (write)
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bmic |= 1 << 3;
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// write the new bmic
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Port::<u8>::new(addr).write(bmic);
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port.write(bmic);
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}
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unsafe fn clear_status(&self, secondary: bool) {
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let addr = if secondary { BMI_SECONDARY } else { 0 } + self.bmiba + BMIS_OFFSET;
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let mut bmis = Port::<u8>::new(addr).read();
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unsafe fn clear_status(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIS_OFFSET;
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let port: Port<u8> = Port::new(addr);
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let mut bmis = port.read();
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// write 1 to bits 1 (DMA error) and 2 (int status) which clears them
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bmis |= 1 << 1 | 1 << 2;
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// write the new bmis
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Port::<u8>::new(addr).write(bmis);
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port.write(bmis);
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}
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}
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unsafe fn select_drive(drive: Drive, channel: Channel) {
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let addr = if channel.secondary() {
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SECONDARY_COMMAND
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} else {
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PRIMARY_COMMAND
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} + DRIVE_HEAD_OFFSET;
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let port: Port<u8> = Port::new(addr);
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let mut drive_command = port.read();
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if drive.slave() {
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// mark bit 4
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drive_command |= 1 << 4;
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} else {
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// clear bit 4
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drive_command &= !(1 << 4);
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}
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// write the new drive/head register
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port.write(drive_command);
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ata_delay(channel);
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}
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/// Send ATA command and read status afterwards
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unsafe fn ata_send_command(command: u8, channel: Channel) -> u8 {
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let addr = if channel.secondary() {
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SECONDARY_COMMAND
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} else {
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PRIMARY_COMMAND
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} + COMMAND_STATUS_OFFSET;
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let port: Port<u8> = Port::new(addr);
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port.write(command);
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ata_delay(channel);
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port.read()
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}
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/// Read the alternate status register 14 times to create a ~420ns delay
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unsafe fn ata_delay(channel: Channel) {
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let addr = if channel.secondary() {
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SECONDARY_CONTROL
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} else {
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PRIMARY_CONTROL
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} + ALT_STATUS_OFFSET;
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let port: Port<u8> = Port::new(addr);
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for _ in 0..14 {
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port.read();
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}
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}
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struct IdeDevice {
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pub channel: Channel,
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pub drive: Drive,
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pub signature: u16,
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pub capabilities: u16,
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pub command_sets: u32,
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pub size: u64,
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}
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#[derive(Copy, Clone, Debug)]
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enum Channel {
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Primary,
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Secondary,
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}
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impl Channel {
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fn secondary(&self) -> bool {
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matches!(self, Self::Secondary)
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}
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}
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#[derive(Copy, Clone, Debug)]
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enum Drive {
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Master,
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Slave,
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}
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impl Drive {
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fn slave(&self) -> bool {
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matches!(self, Self::Slave)
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}
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}
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