forked from AbleOS/ableos
cpuid fixed
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3b9a3ab18a
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7fa6a45247
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@ -18,6 +18,7 @@
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//! }
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//! ```
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use core::arch::asm;
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use core::ops::Deref;
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use core::{fmt, slice, str};
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@ -39,28 +40,27 @@ pub enum RequestType {
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}
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pub fn cpuid(code: RequestType) -> (u32, u32, u32, u32) {
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let res1;
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let res2;
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let res3;
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let res4;
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let eax;
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let ebx;
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let ecx;
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let edx;
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unsafe {
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llvm_asm!("cpuid"
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: // output operands
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"={eax}"(res1),
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"={ebx}"(res2),
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"={ecx}"(res3),
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"={edx}"(res4)
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: // input operands
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"{eax}"(code as u32),
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"{ecx}"(0 as u32)
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: // clobbers
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: // options
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asm!(
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"movq %rbx, {0:r}",
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"cpuid",
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"xchgq %rbx, {0:r}",
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lateout(reg) ebx,
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inlateout("eax") code as u32 => eax,
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inlateout("ecx") 0 => ecx,
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lateout("edx") edx,
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options(nostack, preserves_flags, att_syntax),
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);
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}
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(res1, res2, res3, res4)
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(eax, ebx, ecx, edx)
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}
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/// The main entrypoint to the CPU information
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#[cfg(any(target_arch = "x86_64", target_arch = "x86"))]
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pub fn master() -> Option<Master> {
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@ -6,17 +6,14 @@
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#![no_std]
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#![feature(
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abi_x86_interrupt,
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// asm,
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asm_sym,
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alloc_error_handler,
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core_intrinsics,
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// global_asm,
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exclusive_range_pattern,
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lang_items,
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llvm_asm,
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naked_functions
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naked_functions,
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slice_pattern,
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)]
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#![feature(exclusive_range_pattern)]
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#![feature(slice_pattern)]
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/// Contains architecture specific code for aarch64.
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#[cfg(target_arch = "aarch64")]
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