I have inflicted self-psychic damage
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# ATA, NVMe, SATA, Floppy Disks and Optical Drives; Storing my own personal hell
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A storage media would reasonably have two features
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`Store` or `write`
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`Load` or `read`
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depending on your favored terminology.
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Alright let us learn about ATA first because it is alphabetically first!
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## ATA
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IDE is used mostly interchangably with ATA but IDE is the physical transmission not the protocol name. Subtle but important difference here down at the bottom.
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ATA seems to have multiple ways of `Store`ing and `Load`ing data.
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Oh joy!
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## SATA and PATA
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SATA is a new standard for data transmission it stands for Serial AT Attachment
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All old ATA devices are retroactively named PATA and it stands for (Parallel) ATA
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The vast majority of SATA devices also support AHCI. AHCI was developed by intel to help handle SATA devices
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To determine if an ATA device is a SATA device you send a standard IDENTIFY command (as specified by P/ATA) to the drive (0xEC) it responds with an ERR and a status pair...
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Ok thats insane
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but sure...
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It also seems there are 2-3 different standards for `Store`ing and `Load`ing data in SATA mode.
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Lets assume for my sake and yours, dear reader, that the API is identical for these modes.
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Let us define a simple API to interact with these devices.
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```rust
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pub struct DiskIO {
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@documentation("The pointer is a pointer into the DISK addressing")
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read: function(pointer: u64, length: u64) -> Vector<u8>;
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@validator(data: data.len() > 0)
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@documentation("The pointer is a pointer into the DISK addressing, the Vector must be u8s and must atleast have one u8")
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write: function(pointer: u64, data: Vector<u8>) -> None;
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}
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```
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Lets move on to the older more legacy saner(?) ATA PIO Mode
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### ATA PIO Mode
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ATA is a hack on an older specification named ST506 (Side note: I WILL NOT be addressing this)
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The only difference anyways is the controller being moved on board and one less cable.
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When accessing a disk the cpu shorts a pin and sets which disk of the master/slave pair is being accessed
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Once a command has been submitted you may poll the drive to check the status of the command. You ***MUST*** poll 15 times ***OR*** delay by 400 nanoseconds after a command is submitted for it to complete. If you send a command to a drive before 400ns are up you can destroy the controller on badly made drives or just mess up the previous command on better behaving more lieniant devices.
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On some drives it is a requirement to flush the hardware cache after each write if this is not done you can create bad sectors until the drive is powercycled.
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This is insane and should not be the case...
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A cache that is flushed after every write is not a cache that is worth using...
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But! None-the-less we have a new concept called a hardware cache, and it has to sometimes be flushed by the driver.
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Another API
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```rust
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pub struct DiskIO {
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@documentation("Set this to false any time we write")
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flushed_hw_cache: bool,
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@documentation("The pointer is a pointer into the DISK addressing")
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read: function(pointer: u64, length: u64) -> Vector<u8>;
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@validator(data: data.len() > 0)
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@documentation("The pointer is a pointer into the DISK addressing, the Vector must be u8s and must atleast have one u8")
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write: function(pointer: u64, data: Vector<u8>) -> None;
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@validator(flushed: false)
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@documentation("Only to be called if we have not flushed yet")
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flush_hw_cache: function(None) -> None;
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}
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```
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Well that is less than ideal but atleast it gives us more control! EXCEPT on drives where we ***MUST*** flush after every write.
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We will not be learning about addressing modes because I gave myself a headache looking at them.
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Next!
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### ATAPI
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ATAPI; Adding a lil SCSI to your ATA.
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Typically CD-ROM, CD-RW, DVD, or tape drive attatched to the ATA Bus use ATAPI.
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This is included in drives that are ATA Version 6 or greater. We will not be adding an API to get the version as any file system interacting with the disk driver would presumably not need to know about the disk.
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More magical methods of identification..
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A new ATA Packet type.
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And finally getting Disc Contents!
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First we must ensure that the disk is readable.
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This will be handled by the disk driver and will not be reported by the API as the device cannot be used by a filesystem driver if it is not readable.
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secondly we check if the disk is writable.
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This will be included in the API because CD-ROM media can be read only for example
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Previously we assumed that disks had infinite storage because in the modern day disks are infinitly big compared to a CD-ROM.
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We will add in the api for getting size now.
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We will also add a free space for convenience
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```rust
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pub struct DiskIO {
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@documentation("Set this to false any time we write")
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flushed_hw_cache: bool,
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@validator(size > 0)
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@documentation("Size is in bytes and must be greater than zero")
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size: u64,
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@validator(size >= free_space)
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free_space: u64,
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@documentation("The pointer is a pointer into the DISK addressing")
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read: function(pointer: u64, length: u64) -> Vector<u8>;
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@validator(data: data.len() > 0)
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@documentation("The pointer is a pointer into the DISK addressing, the Vector must be u8s and must atleast have one u8")
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write: function(pointer: u64, data: Vector<u8>) -> None;
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@validator(flushed: false)
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@documentation("Only to be called if we have not flushed yet")
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flush_hw_cache: function(None) -> None;
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@documentation("Returns True if the disk is writeable.")
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is_writeable: function(None) -> Bool;
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}
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```
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#### ATA/ATAPI using DMA
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There is no noticable API change here but therre is a noticable speed up over previous modes.
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### ATA in x86 RealMode (BIOS)
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This adds nothing interesting and is only useful if you rely on BIOS calls.
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We do not.
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-----
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## Intermission One Act One
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Well that was hell! Luckily thats over with and we move onto the simple things.
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NVMe's!
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## NVMes
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NVMes use the PCI bus to communicate.
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Lets just check the spec real quick...
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oh 458 pages
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...dear me...
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and thats only for the Base specification. What ever that means
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Lets not look at that actually and glance over at the OSDev wiki, my favorite misinformed shit-show forum wiki combo.
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NVMes :(
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NVMes have a few registers to communicate back and forth with the driver.
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11 registers
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of which 2 are static
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so 9 registers
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with these registers you create an admin queue to create submission buffers to feed commands to the NVMe drive
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The NVMe controller may process commands in any order it likes.
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oh dear
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so you must figure out which commands cannot yet be submitted do to dependence on data from other commands yourself and have a second submission buffer queue....
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What the FUCK!
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Please give me back any of the ATA modes.
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## Floppy Disks
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3 modes because of different chipsets
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most commands are silent, ala no status updates when complete.
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Great! more active polling, of the data this time not the disk
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floppy disk controllers are configured via 9 registers that are IO memory mapped
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depending on if you read or write to them you are accessing different registers
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FUCK THIS PLEASE BE NORMAL FOR ONE MINUTE
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In real hardware floppies are incredibly unrealiable
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so you are recommended to (`write` then `read` and compare) twice...
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## Intermission One Act Two
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```rust
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DiskIO.write(0, Vector("I am living in hell"));
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// Oh and don't forget to flush the fucking cache
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DiskIO.flush();
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```
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## Optical Drives
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Ahh back to the good old SCSI of the ATAPI minus the ATAPI packets
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alright.
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So implement optical drives first
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### Random R+W operations on DVD and Bluray
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Its just fucking magic ok.
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## SD Cards
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SD Cards are predictably just as scuffed
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### Vendor Enhancements
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#### Integrated Wi-Fi
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No this cannot be real.
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We have to support Wi-Fi over DiskIO????????????
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No We WILL not. Sorry the one person who needs this
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#### Pre-loaded Content
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What the actual fuck? Pre-loaded reserved content that is write protected...
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oh and lets not forget DRM
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#### Integrated USB Connector
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This is just a built in sdcard reader usb combo
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The sanest extension yet
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#### Different colors
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Similar to USB colors to identify card types
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I actually like this and suggest others do this as well
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#### Integrated display
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Ok well thats it fools.
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