From b5906f42d5011a97a0be9575ee048a62ebe5ffaf Mon Sep 17 00:00:00 2001 From: Ryan Kennedy Date: Sun, 22 Mar 2020 19:02:01 -0500 Subject: [PATCH] Bunch of docs --- src/registers/attribute_controller.rs | 37 +++++++++++++++------------ src/registers/color_palette.rs | 5 ++++ src/registers/crtc_controller.rs | 5 ++++ src/registers/general.rs | 3 +++ src/registers/graphics_controller.rs | 5 ++++ src/registers/sequencer.rs | 3 +++ src/vga.rs | 6 +++++ 7 files changed, 48 insertions(+), 16 deletions(-) diff --git a/src/registers/attribute_controller.rs b/src/registers/attribute_controller.rs index 7fdd0b3..9a1e214 100644 --- a/src/registers/attribute_controller.rs +++ b/src/registers/attribute_controller.rs @@ -58,6 +58,7 @@ impl From for u8 { } } +/// Represents the attribute controller registers on vga hardware. #[derive(Debug)] pub struct AttributeControllerRegisters { arx_index: Port, @@ -76,12 +77,16 @@ impl AttributeControllerRegisters { } } + /// Reads the current value of the attribute controller, as specified + /// by `emulation_mode` and `index`. pub fn read(&mut self, emulation_mode: EmulationMode, index: AttributeControllerIndex) -> u8 { self.toggle_index(emulation_mode); self.set_index(index); unsafe { self.arx_data.read() } } + /// Writes the `value` to the attribute controller, as specified + /// `emulation_mode` and `index`. pub fn write( &mut self, emulation_mode: EmulationMode, @@ -95,22 +100,6 @@ impl AttributeControllerRegisters { } } - fn set_index(&mut self, index: AttributeControllerIndex) { - unsafe { - self.arx_index.write(u8::from(index)); - } - } - - fn toggle_index(&mut self, emulation_mode: EmulationMode) { - let st01_read = match emulation_mode { - EmulationMode::Cga => &mut self.st01_read_cga, - EmulationMode::Mda => &mut self.st01_read_mda, - }; - unsafe { - st01_read.read(); - } - } - /// Video Enable. Note that In the VGA standard, this is called the "Palette Address Source" bit. /// Clearing this bit will cause the VGA display data to become all 00 index values. For the default /// palette, this will cause a black screen. The video timing signals continue. Another control bit will @@ -142,4 +131,20 @@ impl AttributeControllerRegisters { self.arx_index.write(arx_index_value | 0x20); } } + + fn set_index(&mut self, index: AttributeControllerIndex) { + unsafe { + self.arx_index.write(u8::from(index)); + } + } + + fn toggle_index(&mut self, emulation_mode: EmulationMode) { + let st01_read = match emulation_mode { + EmulationMode::Cga => &mut self.st01_read_cga, + EmulationMode::Mda => &mut self.st01_read_mda, + }; + unsafe { + st01_read.read(); + } + } } diff --git a/src/registers/color_palette.rs b/src/registers/color_palette.rs index 83a595d..e148e03 100644 --- a/src/registers/color_palette.rs +++ b/src/registers/color_palette.rs @@ -4,6 +4,7 @@ use super::{ }; use x86_64::instructions::port::Port; +/// Represents the color palette registers on vga hardware. #[derive(Debug)] pub struct ColorPaletteRegisters { data_port: Port, @@ -20,6 +21,8 @@ impl ColorPaletteRegisters { } } + /// Loads a 256 color palette, as specified by `palette`, with every 3 + /// bytes representing a color. pub fn load_palette(&mut self, palette: &[u8; PALETTE_SIZE]) { unsafe { self.index_write_port.write(0); @@ -31,6 +34,8 @@ impl ColorPaletteRegisters { } } + /// Reads the current 256 color palette into `palette`, with every 3 + /// bytes representing a color. pub fn read_palette(&mut self, palette: &mut [u8; PALETTE_SIZE]) { unsafe { self.index_read_port.write(0); diff --git a/src/registers/crtc_controller.rs b/src/registers/crtc_controller.rs index d9df5d4..b8bb34a 100644 --- a/src/registers/crtc_controller.rs +++ b/src/registers/crtc_controller.rs @@ -70,6 +70,7 @@ impl From for u8 { } } +/// Represents the crtc controller registers on vga hardware. #[derive(Debug)] pub struct CrtcControllerRegisters { crx_index_cga: Port, @@ -88,11 +89,15 @@ impl CrtcControllerRegisters { } } + /// Reads the current value from the crtc controller, as specified + /// by `emulation_mode` and `index`. pub fn read(&mut self, emulation_mode: EmulationMode, index: CrtcControllerIndex) -> u8 { self.set_index(emulation_mode, index); unsafe { self.get_data_port(emulation_mode).read() } } + /// Writes the `value` to the crtc_controller, as specified + /// by `emulation_mode` and `index`. pub fn write(&mut self, emulation_mode: EmulationMode, index: CrtcControllerIndex, value: u8) { self.set_index(emulation_mode, index); unsafe { diff --git a/src/registers/general.rs b/src/registers/general.rs index 6f4ddca..e6392c5 100644 --- a/src/registers/general.rs +++ b/src/registers/general.rs @@ -4,6 +4,7 @@ use super::{ }; use x86_64::instructions::port::{PortReadOnly, PortWriteOnly}; +/// Represents the general registers on vga hardware. #[derive(Debug)] pub struct GeneralRegisters { st00_read: PortReadOnly, @@ -30,10 +31,12 @@ impl GeneralRegisters { } } + /// Reads the current value from the miscellaneous output register. pub fn read_msr(&mut self) -> u8 { unsafe { self.msr_read.read() } } + /// Writes the `value` to the miscellaneous output register. pub fn write_msr(&mut self, value: u8) { unsafe { self.msr_write.write(value); diff --git a/src/registers/graphics_controller.rs b/src/registers/graphics_controller.rs index 1aca93b..716cd02 100644 --- a/src/registers/graphics_controller.rs +++ b/src/registers/graphics_controller.rs @@ -37,6 +37,7 @@ impl From for u8 { } } +/// Represents the graphics controller registers on vga hardware. #[derive(Debug)] pub struct GraphicsControllerRegisters { grx_index: Port, @@ -51,11 +52,15 @@ impl GraphicsControllerRegisters { } } + /// Reads the current value from the graphics controller, as specified + /// by `index`. pub fn read(&mut self, index: GraphicsControllerIndex) -> u8 { self.set_index(index); unsafe { self.grx_data.read() } } + /// Writes the `value` to the graphics controller, as specified + /// by `index. pub fn write(&mut self, index: GraphicsControllerIndex, value: u8) { self.set_index(index); unsafe { diff --git a/src/registers/sequencer.rs b/src/registers/sequencer.rs index 097cdeb..1612dc9 100644 --- a/src/registers/sequencer.rs +++ b/src/registers/sequencer.rs @@ -65,6 +65,7 @@ impl From for u8 { } } +/// Represents the sequencer registers on vga hardware. #[derive(Debug)] pub struct SequencerRegisters { srx_index: Port, @@ -79,11 +80,13 @@ impl SequencerRegisters { } } + /// Reads the current value from the sequencer, as specified by `index`. pub fn read(&mut self, index: SequencerIndex) -> u8 { self.set_index(index); unsafe { self.srx_data.read() } } + /// Writes the `value` to the sequencer, as specified by `index`. pub fn write(&mut self, index: SequencerIndex, value: u8) { self.set_index(index); unsafe { diff --git a/src/vga.rs b/src/vga.rs index 6f8955c..81ecdc2 100644 --- a/src/vga.rs +++ b/src/vga.rs @@ -102,11 +102,17 @@ pub enum VideoMode { /// Represents a vga graphics card with it's common registers, /// as well as the most recent video mode. pub struct Vga { + /// Represents the general registers on vga hardware. pub general_registers: GeneralRegisters, + /// Represents the sequencer registers on vga hardware. pub sequencer_registers: SequencerRegisters, + /// Represents the graphics controller registers on vga hardware. pub graphics_controller_registers: GraphicsControllerRegisters, + /// Represents the attribute controller registers on vga hardware. pub attribute_controller_registers: AttributeControllerRegisters, + /// Represents the crtc controller registers on vga hardware. pub crtc_controller_registers: CrtcControllerRegisters, + /// Represents the color palette registers on vga hardware. pub color_palette_registers: ColorPaletteRegisters, most_recent_video_mode: Option, }