344 lines
12 KiB
Rust
344 lines
12 KiB
Rust
//! Provides access to the vga graphics card.
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use super::{
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vga_configurations::{
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VgaConfiguration, MODE_40X25_CONFIGURATION, MODE_40X50_CONFIGURATION,
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MODE_640X480X16_CONFIGURATION, MODE_80X25_CONFIGURATION,
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},
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vga_fonts::{VgaFont, TEXT_8X16_FONT, TEXT_8X8_FONT},
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vga_registers::{
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AttributeControllerRegisters, CrtcControllerIndex, CrtcControllerRegisters, EmulationMode,
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GeneralRegisters, GraphicsControllerIndex, GraphicsControllerRegisters, SequencerIndex,
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SequencerRegisters,
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},
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};
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use conquer_once::spin::Lazy;
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use spinning_top::Spinlock;
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/// Provides mutable access to the vga graphics card.
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pub static VGA: Lazy<Spinlock<Vga>> = Lazy::new(|| Spinlock::new(Vga::new()));
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/// Represents the starting address of the frame buffer for
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/// various video modes.
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#[derive(Debug, Copy, Clone)]
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#[repr(u32)]
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pub enum FrameBuffer {
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/// The starting address for graphics modes.
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GraphicsMode = 0xa0000,
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/// The starting address for color text modes.
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CgaMode = 0xb8000,
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/// The starting address for monochrome text modes.
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MdaMode = 0xb0000,
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}
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impl From<u8> for FrameBuffer {
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fn from(value: u8) -> FrameBuffer {
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match value {
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0x1 => FrameBuffer::GraphicsMode,
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0x2 => FrameBuffer::MdaMode,
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0x3 => FrameBuffer::CgaMode,
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_ => panic!("{:X} is not a valid FrameBuffer value", value),
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}
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}
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}
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impl From<FrameBuffer> for u32 {
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fn from(value: FrameBuffer) -> u32 {
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value as u32
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}
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}
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/// Represents a plane for reading and writing vga data.
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#[allow(dead_code)]
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#[derive(Debug, Copy, Clone)]
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#[repr(u8)]
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pub enum Plane {
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/// Represents `Plane 0 (0x0)`.
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Plane0 = 0x0,
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/// Represents `Plane 1 (0x1)`.
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Plane1 = 0x1,
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/// Represents `Plane 2 (0x2)`.
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Plane2 = 0x2,
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/// Represents `Plane 3 (0x3)`.
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Plane3 = 0x3,
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}
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impl From<Plane> for u8 {
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fn from(value: Plane) -> u8 {
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value as u8
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}
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}
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/// Represents a specified vga video mode.
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#[derive(Debug, Clone, Copy)]
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pub enum VideoMode {
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/// Represents text mode 40x25.
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Mode40x25,
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/// Represents text mode 40x50.
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Mode40x50,
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/// Represents text mode 80x25.
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Mode80x25,
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/// Represents graphics mode 640x480x16.
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Mode640x480x16,
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}
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/// Represents a vga graphics card with it's common registers,
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/// as well as the most recent video mode.
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pub struct Vga {
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general_registers: GeneralRegisters,
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sequencer_registers: SequencerRegisters,
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graphics_controller_registers: GraphicsControllerRegisters,
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attribute_controller_registers: AttributeControllerRegisters,
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crtc_controller_registers: CrtcControllerRegisters,
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most_recent_video_mode: Option<VideoMode>,
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}
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impl Vga {
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fn new() -> Vga {
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Vga {
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general_registers: GeneralRegisters::new(),
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sequencer_registers: SequencerRegisters::new(),
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graphics_controller_registers: GraphicsControllerRegisters::new(),
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attribute_controller_registers: AttributeControllerRegisters::new(),
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crtc_controller_registers: CrtcControllerRegisters::new(),
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most_recent_video_mode: None,
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}
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}
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/// Sets the vga graphics card to the given `VideoMode`.
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pub fn set_video_mode(&mut self, video_mode: VideoMode) {
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match video_mode {
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VideoMode::Mode40x25 => self.set_video_mode_40x25(),
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VideoMode::Mode40x50 => self.set_video_mode_40x50(),
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VideoMode::Mode80x25 => self.set_video_mode_80x25(),
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VideoMode::Mode640x480x16 => self.set_video_mode_640x480x16(),
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}
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}
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/// Gets the `FrameBuffer` address as specified by the
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/// `Miscellaneous Output Register`.
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pub fn get_frame_buffer(&mut self) -> FrameBuffer {
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let miscellaneous_graphics = self
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.graphics_controller_registers
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.read(GraphicsControllerIndex::Miscellaneous);
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let memory_map_mode = (miscellaneous_graphics >> 0x2) & 0x3;
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FrameBuffer::from(memory_map_mode)
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}
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/// Returns the most recent video mode, or `None` if no
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/// video mode has been set yet.
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pub fn get_most_recent_video_mode(&self) -> Option<VideoMode> {
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self.most_recent_video_mode
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}
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/// `I/O Address Select` Bit 0 `(value & 0x1)` of MSR selects 3Bxh or 3Dxh as the I/O address for the CRT Controller
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/// registers, the Feature Control Register (FCR), and Input Status Register 1 (ST01). Presently
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/// ignored (whole range is claimed), but will "ignore" 3Bx for color configuration or 3Dx for
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/// monochrome.
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/// Note that it is typical in AGP chipsets to shadow this bit and properly steer I/O cycles to the
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/// proper bus for operation where a MDA exists on another bus such as ISA.
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///
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/// 0 = Select 3Bxh I/O address `(EmulationMode::Mda)`
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///
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/// 1 = Select 3Dxh I/O address `(EmulationMode:Cga)`
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fn get_emulation_mode(&mut self) -> EmulationMode {
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EmulationMode::from(self.general_registers.read_msr() & 0x1)
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}
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fn load_font(&mut self, vga_font: &VgaFont) {
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// Save registers
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let (
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plane_mask,
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sequencer_memory_mode,
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read_plane_select,
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graphics_mode,
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miscellaneous_graphics,
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) = self.save_font_registers();
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// Switch to flat addressing
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self.sequencer_registers
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.write(SequencerIndex::MemoryMode, sequencer_memory_mode | 0x04);
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// Disable Even/Odd addressing
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self.graphics_controller_registers
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.write(GraphicsControllerIndex::GraphicsMode, graphics_mode & !0x10);
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self.graphics_controller_registers.write(
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GraphicsControllerIndex::Miscellaneous,
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miscellaneous_graphics & !0x02,
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);
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// Write font to plane
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self.set_plane(Plane::Plane2);
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let frame_buffer = u32::from(self.get_frame_buffer()) as *mut u8;
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for character in 0..vga_font.characters {
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for row in 0..vga_font.character_height {
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let offset = (character * 32) + row;
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let font_offset = (character * vga_font.character_height) + row;
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unsafe {
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frame_buffer
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.offset(offset as isize)
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.write_volatile(vga_font.font_data[font_offset as usize]);
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}
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}
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}
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self.restore_font_registers(
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plane_mask,
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sequencer_memory_mode,
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read_plane_select,
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graphics_mode,
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miscellaneous_graphics,
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);
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}
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fn restore_font_registers(
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&mut self,
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plane_mask: u8,
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sequencer_memory_mode: u8,
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read_plane_select: u8,
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graphics_mode: u8,
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miscellaneous_graphics: u8,
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) {
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self.sequencer_registers
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.write(SequencerIndex::PlaneMask, plane_mask);
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self.sequencer_registers
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.write(SequencerIndex::MemoryMode, sequencer_memory_mode);
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self.graphics_controller_registers
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.write(GraphicsControllerIndex::ReadPlaneSelect, read_plane_select);
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self.graphics_controller_registers
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.write(GraphicsControllerIndex::GraphicsMode, graphics_mode);
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self.graphics_controller_registers.write(
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GraphicsControllerIndex::Miscellaneous,
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miscellaneous_graphics,
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);
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}
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fn save_font_registers(&mut self) -> (u8, u8, u8, u8, u8) {
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(
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self.sequencer_registers.read(SequencerIndex::PlaneMask),
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self.sequencer_registers.read(SequencerIndex::MemoryMode),
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self.graphics_controller_registers
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.read(GraphicsControllerIndex::ReadPlaneSelect),
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self.graphics_controller_registers
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.read(GraphicsControllerIndex::GraphicsMode),
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self.graphics_controller_registers
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.read(GraphicsControllerIndex::Miscellaneous),
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)
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}
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/// Turns on the given `Plane` in the vga graphics card.
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pub fn set_plane(&mut self, plane: Plane) {
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let mut plane = u8::from(plane);
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plane &= 0x3;
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self.graphics_controller_registers
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.write(GraphicsControllerIndex::ReadPlaneSelect, plane);
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self.sequencer_registers
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.write(SequencerIndex::PlaneMask, 0x1 << plane);
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}
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fn set_registers(&mut self, configuration: &VgaConfiguration) {
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let emulation_mode = self.get_emulation_mode();
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// Set miscellaneous output
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self.general_registers
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.write_msr(configuration.miscellaneous_output);
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// Set the sequencer registers.
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for (index, value) in configuration.sequencer_registers {
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self.sequencer_registers.write(*index, *value);
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}
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// Unlock the crtc registers.
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self.unlock_crtc_registers(emulation_mode);
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// Set the crtc registers.
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for (index, value) in configuration.crtc_controller_registers {
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self.crtc_controller_registers
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.write(emulation_mode, *index, *value);
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}
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// Set the grx registers.
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for (index, value) in configuration.graphics_controller_registers {
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self.graphics_controller_registers.write(*index, *value);
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}
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// Blank the screen so the palette registers are unlocked.
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self.attribute_controller_registers
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.blank_screen(emulation_mode);
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// Set the arx registers.
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for (index, value) in configuration.attribute_controller_registers {
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self.attribute_controller_registers
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.write(emulation_mode, *index, *value);
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}
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// Unblank the screen so the palette registers are locked.
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self.attribute_controller_registers
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.unblank_screen(emulation_mode);
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}
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/// Sets the video card to Mode 40x25.
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fn set_video_mode_40x25(&mut self) {
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self.set_registers(&MODE_40X25_CONFIGURATION);
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self.load_font(&TEXT_8X16_FONT);
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self.most_recent_video_mode = Some(VideoMode::Mode40x25);
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}
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/// Sets the video card to Mode 40x50.
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fn set_video_mode_40x50(&mut self) {
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self.set_registers(&MODE_40X50_CONFIGURATION);
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self.load_font(&TEXT_8X8_FONT);
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self.most_recent_video_mode = Some(VideoMode::Mode40x50);
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}
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/// Sets the video card to Mode 80x25.
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fn set_video_mode_80x25(&mut self) {
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self.set_registers(&MODE_80X25_CONFIGURATION);
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self.load_font(&TEXT_8X16_FONT);
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self.most_recent_video_mode = Some(VideoMode::Mode80x25);
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}
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/// Sets the video card to Mode 640x480x16.
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fn set_video_mode_640x480x16(&mut self) {
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self.set_registers(&MODE_640X480X16_CONFIGURATION);
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self.most_recent_video_mode = Some(VideoMode::Mode640x480x16);
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}
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/// Unlocks the CRTC registers by setting bit 7 to 0 `(value & 0x7F)`.
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///
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/// `Protect Registers [0:7]`: Note that the ability to write to Bit 4 of the Overflow Register (CR07)
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/// is not affected by this bit (i.e., bit 4 of the Overflow Register is always writeable).
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///
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/// 0 = Enable writes to registers `CR[00:07]`
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///
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/// 1 = Disable writes to registers `CR[00:07]`
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fn unlock_crtc_registers(&mut self, emulation_mode: EmulationMode) {
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// Setting bit 7 to 1 used to be required for `VGA`, but says it's
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// ignored in modern hardware. Setting it to 1 just to be safe for older
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// hardware. More information can be found here
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// https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-display.pdf
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// under `CR03 - Horizontal Blanking End Register`.
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let horizontal_blanking_end = self
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.crtc_controller_registers
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.read(emulation_mode, CrtcControllerIndex::HorizontalBlankingEnd);
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self.crtc_controller_registers.write(
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emulation_mode,
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CrtcControllerIndex::HorizontalBlankingEnd,
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horizontal_blanking_end | 0x80,
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);
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let vertical_sync_end = self
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.crtc_controller_registers
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.read(emulation_mode, CrtcControllerIndex::VerticalSyncEnd);
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self.crtc_controller_registers.write(
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emulation_mode,
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CrtcControllerIndex::VerticalSyncEnd,
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vertical_sync_end & 0x7F,
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);
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}
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}
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