386 lines
11 KiB
Rust
386 lines
11 KiB
Rust
use x86_64::instructions::port::{Port, PortReadOnly, PortWriteOnly};
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const ST00_READ_ADDRESS: u16 = 0x3C2;
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const ST01_READ_CGA_ADDRESS: u16 = 0x3DA;
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const ST01_READ_MDA_ADDRESS: u16 = 0x3BA;
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const FCR_READ_ADDRESS: u16 = 0x3CA;
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const FCR_CGA_WRITE_ADDRESS: u16 = 0x3DA;
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const FCR_MDA_WRITE_ADDRESS: u16 = 0x3BA;
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const MSR_READ_ADDRESS: u16 = 0x3CC;
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const MSR_WRITE_ADDRESS: u16 = 0x3C2;
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const SRX_INDEX_ADDRESS: u16 = 0x3C4;
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const SRX_DATA_ADDRESS: u16 = 0x3C5;
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const GRX_INDEX_ADDRESS: u16 = 0x3CE;
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const GRX_DATA_ADDRESS: u16 = 0x3CF;
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const ARX_INDEX_ADDRESS: u16 = 0x3C0;
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const ARX_DATA_ADDRESS: u16 = 0x3C1;
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const CRX_INDEX_CGA_ADDRESS: u16 = 0x3D4;
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const CRX_INDEX_MDA_ADDRESS: u16 = 0x3B4;
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const CRX_DATA_CGA_ADDRESS: u16 = 0x3D5;
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const CRX_DATA_MDA_ADDRESS: u16 = 0x3B5;
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#[derive(Debug, Copy, Clone)]
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#[repr(u8)]
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pub enum EmulationMode {
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Mda = 0x0,
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Cga = 0x1,
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}
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impl From<u8> for EmulationMode {
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fn from(value: u8) -> EmulationMode {
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match value {
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0x0 => EmulationMode::Mda,
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0x1 => EmulationMode::Cga,
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_ => panic!("{} is an invalid emulation mode", value),
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}
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}
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}
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#[derive(Debug, Clone, Copy)]
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#[repr(u8)]
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pub enum SequencerIndex {
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SequencerReset = 0x0,
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ClockingMode = 0x1,
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PlaneMask = 0x2,
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CharacterFont = 0x3,
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MemoryMode = 0x4,
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CounterReset = 0x7,
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}
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impl From<SequencerIndex> for u8 {
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fn from(value: SequencerIndex) -> u8 {
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value as u8
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}
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}
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#[derive(Debug, Copy, Clone)]
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#[repr(u8)]
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pub enum GraphicsControllerIndex {
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SetReset = 0x0,
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EnableSetReset = 0x1,
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ColorCompare = 0x2,
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DataRotate = 0x3,
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ReadPlaneSelect = 0x4,
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GraphicsMode = 0x5,
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Miscellaneous = 0x6,
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ColorDontCare = 0x7,
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BitMask = 0x8,
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AddressMapping = 0x10,
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PageSelector = 0x11,
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SoftwareFlags = 0x18,
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}
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impl From<GraphicsControllerIndex> for u8 {
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fn from(value: GraphicsControllerIndex) -> u8 {
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value as u8
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}
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}
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#[derive(Debug, Copy, Clone)]
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#[repr(u8)]
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pub enum AttributeControllerIndex {
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PaletteRegister0 = 0x00,
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PaletteRegister1 = 0x01,
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PaletteRegister2 = 0x02,
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PaletteRegister3 = 0x03,
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PaletteRegister4 = 0x04,
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PaletteRegister5 = 0x05,
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PaletteRegister6 = 0x06,
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PaletteRegister7 = 0x07,
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PaletteRegister8 = 0x08,
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PaletteRegister9 = 0x09,
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PaletteRegisterA = 0x0A,
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PaletteRegisterB = 0x0B,
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PaletteRegisterC = 0x0C,
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PaletteRegisterD = 0x0D,
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PaletteRegisterE = 0x0E,
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PaletteRegisterF = 0x0F,
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ModeControl = 0x10,
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OverscanColor = 0x11,
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MemoryPlaneEnable = 0x12,
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HorizontalPixelPanning = 0x13,
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ColorSelect = 0x14,
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}
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impl From<AttributeControllerIndex> for u8 {
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fn from(value: AttributeControllerIndex) -> u8 {
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value as u8
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}
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}
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#[derive(Debug, Copy, Clone)]
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#[repr(u8)]
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pub enum CrtcControllerIndex {
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HorizontalTotal = 0x00,
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HorizontalDisplayEnableEnd = 0x01,
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HorizontalBlankingStart = 0x02,
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HorizontalBlankingEnd = 0x03,
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HorizontalSyncStart = 0x04,
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HorizontalSyncEnd = 0x05,
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VeritcalTotal = 0x06,
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Overflow = 0x07,
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PresetRowScan = 0x08,
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MaximumScanLine = 0x09,
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TextCursorStart = 0x0A,
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TextCursorEnd = 0x0B,
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StartAddressHigh = 0x0C,
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StartAddressLow = 0x0D,
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TextCursorLocationHigh = 0x0E,
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TextCursorLocationLow = 0x0F,
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VerticalSyncStart = 0x10,
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VerticalSyncEnd = 0x11,
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VerticalDisplayEnableEnd = 0x12,
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Offset = 0x13,
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UnderlineLocationRegister = 0x14,
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VerticalBlankingStart = 0x15,
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VerticalBlankingEnd = 0x16,
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ModeControl = 0x17,
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LineCompare = 0x18,
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MemoryReadLatchData = 0x22,
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ToggleStateOfAttributeController = 0x24,
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}
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impl From<CrtcControllerIndex> for u8 {
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fn from(value: CrtcControllerIndex) -> u8 {
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value as u8
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}
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}
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#[derive(Debug)]
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pub struct GeneralRegisters {
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st00_read: PortReadOnly<u8>,
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st01_read_cga: PortReadOnly<u8>,
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st01_read_mda: PortReadOnly<u8>,
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fcr_read: PortReadOnly<u8>,
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fcr_write_cga: PortWriteOnly<u8>,
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fcr_write_mda: PortWriteOnly<u8>,
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msr_read: PortReadOnly<u8>,
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msr_write: PortWriteOnly<u8>,
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}
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impl GeneralRegisters {
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pub fn new() -> GeneralRegisters {
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GeneralRegisters {
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st00_read: PortReadOnly::new(ST00_READ_ADDRESS),
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st01_read_cga: PortReadOnly::new(ST01_READ_CGA_ADDRESS),
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st01_read_mda: PortReadOnly::new(ST01_READ_MDA_ADDRESS),
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fcr_read: PortReadOnly::new(FCR_READ_ADDRESS),
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fcr_write_cga: PortWriteOnly::new(FCR_CGA_WRITE_ADDRESS),
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fcr_write_mda: PortWriteOnly::new(FCR_MDA_WRITE_ADDRESS),
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msr_read: PortReadOnly::new(MSR_READ_ADDRESS),
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msr_write: PortWriteOnly::new(MSR_WRITE_ADDRESS),
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}
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}
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pub fn read_msr(&mut self) -> u8 {
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unsafe { self.msr_read.read() }
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}
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pub fn write_msr(&mut self, value: u8) {
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unsafe {
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self.msr_write.write(value);
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}
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}
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}
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#[derive(Debug)]
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pub struct SequencerRegisters {
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srx_index: Port<u8>,
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srx_data: Port<u8>,
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}
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impl SequencerRegisters {
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pub fn new() -> SequencerRegisters {
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SequencerRegisters {
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srx_index: Port::new(SRX_INDEX_ADDRESS),
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srx_data: Port::new(SRX_DATA_ADDRESS),
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}
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}
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pub fn read(&mut self, index: SequencerIndex) -> u8 {
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self.set_index(index);
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unsafe { self.srx_data.read() }
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}
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pub fn write(&mut self, index: SequencerIndex, value: u8) {
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self.set_index(index);
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unsafe {
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self.srx_data.write(value);
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}
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}
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fn set_index(&mut self, index: SequencerIndex) {
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unsafe {
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self.srx_index.write(u8::from(index));
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}
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}
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}
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#[derive(Debug)]
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pub struct GraphicsControllerRegisters {
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grx_index: Port<u8>,
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grx_data: Port<u8>,
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}
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impl GraphicsControllerRegisters {
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pub fn new() -> GraphicsControllerRegisters {
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GraphicsControllerRegisters {
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grx_index: Port::new(GRX_INDEX_ADDRESS),
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grx_data: Port::new(GRX_DATA_ADDRESS),
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}
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}
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pub fn read(&mut self, index: GraphicsControllerIndex) -> u8 {
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self.set_index(index);
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unsafe { self.grx_data.read() }
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}
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pub fn write(&mut self, index: GraphicsControllerIndex, value: u8) {
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self.set_index(index);
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unsafe {
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self.grx_data.write(value);
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}
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}
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fn set_index(&mut self, index: GraphicsControllerIndex) {
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unsafe {
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self.grx_index.write(u8::from(index));
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}
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}
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}
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#[derive(Debug)]
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pub struct AttributeControllerRegisters {
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arx_index: Port<u8>,
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arx_data: Port<u8>,
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st01_read_cga: Port<u8>,
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st01_read_mda: Port<u8>,
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}
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impl AttributeControllerRegisters {
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pub fn new() -> AttributeControllerRegisters {
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AttributeControllerRegisters {
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arx_index: Port::new(ARX_INDEX_ADDRESS),
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arx_data: Port::new(ARX_DATA_ADDRESS),
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st01_read_cga: Port::new(ST01_READ_CGA_ADDRESS),
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st01_read_mda: Port::new(ST01_READ_MDA_ADDRESS),
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}
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}
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pub fn write(
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&mut self,
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emulation_mode: EmulationMode,
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index: AttributeControllerIndex,
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value: u8,
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) {
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self.toggle_index(emulation_mode);
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self.set_index(index);
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unsafe {
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self.arx_index.write(value);
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}
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}
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fn set_index(&mut self, index: AttributeControllerIndex) {
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unsafe {
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self.arx_index.write(u8::from(index));
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}
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}
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fn toggle_index(&mut self, emulation_mode: EmulationMode) {
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let st01_read = match emulation_mode {
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EmulationMode::Cga => &mut self.st01_read_cga,
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EmulationMode::Mda => &mut self.st01_read_mda,
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};
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unsafe {
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st01_read.read();
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}
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}
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/// Video Enable. Note that In the VGA standard, this is called the "Palette Address Source" bit.
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/// Clearing this bit will cause the VGA display data to become all 00 index values. For the default
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/// palette, this will cause a black screen. The video timing signals continue. Another control bit will
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/// turn video off and stop the data fetches.
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///
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/// 0 = Disable. Attribute controller color registers (AR[00:0F]) can be accessed by the CPU.
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///
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/// 1 = Enable. Attribute controller color registers (AR[00:0F]) are inaccessible by the CPU.
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pub fn blank_screen(&mut self, emulation_mode: EmulationMode) {
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self.toggle_index(emulation_mode);
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let arx_index_value = unsafe { self.arx_index.read() };
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unsafe {
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self.arx_index.write(arx_index_value & 0xDF);
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}
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}
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/// Video Enable. Note that In the VGA standard, this is called the "Palette Address Source" bit.
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/// Clearing this bit will cause the VGA display data to become all 00 index values. For the default
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/// palette, this will cause a black screen. The video timing signals continue. Another control bit will
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/// turn video off and stop the data fetches.
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///
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/// 0 = Disable. Attribute controller color registers (AR[00:0F]) can be accessed by the CPU.
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///
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/// 1 = Enable. Attribute controller color registers (AR[00:0F]) are inaccessible by the CPU.
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pub fn unblank_screen(&mut self, emulation_mode: EmulationMode) {
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self.toggle_index(emulation_mode);
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let arx_index_value = unsafe { self.arx_index.read() };
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unsafe {
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self.arx_index.write(arx_index_value | 0x20);
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}
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}
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}
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#[derive(Debug)]
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pub struct CrtcControllerRegisters {
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crx_index_cga: Port<u8>,
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crx_index_mda: Port<u8>,
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crx_data_cga: Port<u8>,
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crx_data_mda: Port<u8>,
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}
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impl CrtcControllerRegisters {
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pub fn new() -> CrtcControllerRegisters {
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CrtcControllerRegisters {
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crx_index_cga: Port::new(CRX_INDEX_CGA_ADDRESS),
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crx_index_mda: Port::new(CRX_INDEX_MDA_ADDRESS),
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crx_data_cga: Port::new(CRX_DATA_CGA_ADDRESS),
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crx_data_mda: Port::new(CRX_DATA_MDA_ADDRESS),
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}
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}
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pub fn read(&mut self, emulation_mode: EmulationMode, index: CrtcControllerIndex) -> u8 {
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self.set_index(emulation_mode, index);
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unsafe { self.get_data_port(emulation_mode).read() }
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}
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pub fn write(&mut self, emulation_mode: EmulationMode, index: CrtcControllerIndex, value: u8) {
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self.set_index(emulation_mode, index);
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unsafe {
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self.get_data_port(emulation_mode).write(value);
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}
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}
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fn set_index(&mut self, emulation_mode: EmulationMode, index: CrtcControllerIndex) {
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unsafe {
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self.get_index_port(emulation_mode).write(u8::from(index));
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}
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}
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fn get_data_port(&mut self, emulation_mode: EmulationMode) -> &mut Port<u8> {
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match emulation_mode {
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EmulationMode::Cga => &mut self.crx_data_cga,
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EmulationMode::Mda => &mut self.crx_data_mda,
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}
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}
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fn get_index_port(&mut self, emulation_mode: EmulationMode) -> &mut Port<u8> {
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match emulation_mode {
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EmulationMode::Cga => &mut self.crx_index_cga,
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EmulationMode::Mda => &mut self.crx_index_mda,
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}
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}
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}
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