495 lines
10 KiB
NASM
495 lines
10 KiB
NASM
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title "PcCard IRQ detection"
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;++
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;
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; Copyright (c) 1989 Microsoft Corporation
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;
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; Module Name:
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;
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; pccarda.asm
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;
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; Abstract:
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;
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; This module implements the assembly code necessary to support the
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; scanning of ISA IRQ's for cardbus controllers.
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;
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; Author:
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;
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; Neil Sandlin (neilsa) 10-Dec-1991.
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; The "Clear_IR" routines were taken from win9x code (vpicd)
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;
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; Environment:
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;
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; x86 Real Mode.
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;
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; Revision History:
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;
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;
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;--
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.xlist
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include pccard.inc
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.list
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.386
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_DATA SEGMENT PARA USE16 PUBLIC 'DATA'
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_DATA ENDS
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_TEXT SEGMENT PARA USE16 PUBLIC 'CODE'
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ASSUME CS: _TEXT, DS:NOTHING, SS:NOTHING
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;++
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;
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; clr_ir_int_proc
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;
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; Routine Description:
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;
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; Interrupt handler for clearing IR bit. Just EOIs the PICs.
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;
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; Arguments:
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;
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; None.
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;
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; Return Value:
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;
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; None.
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;
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;--
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Clr_IR_Int dw 0 ; Current int # being processed
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public clr_ir_int_proc
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clr_ir_int_proc proc far
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push ax
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mov ax, Clr_IR_Int
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cmp ax, 8 ; Q: is int on the master PIC?
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jb CIP_eoi ; Y: only eoi master PIC
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sub ax, 8 ; AL = int on slave PIC
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or al, PIC_SPEC_EOI
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out PIC_A0, al ; EOI the specific interrupt
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mov al, 2 ; EOI the master PIC
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CIP_eoi:
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or al, PIC_SPEC_EOI
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out PIC_20, al ; EOI the specific interrupt
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mov al, 0FFh ; Mask all interrupts
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out PIC_A1, al
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out PIC_21, al
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pop ax
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iret
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clr_ir_int_proc endp
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;++
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;
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; clr_ir_enable_int
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;
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; Routine Description:
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;
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;
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; Arguments:
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;
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; EAX = interrupt to hook and enable.
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; Interrupts must be disabled on entry.
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;
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; Return Value:
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;
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; None.
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;
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;--
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clr_ir_enable_int proc near
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push bx
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push esi
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; Hook interrupt so it can be handled.
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mov Clr_IR_Int, ax ; Set current interrupt being processed
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cmp ax, 8 ; Q: is int on the master PIC?
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jb CIEI_master ; Y: based at 8
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add ax, 68h ; N: based at 70h
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jmp CIEI_vector
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CIEI_master:
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add ax, 8
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CIEI_vector:
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mov bx, ax
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shl bx, 2 ; IVT vector offset
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push ds
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mov ax, 0
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mov ds, ax
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ASSUME DS:NOTHING
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mov si, offset clr_ir_int_proc
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xchg word ptr [bx], si ; LSW
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ror esi, 16
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push cs
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pop si
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xchg word ptr [bx+2], si ; MSW
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ror esi, 16 ; ESI = old handler offset
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pop ds
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ASSUME DS:_DATA
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sti
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nop ; allow interrupt to occur
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nop
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nop
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cli
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; UnHook interrupt.
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push ds
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mov ax, 0
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mov ds, ax
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ASSUME DS:NOTHING
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mov word ptr [bx], si ; Restore LSW
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ror esi, 16
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mov word ptr [bx+2], si ; Restore MSW
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pop ds
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ASSUME DS:_DATA
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pop esi
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pop bx
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ret
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clr_ir_enable_int endp
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;++
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;
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; _Clear_IR_Bits
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;
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; Routine Description:
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;
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; This routine and its support routines were copied (and munged) from
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; win9x's vxd\vpicd\vpicserv.asm.
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;
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; Clears the desired Interrupt Request bits in the PIC.
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; Interrupt must be masked at the PIC on entry.
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;
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; Arguments:
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;
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; [ESP+4] = bit mask of bits to clear
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; Interrupts must be disabled on entry.
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;
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; Return Value:
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;
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; None.
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;
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;--
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public _Clear_IR_Bits
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_Clear_IR_Bits proc near
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push bp
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mov bp, sp
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BitMask equ [bp+4]
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push eax
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push ebx
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push ecx
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push edx
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mov bx, BitMask ; BX = mask to clear
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or bx, bx ; Are there any bits to clear?
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jz CIB_exit ; no, return
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pushfd
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cli
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in al, PIC_A1
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mov ah, al
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in al, PIC_21
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push eax
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mov al, 0FFh
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out PIC_A1, al
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; Walk each bit from the lowest bit to highest on each controller.
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mov ecx, 01h ; CL = test mask
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CIB_loop20:
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test bl, cl
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jz CIB_next20
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mov al, cl
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not al
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out PIC_21, al ; Unmask the specific interrupt
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bsf eax, ecx
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call clr_ir_enable_int ; Hook interrupt and enable it
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mov al, 0FFh ; Mask all interrupts
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out PIC_21, al
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CIB_next20:
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shl cl, 1
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jnz CIB_loop20 ; Clear next bit
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; Setup for second PIC. Handle the second controller by setting
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; up both PICs, since they are chained.
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mov bl, bh ; BL = second PICs mask to clear
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mov cl, 01h ; CL = test mask
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CIB_loopA0:
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test bl, cl
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jz CIB_nextA0
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mov al, 0FBh ; Mask for chained master PIC
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out PIC_21, al ; Unmask the specific interrupt
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mov al, cl
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not al
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out PIC_A1, al ; Unmask the specific interrupt
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xchg cl, ch
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bsf eax, ecx
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call clr_ir_enable_int ; Hook interrupt and enable it
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xchg cl, ch
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mov al, 0FFh ; Mask all interrupts
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out PIC_A1, al
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out PIC_21, al
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CIB_nextA0:
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shl cl, 1
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jnz CIB_loopA0 ; Clear next bit
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pop eax
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out PIC_21, al
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mov al, ah
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out PIC_A1, al
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popfd
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CIB_exit:
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pop edx
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pop ecx
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pop ebx
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pop eax
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mov sp, bp
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pop bp
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ret
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_Clear_IR_Bits endp
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;++
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;
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; GetPCIType1Data
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;
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; Routine Description:
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;
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; Arguments:
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;
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; Return Value:
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;
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; None.
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;
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;--
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public _GetPCIType1Data
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_GetPCIType1Data proc near
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push bp
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mov bp, sp
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push bx
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push di
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gpd_addr equ [bp+4]
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gpd_offset equ [bp+8]
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gpd_buffer equ [bp+10]
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gpd_width equ [bp+12]
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mov dx, PCI_TYPE1_ADDR_PORT
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mov eax, gpd_addr
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out dx, eax
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mov bx, gpd_buffer
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mov dx, gpd_offset
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add dx, PCI_TYPE1_DATA_PORT
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mov di, gpd_width
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cmp di, 1
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jnz @f
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in al, dx
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mov [bx], al
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jmp gpd_exit
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@@:
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cmp di, 2
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jnz @f
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in ax, dx
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mov [bx], al
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mov [bx+1], ah
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jmp gpd_exit
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@@:
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cmp di, 4
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jnz gpd_exit
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in eax, dx
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mov [bx], al
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mov [bx+1], ah
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shr eax, 16
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mov [bx+2], al
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mov [bx+3], ah
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gpd_exit:
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pop di
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pop bx
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mov sp, bp
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pop bp
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ret
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_GetPCIType1Data endp
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;++
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;
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; SetPCIType1Data
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;
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; Routine Description:
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;
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; Arguments:
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;
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; Return Value:
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;
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; None.
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;
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;--
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public _SetPCIType1Data
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_SetPCIType1Data proc near
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push bp
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mov bp, sp
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push bx
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push di
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spd_addr equ [bp+4]
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spd_offset equ [bp+8]
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spd_buffer equ [bp+10]
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spd_width equ [bp+12]
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mov dx, PCI_TYPE1_ADDR_PORT
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mov eax, spd_addr
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out dx, eax
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mov bx, spd_buffer
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mov dx, spd_offset
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add dx, PCI_TYPE1_DATA_PORT
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mov di, spd_width
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cmp di, 1
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jnz @f
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mov al, [bx]
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out dx, al
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jmp spd_exit
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@@:
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cmp di, 2
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jnz @f
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mov al, [bx]
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mov ah, [bx+1]
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out dx, ax
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jmp spd_exit
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@@:
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cmp di, 4
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jnz spd_exit
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mov al, [bx+2]
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mov ah, [bx+3]
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shl eax, 16
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mov al, [bx]
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mov ah, [bx+1]
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out dx, eax
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spd_exit:
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pop di
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pop bx
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mov sp, bp
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pop bp
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ret
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_SetPCIType1Data endp
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;++
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;
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; TimeOut
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;
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; Routine Description:
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;
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; This routine implements a stall for waiting on hardware. It uses the
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; PC timer hardware (8237). The caller needs to insure that this hardware
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; exists on the machine before calling this function.
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;
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; The function will take as input the count, and decrement the count
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; matching the timer hardware's count. It returns when the count reaches
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; zero. The caller must insure that the clock is programmed at the
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; desired rate.
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;
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; Arguments:
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;
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; Count - number of clock ticks to wait (approx 840ns per tick)
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;
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; Return Value:
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;
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; None.
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;
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;--
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public _TimeOut
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_TimeOut proc near
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TMCTRL_LATCHCNT0 equ 0d2h
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TIMERPORT_CONTROL equ 43h
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TIMERPORT_CNT0 equ 40h
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push bp
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mov bp, sp
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push cx
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push si
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push di
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|
||
|
|
to_count equ [bp+4]
|
||
|
|
|
||
|
|
mov dx, TIMERPORT_CONTROL
|
||
|
|
mov al, TMCTRL_LATCHCNT0
|
||
|
|
out dx, al
|
||
|
|
|
||
|
|
mov dx, TIMERPORT_CNT0
|
||
|
|
in al, dx
|
||
|
|
mov ah, al
|
||
|
|
in al, dx
|
||
|
|
xchg ah, al
|
||
|
|
mov si, ax
|
||
|
|
xor cx, cx
|
||
|
|
|
||
|
|
; si = prevtime
|
||
|
|
; cx = ExpireTime
|
||
|
|
|
||
|
|
timeloop:
|
||
|
|
mov dx, TIMERPORT_CONTROL
|
||
|
|
mov al, TMCTRL_LATCHCNT0
|
||
|
|
out dx, al
|
||
|
|
mov dx, TIMERPORT_CNT0
|
||
|
|
in al, dx
|
||
|
|
mov ah, al
|
||
|
|
in al, dx
|
||
|
|
xchg ah, al
|
||
|
|
mov di, ax
|
||
|
|
|
||
|
|
cmp ax, si
|
||
|
|
jbe @f
|
||
|
|
; wrapped
|
||
|
|
neg ax
|
||
|
|
add ax, si
|
||
|
|
add cx, ax
|
||
|
|
jmp timeincr
|
||
|
|
@@:
|
||
|
|
sub si, ax
|
||
|
|
add cx, si
|
||
|
|
timeincr:
|
||
|
|
mov si, di
|
||
|
|
cmp cx, to_count
|
||
|
|
jb timeloop
|
||
|
|
|
||
|
|
pop di
|
||
|
|
pop si
|
||
|
|
pop cx
|
||
|
|
mov sp, bp
|
||
|
|
pop bp
|
||
|
|
ret
|
||
|
|
_TimeOut endp
|
||
|
|
|
||
|
|
|
||
|
|
_TEXT ends
|
||
|
|
|
||
|
|
|
||
|
|
end
|