380 lines
12 KiB
C
380 lines
12 KiB
C
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/******************************************************************************\
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*
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* FileName: AGPCPQ.H
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*
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* Group: AGP (Accelerated Graphics Port)
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*
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* Level: Driver
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*
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* Date: December 15, 1997
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*
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* Author: John Theisen
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*
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********************************************************************************
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*
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* Module Functional Description:
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*
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* This is the header file for Compaq's Accelerated Graphics Port (AGP)
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* GART MiniPort driver.
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*
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********************************************************************************
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*
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* History:
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*
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* DATE REV. DESCRIPTION DELEVOPER
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* -------- ---- ------------------------------------ -------------------------
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*
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* 12/15/97 1.00 Initial Revision. John Theisen
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*
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\******************************************************************************/
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#define _NTDRIVER_
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#include "stdarg.h"
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#include "stdio.h"
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#include "ntos.h"
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#include "pci.h"
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#include "wdmguid.h"
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#include "zwapi.h"
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#include "ntpoapi.h"
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#include "agp.h"
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//
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// Device/Function/Bus numbers for the primary and secondary north bridges.
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//
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// "Primary" values are the same for RCC and Draco.
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// "Secondary" values are only relevant on RCC HPSA machines.
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// (By definition, if a northbridge exists at this location, then it is an HPSA machine.)
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//
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#define PRIMARY_LE_BUS_ID 0
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#define SECONDARY_LE_BUS_ID 0
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//
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// PCI_SLOT_NUMBER type = ULONG == [XXXXXXXX XXXXXXXX XXXXXXXX YYYZZZZZ]
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//
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// Where X = reserved
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// Y = function number 0 - 7
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// Z = device number 0 - 255
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//
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#define MAKE_PCI_SLOT_NUMBER(dev, func) ((func << 5) + (dev))
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#define PRIMARY_LE_HOST_DEVICE 0
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#define PRIMARY_LE_HOST_FUNCTION 0
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#define PRIMARY_LE_PCI_DEVICE PRIMARY_LE_HOST_DEVICE
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#define PRIMARY_LE_PCI_FUNCION 1
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#define SECONDARY_LE_HOST_DEVICE 17
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#define SECONDARY_LE_HOST_FUNCTION 0
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#define SECONDARY_LE_PCI_DEVICE SECONDARY_LE_HOST_DEVICE
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#define SECONDARY_LE_PCI_FUNCION 1
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#define PRIMARY_LE_HOSTPCI_SLOT_ID MAKE_PCI_SLOT_NUMBER(PRIMARY_LE_HOST_DEVICE, PRIMARY_LE_HOST_FUNCTION)
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#define PRIMARY_LE_PCIPCI_SLOT_ID MAKE_PCI_SLOT_NUMBER(PRIMARY_LE_PCI_DEVICE, PRIMARY_LE_PCI_FUNCION)
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#define SECONDARY_LE_HOSTPCI_SLOT_ID MAKE_PCI_SLOT_NUMBER(SECONDARY_LE_HOST_DEVICE, SECONDARY_LE_HOST_FUNCTION)
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#define SECONDARY_LE_PCIPCI_SLOT_ID MAKE_PCI_SLOT_NUMBER(SECONDARY_LE_PCI_DEVICE, SECONDARY_LE_PCI_FUNCION)
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//
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//
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//
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#define AGP_CPQ_BUS_ID PRIMARY_LE_BUS_ID
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#define AGP_CPQ_HOSTPCI_SLOT_ID PRIMARY_LE_HOSTPCI_SLOT_ID
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#define AGP_CPQ_PCIPCI_SLOT_ID PRIMARY_LE_PCIPCI_SLOT_ID
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#define OFFSET_DEVICE_VENDOR_ID 0x00
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#define OFFSET_BAR0 0x10 // Base of AGP Device Address Space
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#define OFFSET_BAR1 0x14 // Memory Mapped Control Registers Pointer
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#define OFFSET_AP_SIZE 0x8C // For the RCC chipsets. Draco doesn't implement this.
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#define OFFSET_REV_ID 0x08 // Silicon Revision ID (on RCC chipsets).
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#define MAX_REV_ID_TO_LIMIT_1X 4 // Maximum Silicon Rev ID that has the 2X bug.
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#define MAX_REV_ID_TO_FIX_RQ 5 // Macimum Silicon Rev ID that has the RQ bug.
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#define OFFSET_SHADOW_BYTE 0x93 // Byte that contains the shaddow enable bit (bit 3).
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#define FLAG_DISABLE_SHADOW 0x08
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#define MASK_ENABLE_SHADOW (~FLAG_DISABLE_SHADOW)
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//
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// RCC Vendor-Device IDs (as of August 1998):
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//
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// CNB_20_LE (function 0) -- 0x00071166
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// CNB_20_LE (function 1) -- 0x00051166
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// CNB_20_HE (function 0) -- 0x00081166
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// CNB_20_HE (function 1) -- 0x00091166
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//
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#define AGP_CNB20_LE_IDENTIFIER 0x00071166 // * function 0 ID.
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#define AGP_CNB20_HE_IDENTIFIER 0x00081166
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#define AGP_CNB20_HE4X_IDENTIFIER 0x00131166
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#define AGP_CMIC_GC_IDENTIFIER 0x00151166
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#define AGP_DRACO_IDENTIFIER 0xAE6C0E11 // * Note, support for this chipset is no longer required.
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#define AP_SIZE_DEFAULT 0x10000000 // all chipsets default to 256MB
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#define AP_MAX_SIZE_CNB20_LE 0x80000000 // 2GB
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#define AP_MAX_SIZE_CNB20_HE 0x80000000 // 2GB
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#define AP_MAX_SIZE_DRACO 0x10000000 // 256MB
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#define AP_SIZE_COUNT_CNB20_LE 7
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#define AP_SIZE_COUNT_CNB20_HE 7
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#define AP_SIZE_COUNT_DRACO 1
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#define LOWEST_REVISION_ID_SUPPORTED 1
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#define MAX_CACHED_ENTRIES_TO_INVALIDATE 3
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#define MASK_LOW_TWENTYFIVE (~0x01FFFFFF)
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#define ALL_ONES (~0x0)
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//
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// Conversions from BAR0 read/write-attribute-encoding to aperture sizes.
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//
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// 0x00000000 (b 0000 0000 ...) = 0MB
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// 0xFE000000 (b 1111 1110 ...) = 32MB
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// 0xFC000000 (b 1111 1100 ...) = 64MB
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// 0xF8000000 (b 1111 1000 ...) = 128MB
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// 0xF0000000 (b 1111 0000 ...) = 256MB
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// 0xE0000000 (b 1110 0000 ...) = 512MB
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// 0xC0000000 (b 1100 0000 ...) = 1GB
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// 0x80000000 (b 1000 0000 ...) = 2GB
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#define BAR0_CODED_AP_SIZE_0MB 0x00000000
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#define BAR0_CODED_AP_SIZE_32MB 0xFE000000
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#define BAR0_CODED_AP_SIZE_64MB 0xFC000000
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#define BAR0_CODED_AP_SIZE_128MB 0xF8000000
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#define BAR0_CODED_AP_SIZE_256MB 0xF0000000
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#define BAR0_CODED_AP_SIZE_512MB 0xE0000000
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#define BAR0_CODED_AP_SIZE_1GB 0xC0000000
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#define BAR0_CODED_AP_SIZE_2GB 0x80000000
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//
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// Conversions from the values in bits 3:1 of the AGP Device
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// Address Space Size Register to aperture sizes.
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//
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// 0 (b 000) = 32MB
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// 1 (b 001) = 64MB
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// 2 (b 010) = 128MB
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// 3 (b 011) = 256MB
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// 4 (b 100) = 512MB
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// 5 (b 101) = 1GB
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// 6 (b 110) = 2GB
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// 7 (b 111) -> "Reserved"
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//
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#define SET_AP_SIZE_32MB 0
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#define SET_AP_SIZE_64MB 1
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#define SET_AP_SIZE_128MB 2
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#define SET_AP_SIZE_256MB 3
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#define SET_AP_SIZE_512MB 4
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#define SET_AP_SIZE_1GB 5
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#define SET_AP_SIZE_2GB 6
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#define BYTES_2G 0x80000000UL // 2G Value, to avoid integral const. overflow
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//
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// Taken from config.c
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//
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typedef struct _BUS_SLOT_ID {
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ULONG BusId;
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ULONG SlotId;
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} BUS_SLOT_ID, *PBUS_SLOT_ID;
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//
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// Macros for reading and writing to the Host-PCI Bridge registers
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//
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#define ReadCPQConfig(_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalGetBusDataByOffset(PCIConfiguration, \
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AGP_CPQ_BUS_ID, \
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AGP_CPQ_HOSTPCI_SLOT_ID, \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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ASSERT(_len_ == (_size_)); \
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}
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#define WriteCPQConfig(_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalSetBusDataByOffset(PCIConfiguration, \
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AGP_CPQ_BUS_ID, \
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AGP_CPQ_HOSTPCI_SLOT_ID, \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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ASSERT(_len_ == (_size_)); \
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}
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//
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// Macro to translate the APSIZE encoding into MB.
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//
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#define TranslateCodedValueIntoApSize(_apsize_, _value_) \
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{ \
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_apsize_ = (((_value_ & MASK_LOW_TWENTYFIVE) ^ ALL_ONES) + 1); \
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}
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//
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// GART table entry.
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//
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typedef struct _GART_ENTRY_HW {
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ULONG Valid : 1;
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ULONG Linked : 1;
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ULONG Dirty : 1;
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ULONG Rsrvd1 : 9;
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ULONG Page : 20;
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} GART_ENTRY_HW, *PGART_ENTRY_HW;
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typedef struct _GART_ENTRY_SW {
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ULONG State : 5;
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ULONG Rsrvd1 : 27;
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} GART_ENTRY_SW, *PGART_ENTRY_SW;
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typedef struct _GART_PTE {
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union {
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GART_ENTRY_HW Hard;
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ULONG AsUlong;
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GART_ENTRY_SW Soft;
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};
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} GART_PTE, *PGART_PTE;
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//
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// GART Entry bits
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//
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#define GART_ENTRY_INVALID 0x00 // 00000
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#define GART_ENTRY_VALID 0x01 // 00001
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#define GART_ENTRY_LINKED 0x02 // 00010
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#define GART_ENTRY_DIRTY 0x04 // 00100
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#define GART_ENTRY_WC 0x08 // 01000
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#define GART_ENTRY_UC 0x10 // 10000
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//
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// Defined GART Entry states.
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//
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#define GART_ENTRY_FREE GART_ENTRY_INVALID
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#define GART_ENTRY_RESERVED_WC GART_ENTRY_WC
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#define GART_ENTRY_RESERVED_UC GART_ENTRY_UC
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#define GART_ENTRY_VALID_WC (GART_ENTRY_VALID)
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#define GART_ENTRY_VALID_UC (GART_ENTRY_VALID)
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#define GART_ENTRY_VALID_WC_LINKED (GART_ENTRY_VALID_WC | GART_ENTRY_LINKED)
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#define GART_ENTRY_VALID_UC_LINKED (GART_ENTRY_VALID_UC | GART_ENTRY_LINKED)
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//
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// Memory Mapped Control Registers.
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//
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typedef struct _GART_CACHE_ENTRY_CONTROL_REGISTER {
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ULONG volatile GartEntryInvalidate:1;
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ULONG volatile GartEntryUpdate:1;
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ULONG Rsrvd1:10;
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ULONG volatile GartEntryOffset:20;
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} GART_CACHE_ENTRY_CONTROL_REGISTER, *PGART_CACHE_ENTRY_CONTROL_REGISTER;
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typedef struct _GART_CACHE_ENTRY_CONTROL {
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union {
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GART_CACHE_ENTRY_CONTROL_REGISTER AsBits;
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ULONG volatile AsDword;
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};
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} GART_CACHE_ENTRY_CONTROL, *PGART_CACHE_ENTRY_CONTROL;
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typedef struct _MM_CONTROL_REGS {
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UCHAR RevisionID;
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struct _GART_CAPABILITES {
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UCHAR ValidBitErrorReportingSupported:1;
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UCHAR LinkingSupported:1;
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UCHAR TwoLevelAddrTransSupported:1;
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UCHAR BusCountersSupported:1;
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UCHAR Rsrvd1:4;
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} Capabilities;
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struct _GART_FEATURE_CONTROL {
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UCHAR ValidBitErrorReportingEnable:1;
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UCHAR LinkingEnable:1;
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UCHAR Rsrvd1:1;
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UCHAR GARTCacheEnable:1;
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UCHAR Rsrvd2:4;
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} FeatureControl;
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struct _GART_FEATURE_STATUS {
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UCHAR volatile ValidBitErrorDetected:1;
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UCHAR Rsrvd1:7;
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} FeatureStatus;
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struct _GART_BASE_ADDRESS {
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ULONG Rsrvd1:12;
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ULONG Page:20;
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} GartBase;
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struct _GART_AND_DIR_CACHE_SIZES {
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ULONG MaxTableEntries:16;
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ULONG MaxDirEntries:16;
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} CacheSize;
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struct _GART_CACHE_CONTROL {
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ULONG volatile GartAndDirCacheInvalidate:1;
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ULONG Rsrvd1:31;
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} CacheControl;
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GART_CACHE_ENTRY_CONTROL CacheEntryControl;
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struct _POSTED_WRITE_BUFFER_CONTROL {
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UCHAR volatile Flush:1;
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UCHAR Rsrvd1:7;
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} PostedWriteBufferControl;
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struct _AGP_BUS_COUNTERS_COMMAND {
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UCHAR volatile ClearCounters:1;
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UCHAR EnableUtilization:1;
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UCHAR EnableBandwidth:1;
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UCHAR EnableLatency:1;
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UCHAR Rsrvd1:4;
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} BusCounters;
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USHORT Rsrvd1;
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ULONG BusUtilizationCounter;
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ULONG BusBandwidthCounter;
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ULONG BusLatencyCounter;
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} MM_CONTROL_REGS, *PMM_CONTROL_REGS;
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typedef struct _AGP_DEVICE_ADDRESS_SPACE_SIZE_REG {
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UCHAR Rsrvd1:4;
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UCHAR ApSize:3;
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UCHAR AgpValid:1;
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} AGP_DAS_SIZE_REG, *PAGP_DAS_SIZE_REG;
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typedef struct _AGP_AP_SIZE_REG {
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union {
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AGP_DAS_SIZE_REG AsBits;
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UCHAR AsByte;
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};
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} AGP_AP_SIZE_REG, *PAGP_AP_SIZE_REG;
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//
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// Compaq-specific extension
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//
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typedef struct _AGPCPQ_EXTENSION {
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PMM_CONTROL_REGS MMIO;
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PHYSICAL_ADDRESS ApertureStart;
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ULONG ApertureLength;
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PGART_PTE Gart;
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PVOID Dir;
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ULONG GartLength;
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ULONG MaxGartLength;
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ULONG DeviceVendorID;
|
||
|
|
ULONG GartPointer;
|
||
|
|
BOOLEAN IsHPSA;
|
||
|
|
ULONGLONG SpecialTarget;
|
||
|
|
} AGPCPQ_EXTENSION, *PAGPCPQ_EXTENSION;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Taken from Config.c
|
||
|
|
//
|
||
|
|
extern
|
||
|
|
NTSTATUS
|
||
|
|
ApGetSetBusData(
|
||
|
|
IN PBUS_SLOT_ID BusSlotId,
|
||
|
|
IN BOOLEAN Read,
|
||
|
|
IN PVOID Buffer,
|
||
|
|
IN ULONG Offset,
|
||
|
|
IN ULONG Length
|
||
|
|
);
|
||
|
|
|
||
|
|
extern
|
||
|
|
NTSTATUS
|
||
|
|
DnbSetShadowBit(
|
||
|
|
ULONG SetToOne
|
||
|
|
);
|
||
|
|
|