432 lines
14 KiB
C
432 lines
14 KiB
C
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/*++
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Copyright (c) 1996, 1997 Microsoft Corporation
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Module Name:
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init.c
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Abstract:
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This module contains the initialization code for the Compaq driver.
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Author:
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John Vert (jvert) 10/21/1997
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Revision History:
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12/15/97 John Theisen Modified to support Compaq Chipsets
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10/09/98 John Theisen Modified to workaround an RCC silicon bug.
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If RCC Silicon Rev <= 4, then limit DATA_RATE to 1X.
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10/09/98 John Theisen Modified to enable Shadowing in the SP700 prior to MMIO writes.
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01/15/98 John Theisen Modified to set RQ depth to be 0x0F for all REV_IDs
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03/14/00 Peter Johnston Add support for HE chipset.
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--*/
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#include "AGPCPQ.H"
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ULONG AgpExtensionSize = sizeof(AGPCPQ_EXTENSION);
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PAGP_FLUSH_PAGES AgpFlushPages = NULL; // not implemented
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NTSTATUS
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AgpInitializeTarget(
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IN PVOID AgpExtension
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)
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/*******************************************************************************
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*
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* Routine Functional Description:
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*
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* This function is the entrypoint for initialization of the AGP Target. It
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* is called first, and performs initialization of the chipset and extension.
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*
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* Assumptions: Regardless of whether we are running on a dual north bridge platform,
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* this driver will only be installed and invoked once (for the AGP bridge at B0D0F1).
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*
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* Arguments:
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*
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* AgpExtension -- Supplies the AGP Extension
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*
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* Return Value:
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*
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* STATUS_SUCCESS if successfull
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*
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*******************************************************************************/
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{
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ULONG DeviceVendorID = 0;
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ULONG BAR1 = 0;
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PAGPCPQ_EXTENSION Extension = AgpExtension;
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PHYSICAL_ADDRESS pa;
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ULONG BytesReturned = 0;
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AGPLOG(AGP_NOISE, ("AgpCpq: AgpInitializeTarget entered.\n"));
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//
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// Initialize our Extension
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//
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RtlZeroMemory(Extension, sizeof(AGPCPQ_EXTENSION));
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//
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// Verify that the chipset is a supported RCC Chipset.
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//
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ReadCPQConfig(&DeviceVendorID,OFFSET_DEVICE_VENDOR_ID,sizeof(DeviceVendorID));
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if ((DeviceVendorID != AGP_CNB20_LE_IDENTIFIER) &&
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(DeviceVendorID != AGP_CNB20_HE_IDENTIFIER) &&
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(DeviceVendorID != AGP_CNB20_HE4X_IDENTIFIER) &&
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(DeviceVendorID != AGP_CMIC_GC_IDENTIFIER)) {
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AGPLOG(AGP_CRITICAL,
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("AGPCPQ - AgpInitializeTarget was called for platform %08x, which is not a known RCC AGP chipset!\n",
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DeviceVendorID));
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return(STATUS_UNSUCCESSFUL);
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}
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Extension->DeviceVendorID = DeviceVendorID;
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//
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// Read the chipset's BAR1 Register, and then map the chipset's
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// Memory Mapped Control Registers into kernel mode address space.
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//
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ReadCPQConfig(&BAR1,OFFSET_BAR1,sizeof(BAR1));
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pa.HighPart = 0;
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pa.LowPart = BAR1;
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Extension->MMIO = (PMM_CONTROL_REGS)MmMapIoSpace(pa, sizeof(MM_CONTROL_REGS), FALSE);
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if (Extension->MMIO == NULL)
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{
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AGPLOG(AGP_CRITICAL,
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("AgpInitializeTarget - Couldn't allocate %08x bytes for MMIO\n",
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sizeof(MM_CONTROL_REGS)));
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return(STATUS_UNSUCCESSFUL);
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}
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//
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// Verify that the chipset's Revision ID is correct, but only complain, if it isn't.
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//
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if (Extension->MMIO->RevisionID < LOWEST_REVISION_ID_SUPPORTED)
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{
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AGPLOG(AGP_CRITICAL,
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("AgpInitializeTarget - Revision ID = %08x, it should = 1.\n",
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Extension->MMIO->RevisionID));
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}
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//
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// Determine if there are two RCC North Bridges in this system.
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//
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DeviceVendorID = 0;
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BytesReturned = HalGetBusDataByOffset(PCIConfiguration, SECONDARY_LE_BUS_ID, SECONDARY_LE_HOSTPCI_SLOT_ID,
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&DeviceVendorID, OFFSET_DEVICE_VENDOR_ID, sizeof(DeviceVendorID));
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if((DeviceVendorID != Extension->DeviceVendorID) || (BytesReturned != sizeof(DeviceVendorID)) ) {
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Extension->IsHPSA = FALSE;
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} else {
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Extension->IsHPSA = TRUE;
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}
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//
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// Enable the GART cache
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//
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if (Extension->IsHPSA) DnbSetShadowBit(0);
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Extension->MMIO->FeatureControl.GARTCacheEnable = 1;
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Extension->GartPointer = 0;
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Extension->SpecialTarget = 0;
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//
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// If the chipset supports linking then enable linking.
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//
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if (Extension->MMIO->Capabilities.LinkingSupported==1) {
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Extension->MMIO->FeatureControl.LinkingEnable=1;
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}
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if (Extension->IsHPSA) DnbSetShadowBit(1);
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return(STATUS_SUCCESS);
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}
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NTSTATUS
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AgpInitializeMaster(
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IN PVOID AgpExtension,
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OUT ULONG *AgpCapabilities
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)
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/*******************************************************************************
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*
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* Routine Functional Description:
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*
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* This function is the entrypoint for initialization of the AGP Master. It
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* is called after Target initialization, and is intended to be used to
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* initialize the AGP capabilities of both master and target.
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*
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* Arguments:
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*
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* AgpExtension -- Supplies the AGP Extension
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*
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* AgpCapabilities -- Returns the "software-visible" capabilities of the device
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*
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* Return Value:
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*
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* NTSTATUS
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*
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*******************************************************************************/
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{
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NTSTATUS Status;
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PCI_AGP_CAPABILITY MasterCap;
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PCI_AGP_CAPABILITY TargetCap;
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PAGPCPQ_EXTENSION Extension = AgpExtension;
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ULONG SBAEnable;
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ULONG FastWrite;
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ULONG DataRate;
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UCHAR RevID = 0;
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BOOLEAN ReverseInit;
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AGPLOG(AGP_NOISE, ("AgpCpq: AgpInitializeMaster entered.\n"));
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//
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// Get the master and target AGP capabilities
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//
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Status = AgpLibGetMasterCapability(AgpExtension, &MasterCap);
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if (!NT_SUCCESS(Status))
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{
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AGPLOG(AGP_CRITICAL,
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("AGPCPQInitializeDevice - AgpLibGetMasterCapability failed %08lx\n",
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Status));
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return(Status);
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}
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Status = AgpLibGetPciDeviceCapability(AGP_CPQ_BUS_ID,
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AGP_CPQ_PCIPCI_SLOT_ID,
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&TargetCap);
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if (!NT_SUCCESS(Status))
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{
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AGPLOG(AGP_CRITICAL,
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("AGPCPQInitializeDevice - AgpLibGetPciDeviceCapability failed %08lx\n",
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Status));
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return(Status);
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}
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//
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// Determine the greatest common denominator for data rate.
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//
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DataRate = TargetCap.AGPStatus.Rate & MasterCap.AGPStatus.Rate;
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ASSERT(DataRate != 0);
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//
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// Select the highest common rate.
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//
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if (DataRate & PCI_AGP_RATE_4X) {
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DataRate = PCI_AGP_RATE_4X;
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} else if (DataRate & PCI_AGP_RATE_2X) {
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DataRate = PCI_AGP_RATE_2X;
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} else if (DataRate & PCI_AGP_RATE_1X) {
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DataRate = PCI_AGP_RATE_1X;
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}
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//
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// Previously a call was made to change the rate (successfully),
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// use this rate again now
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//
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if (Extension->SpecialTarget & AGP_FLAG_SPECIAL_RESERVE) {
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DataRate = (ULONG)((Extension->SpecialTarget &
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AGP_FLAG_SPECIAL_RESERVE) >>
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AGP_FLAG_SET_RATE_SHIFT);
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}
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//
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// FIX RCC silicon bugs:
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// If RevID <= 4, then the reported Data Rate is 2X but the chip only supports 1X.
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// Regardless of RevID the reported RQDepth should be 0x0F.
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//
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if (Extension->DeviceVendorID == AGP_CNB20_LE_IDENTIFIER) {
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ReadCPQConfig(&RevID, OFFSET_REV_ID, sizeof(RevID));
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ASSERT(TargetCap.AGPStatus.RequestQueueDepthMaximum == 0x10);
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TargetCap.AGPStatus.RequestQueueDepthMaximum = 0x0F;
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if (RevID <= MAX_REV_ID_TO_LIMIT_1X) {
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DataRate = PCI_AGP_RATE_1X;
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}
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}
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//
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// Enable SBA if both master and target support it.
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//
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SBAEnable = (TargetCap.AGPStatus.SideBandAddressing &
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MasterCap.AGPStatus.SideBandAddressing);
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//
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// Enable FastWrite if both master and target support it.
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//
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FastWrite = (TargetCap.AGPStatus.FastWrite &
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MasterCap.AGPStatus.FastWrite);
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//
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// Enable the Master first.
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//
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ReverseInit =
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(Extension->SpecialTarget & AGP_FLAG_REVERSE_INITIALIZATION) ==
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AGP_FLAG_REVERSE_INITIALIZATION;
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if (ReverseInit) {
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MasterCap.AGPCommand.Rate = DataRate;
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MasterCap.AGPCommand.AGPEnable = 1;
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MasterCap.AGPCommand.SBAEnable = SBAEnable;
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MasterCap.AGPCommand.FastWriteEnable = FastWrite;
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MasterCap.AGPCommand.RequestQueueDepth = TargetCap.AGPStatus.RequestQueueDepthMaximum;
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Status = AgpLibSetMasterCapability(AgpExtension, &MasterCap);
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if (!NT_SUCCESS(Status))
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{
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AGPLOG(AGP_CRITICAL,
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("AGPCPQInitializeDevice - AgpLibSetMasterCapability %08lx failed %08lx\n",
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&MasterCap,
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Status));
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}
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}
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//
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// Now enable the Target.
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//
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TargetCap.AGPCommand.Rate = DataRate;
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TargetCap.AGPCommand.AGPEnable = 1;
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TargetCap.AGPCommand.SBAEnable = SBAEnable;
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TargetCap.AGPCommand.FastWriteEnable = FastWrite;
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Status = AgpLibSetPciDeviceCapability(AGP_CPQ_BUS_ID,
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AGP_CPQ_PCIPCI_SLOT_ID,
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&TargetCap);
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if (!NT_SUCCESS(Status))
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{
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AGPLOG(AGP_CRITICAL,
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("AGPCPQInitializeDevice - AgpLibSetPciDeviceCapability %08lx for target failed %08lx\n",
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&TargetCap,
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Status));
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return(Status);
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}
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if (!ReverseInit) {
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MasterCap.AGPCommand.Rate = DataRate;
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MasterCap.AGPCommand.AGPEnable = 1;
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MasterCap.AGPCommand.SBAEnable = SBAEnable;
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MasterCap.AGPCommand.FastWriteEnable = FastWrite;
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MasterCap.AGPCommand.RequestQueueDepth = TargetCap.AGPStatus.RequestQueueDepthMaximum;
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Status = AgpLibSetMasterCapability(AgpExtension, &MasterCap);
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if (!NT_SUCCESS(Status))
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{
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AGPLOG(AGP_CRITICAL,
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("AGPCPQInitializeDevice - AgpLibSetMasterCapability %08lx failed %08lx\n",
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&MasterCap,
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Status));
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}
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}
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#if DBG
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{
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PCI_AGP_CAPABILITY CurrentCap;
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//
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// Read them back, see if it worked
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//
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Status = AgpLibGetMasterCapability(AgpExtension, &CurrentCap);
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ASSERT(NT_SUCCESS(Status));
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//
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// If the target request queue depth is greater than the master will
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// allow, it will be trimmed. Loosen the assert to not require an
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// exact match.
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//
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ASSERT(CurrentCap.AGPCommand.RequestQueueDepth <= MasterCap.AGPCommand.RequestQueueDepth);
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CurrentCap.AGPCommand.RequestQueueDepth = MasterCap.AGPCommand.RequestQueueDepth;
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ASSERT(RtlEqualMemory(&CurrentCap.AGPCommand, &MasterCap.AGPCommand, sizeof(CurrentCap.AGPCommand)));
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Status = AgpLibGetPciDeviceCapability(AGP_CPQ_BUS_ID,
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AGP_CPQ_PCIPCI_SLOT_ID,
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&CurrentCap);
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ASSERT(NT_SUCCESS(Status));
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ASSERT(RtlEqualMemory(&CurrentCap.AGPCommand, &TargetCap.AGPCommand,
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sizeof(CurrentCap.AGPCommand)));
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}
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#endif
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//
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// Indicate that we can map memory through the GART aperture
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//
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*AgpCapabilities = AGP_CAPABILITIES_MAP_PHYSICAL;
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return(Status);
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}
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NTSTATUS
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DnbSetShadowBit(
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ULONG SetToOne
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)
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//
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// This routine is required, (because of a new requirement in the RCC chipset.).
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// When there are two NorthBridge's, the shadow bit must be set to 0 prior
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// to any MMIO writes, and then set back to 1 when done.
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//
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{
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NTSTATUS Status = STATUS_SUCCESS; // Assume Success
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UCHAR ShadowByte = 0;
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ULONG BytesReturned = 0;
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ULONG length = 1;
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if (SetToOne == 1) {
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//
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// Set the shadow bit to a one. (This disables shadowing.)
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//
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BytesReturned = HalGetBusDataByOffset(PCIConfiguration, SECONDARY_LE_BUS_ID,
|
||
|
|
SECONDARY_LE_HOSTPCI_SLOT_ID, &ShadowByte, OFFSET_SHADOW_BYTE, length);
|
||
|
|
|
||
|
|
if(BytesReturned != length) {
|
||
|
|
AGPLOG(AGP_CRITICAL,("ERROR: Failed to read shadow register!\n"));
|
||
|
|
Status = STATUS_UNSUCCESSFUL;
|
||
|
|
goto exit_routine;
|
||
|
|
}
|
||
|
|
|
||
|
|
ShadowByte |= FLAG_DISABLE_SHADOW;
|
||
|
|
|
||
|
|
HalSetBusDataByOffset(PCIConfiguration, SECONDARY_LE_BUS_ID,
|
||
|
|
SECONDARY_LE_HOSTPCI_SLOT_ID, &ShadowByte, OFFSET_SHADOW_BYTE, length);
|
||
|
|
|
||
|
|
if(BytesReturned != length) {
|
||
|
|
AGPLOG(AGP_CRITICAL,("ERROR: Failed to write shadow register!\n"));
|
||
|
|
Status = STATUS_UNSUCCESSFUL;
|
||
|
|
goto exit_routine;
|
||
|
|
}
|
||
|
|
|
||
|
|
} else {
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set the shadow bit to a zero. (This enables shadowing.)
|
||
|
|
//
|
||
|
|
BytesReturned = HalGetBusDataByOffset(PCIConfiguration, SECONDARY_LE_BUS_ID,
|
||
|
|
SECONDARY_LE_HOSTPCI_SLOT_ID, &ShadowByte, OFFSET_SHADOW_BYTE, length);
|
||
|
|
|
||
|
|
if(BytesReturned != length) {
|
||
|
|
AGPLOG(AGP_CRITICAL,("ERROR: Failed to read shadow register!"));
|
||
|
|
Status = STATUS_UNSUCCESSFUL;
|
||
|
|
goto exit_routine;
|
||
|
|
}
|
||
|
|
|
||
|
|
ShadowByte &= MASK_ENABLE_SHADOW;
|
||
|
|
|
||
|
|
HalSetBusDataByOffset(PCIConfiguration, SECONDARY_LE_BUS_ID,
|
||
|
|
SECONDARY_LE_HOSTPCI_SLOT_ID, &ShadowByte, OFFSET_SHADOW_BYTE, length);
|
||
|
|
|
||
|
|
if(BytesReturned != length) {
|
||
|
|
AGPLOG(AGP_CRITICAL,("ERROR: Failed to write shadow register!"));
|
||
|
|
Status = STATUS_UNSUCCESSFUL;
|
||
|
|
goto exit_routine;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
exit_routine:
|
||
|
|
|
||
|
|
return(Status);
|
||
|
|
}
|