263 lines
9 KiB
C
263 lines
9 KiB
C
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//
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// VIAAGP.sys is a driver, make sure we get the appropriate linkage.
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//
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#define _NTDRIVER_
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#include "stdarg.h"
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#include "stdio.h"
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#include "ntddk.h"
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#include "agp.h"
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//
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// Define the location of the GART aperture control registers
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//
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//
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// The GART registers on the VIA live in the host-PCI bridge.
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// This is unfortunate, since the AGP driver attaches to the PCI-PCI (AGP)
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// bridge. So we have to get to the host-PCI bridge config space
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// and this is only possible because we KNOW this is bus 0, slot 0.
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//
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#define AGP_VIA_GART_BUS_ID 0
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#define AGP_VIA_GART_SLOT_ID 0
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#define AGP_P2P_SLOT_ID 1
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#define AGP_VGA_BUS_ID 1
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#define AGP_VGA_SLOT_ID 0
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#define AGP_VIA_IDENTIFIER 0x00001106
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// 0x05971106 -> VT82C597 / VT82C597 AT
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// chu
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#define GABASE_OFFSET 0x10 // Graphics Aperture Base
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#define GARTCTRL_OFFSET 0x80 // GART/TLB Control
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#define GASIZE_OFFSET 0x84 // Graphics Aperture Size
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#define GATTBASE_OFFSET 0x88 // GA Translation Table Base
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#define VREF_OFFSET 0xB0 // AGP VREF control
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#define AGPMISC_OFFSET 0xAC // AGP MISC control
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#define ReadVIAConfig(_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalGetBusDataByOffset(PCIConfiguration, \
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AGP_VIA_GART_BUS_ID, \
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AGP_VIA_GART_SLOT_ID, \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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ASSERT(_len_ == (_size_)); \
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}
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#define WriteVIAConfig(_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalSetBusDataByOffset(PCIConfiguration, \
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AGP_VIA_GART_BUS_ID, \
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AGP_VIA_GART_SLOT_ID, \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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ASSERT(_len_ == (_size_)); \
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}
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#define ReadP2PConfig(_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalGetBusDataByOffset(PCIConfiguration, \
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AGP_VIA_GART_BUS_ID, \
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AGP_P2P_SLOT_ID, \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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ASSERT(_len_ == (_size_)); \
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}
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#define WriteP2PConfig(_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalSetBusDataByOffset(PCIConfiguration, \
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AGP_VIA_GART_BUS_ID, \
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AGP_P2P_SLOT_ID, \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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ASSERT(_len_ == (_size_)); \
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}
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#define ReadVGAConfig(_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalGetBusDataByOffset(PCIConfiguration, \
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AGP_VGA_BUS_ID, \
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AGP_VGA_SLOT_ID, \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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ASSERT(_len_ == (_size_)); \
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}
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#define WriteVGAConfig(_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalSetBusDataByOffset(PCIConfiguration, \
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AGP_VGA_BUS_ID, \
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AGP_VGA_SLOT_ID, \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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ASSERT(_len_ == (_size_)); \
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}
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#define ON 1
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#define OFF 0
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#define ViaApertureEnable(Enable) \
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{ \
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VIA_GART_TLB_CTRL AGPCTRL_Config; \
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\
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ReadVIAConfig(&AGPCTRL_Config, GARTCTRL_OFFSET, sizeof(AGPCTRL_Config)); \
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AGPCTRL_Config.AGP_ATFGA = (Enable); \
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AGPCTRL_Config.CPU_ATFGA = (Enable); \
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AGPCTRL_Config.PCI2_ATFGA = (Enable); \
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AGPCTRL_Config.PCI1_ATFGA = (Enable); \
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WriteVIAConfig(&AGPCTRL_Config, GARTCTRL_OFFSET, sizeof(AGPCTRL_Config)); \
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}
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#define ViaGartEnable(Enable) \
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{ \
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VIA_GATT_BASE GARTBASE_Config; \
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\
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ReadVIAConfig(&GARTBASE_Config, GATTBASE_OFFSET, sizeof(GARTBASE_Config));\
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GARTBASE_Config.GA_Enable = (Enable); \
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WriteVIAConfig(&GARTBASE_Config, GATTBASE_OFFSET, sizeof(GARTBASE_Config));}
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//
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// Conversions from Graphics Aperture Size encoding to MB
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//
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// 0xFF (b 1111 1111) = 1MB
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// 0xFE (b 1111 1110) = 2MB
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// 0xFC (b 1111 1100) = 4MB
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// 0xF8 (b 1111 1000) = 8MB
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// 0xF0 (b 1111 0000) = 16MB
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// 0xE0 (b 1110 0000) = 32MB
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// 0xC0 (b 1100 0000) = 64MB
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// 0x80 (b 1000 0000) = 128MB
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// 0x00 (b 0000 0000) = 256MB
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#define GA_SIZE_1MB 0xFF
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#define GA_SIZE_2MB 0xFE
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#define GA_SIZE_4MB 0xFC
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#define GA_SIZE_8MB 0xF8
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#define GA_SIZE_16MB 0xF0
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#define GA_SIZE_32MB 0xE0
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#define GA_SIZE_64MB 0xC0
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#define GA_SIZE_128MB 0x80
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#define GA_SIZE_256MB 0x00
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#define GA_SIZE_COUNT 7
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#define GA_MIN_SIZE (1 * 1024 * 1024)
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#define GA_MAX_SIZE (256 * 1024 * 1024)
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//
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// Define the GART table entry.
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//
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typedef struct _GART_ENTRY_HW {
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ULONG Valid : 1;
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ULONG Reserved : 11;
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ULONG Page : 20;
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} GART_ENTRY_HW, *PGART_ENTRY_HW;
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//
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// Aperture size in MB is equivalent to gart table allocation
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// alignment requirement in KB
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//
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#define VIA_GART_ALIGN(Aperture) ((Aperture) >> 0xA)
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#define VIA_VERIFY_GART_ALIGN(Gart, Aperture) \
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(((Gart) & (VIA_GART_ALIGN((Aperture)) - 1)) == 0)
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//
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// GART Entry states are defined so that all software-only states
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// have the Valid bit clear.
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//
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#define GART_ENTRY_VALID 1 // 001
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#define GART_ENTRY_FREE 0 // 000
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#define GART_ENTRY_WC 2 // 010
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#define GART_ENTRY_UC 4 // 100
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#define GART_ENTRY_RESERVED_WC GART_ENTRY_WC
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#define GART_ENTRY_RESERVED_UC GART_ENTRY_UC
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#define GART_ENTRY_VALID_WC (GART_ENTRY_VALID)
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#define GART_ENTRY_VALID_UC (GART_ENTRY_VALID)
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typedef struct _GART_ENTRY_SW {
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ULONG State : 3;
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ULONG Reserved : 29;
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} GART_ENTRY_SW, *PGART_ENTRY_SW;
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typedef struct _GART_PTE {
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union {
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GART_ENTRY_HW Hard;
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ULONG AsUlong;
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GART_ENTRY_SW Soft;
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};
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} GART_PTE, *PGART_PTE;
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//
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// Define the layout of the hardware registers
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//
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typedef struct _VIA_GART_TLB_CTRL {
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ULONG AGP_ATFGA : 1; // ATFGA = Address Translation for GA Access
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ULONG CPU_ATFGA : 1;
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ULONG PCI2_ATFGA : 1;
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ULONG PCI1_ATFGA : 1;
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ULONG Reserved1 : 3;
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ULONG FlushPageTLB : 1;
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ULONG Reserved2 : 8; // test mode status
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ULONG Reserved3 : 16;
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} VIA_GART_TLB_CTRL, *PVIA_GART_TLB_CTRL;
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typedef struct _VIA_GATT_BASE {
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ULONG TT_NonCache : 1; // Translation Table Noncachable
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ULONG GA_Enable : 1; // Graphics Aperture Enable
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ULONG TLB_Timing : 1;
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ULONG Reserved : 9;
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ULONG GATT_Base : 20;
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} VIA_GATT_BASE, *PVIA_GATT_BASE;
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typedef struct _VREF_REG {
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ULONG Reserved1 : 7;
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ULONG VREF_Control : 1;
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ULONG Reserved2 : 24;
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} VREF_REG, *PVREF_REG;
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typedef struct _AGPMISC_REG {
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ULONG Reserved1 : 18;
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ULONG AGP4X_Support : 1;
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ULONG Reserved2 : 1;
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ULONG FW_Support : 1;
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ULONG AGP4G_Support : 1;
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ULONG Reserved3 : 10;
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} AGPMISC_REG, *PAGPMISC_REG;
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//
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// Define the VIA-specific extension
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//
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typedef struct _AGPVIA_EXTENSION {
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BOOLEAN GlobalEnable;
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BOOLEAN PCIEnable;
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PHYSICAL_ADDRESS ApertureStart; //Aperture Phys Base Address
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ULONG ApertureLength;
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PGART_PTE GartCached;
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PGART_PTE Gart;
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ULONG GartLength;
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PHYSICAL_ADDRESS GartPhysical;
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BOOLEAN Cap_FlushTLB; //TRUE: support Flush TLB
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ULONGLONG SpecialTarget;
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} AGPVIA_EXTENSION, *PAGPVIA_EXTENSION;
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