401 lines
16 KiB
C
401 lines
16 KiB
C
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/*++
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Copyright (c) 1997-2000 Microsoft Corporation
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Module Name:
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data.c
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Abstract:
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Data definitions for discardable/pageable data
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Author:
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Ravisankar Pudipeddi (ravisp) - 1 Feb 1997
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Neil Sandlin (neilsa) June 1 1999
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Environment:
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Kernel mode
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Revision History :
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--*/
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#include "pch.h"
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#ifdef ALLOC_DATA_PRAGMA
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#pragma data_seg ("INIT")
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#endif
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//
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// Beginning of Init Data
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//
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//
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// Global registry values (in pcmcia\\parameters)
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//
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#define PCMCIA_REGISTRY_INTERRUPT_MASK_VALUE L"ForcedInterruptMask"
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#define PCMCIA_REGISTRY_INTERRUPT_FILTER_VALUE L"FilterInterruptMask"
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#define PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_LO_VALUE L"AttributeMemoryLow"
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#define PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_HI_VALUE L"AttributeMemoryHigh"
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#define PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_SIZE_VALUE L"AttributeMemorySize"
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#define PCMCIA_REGISTRY_SOUNDS_ENABLED_VALUE L"SoundsEnabled"
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#define PCMCIA_REGISTRY_POWER_POLICY_VALUE L"PowerPolicy"
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#define PCMCIA_REGISTRY_FORCE_CTLR_DEVICE_WAKE L"ForceControllerDeviceWake"
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#define PCMCIA_REGISTRY_IO_HIGH_VALUE L"IoHigh"
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#define PCMCIA_REGISTRY_IO_LOW_VALUE L"IoLow"
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#define PCMCIA_REGISTRY_READY_DELAY_ITER_VALUE L"ReadyDelayIter"
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#define PCMCIA_REGISTRY_READY_STALL_VALUE L"ReadyStall"
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#define PCMCIA_REGISTRY_USE_POLLED_CSC_VALUE L"ForcePolledMode"
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#define PCMCIA_REGISTRY_CBMODEM_DELAY_VALUE L"CBModemReadyDelay"
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#define PCMCIA_REGISTRY_PCIC_MEMORY_WINDOW_DELAY L"PcicMemoryWindowDelay"
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#define PCMCIA_REGISTRY_PCIC_RESET_WIDTH_DELAY L"PcicResetWidthDelay"
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#define PCMCIA_REGISTRY_PCIC_RESET_SETUP_DELAY L"PcicResetSetupDelay"
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#define PCMCIA_REGISTRY_CB_RESET_WIDTH_DELAY L"CBResetWidthDelay"
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#define PCMCIA_REGISTRY_CB_RESET_SETUP_DELAY L"CBResetSetupDelay"
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#define PCMCIA_REGISTRY_CONTROLLER_POWERUP_DELAY L"ControllerPowerUpDelay"
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#define PCMCIA_REGISTRY_DISABLE_ISA_PCI_ROUTING L"DisableIsaToPciRouting"
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#define PCMCIA_REGISTRY_DEFAULT_ROUTE_R2_TO_ISA L"DefaultRouteToIsa"
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#define PCMCIA_REGISTRY_DISABLE_ACPI_NAMESPACE_CHK L"DisableAcpiNameSpaceCheck"
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#define PCMCIA_REGISTRY_IRQ_ROUTE_PCI_CTLR L"IrqRouteToPciController"
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#define PCMCIA_REGISTRY_IRQ_ROUTE_ISA_CTLR L"IrqRouteToIsaController"
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#define PCMCIA_REGISTRY_IRQ_ROUTE_PCI_LOC L"IrqRouteToPciLocation"
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#define PCMCIA_REGISTRY_IRQ_ROUTE_ISA_LOC L"IrqRouteToIsaLocation"
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#define PCMCIA_REGISTRY_REPORT_MTD0002_AS_ERROR L"ReportMTD0002AsError"
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#define PCMCIA_REGISTRY_DEBUG_MASK L"DebugMask"
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#define PCMCIA_REGISTRY_EVENT_DPC_DELAY L"EventDpcDelay"
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//
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// Table which defines global registry settings
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//
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// RegistryName Internal Variable Default Value
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// ------------ ----------------- -------------
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GLOBAL_REGISTRY_INFORMATION GlobalRegistryInfo[] = {
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#if DBG
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PCMCIA_REGISTRY_DEBUG_MASK, &PcmciaDebugMask, 1,
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#endif
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PCMCIA_REGISTRY_INTERRUPT_MASK_VALUE, &globalOverrideIrqMask, 0,
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PCMCIA_REGISTRY_INTERRUPT_FILTER_VALUE, &globalFilterIrqMask, 0,
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PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_LO_VALUE, &globalAttributeMemoryLow, PCMCIA_DEFAULT_ATTRIBUTE_MEMORY_LOW,
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PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_HI_VALUE, &globalAttributeMemoryHigh, PCMCIA_DEFAULT_ATTRIBUTE_MEMORY_HIGH,
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PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_SIZE_VALUE, &globalAttributeMemorySize, 0,
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PCMCIA_REGISTRY_SOUNDS_ENABLED_VALUE, &initSoundsEnabled, 1,
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PCMCIA_REGISTRY_POWER_POLICY_VALUE, &PcmciaPowerPolicy, 1,
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PCMCIA_REGISTRY_FORCE_CTLR_DEVICE_WAKE, &PcmciaControllerDeviceWake, 0,
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PCMCIA_REGISTRY_IO_HIGH_VALUE, &globalIoHigh, PCMCIA_DEFAULT_IO_HIGH,
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PCMCIA_REGISTRY_IO_LOW_VALUE, &globalIoLow, PCMCIA_DEFAULT_IO_LOW,
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PCMCIA_REGISTRY_READY_DELAY_ITER_VALUE, &globalReadyDelayIter, PCMCIA_DEFAULT_READY_DELAY_ITER,
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PCMCIA_REGISTRY_READY_STALL_VALUE, &globalReadyStall, PCMCIA_DEFAULT_READY_STALL,
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PCMCIA_REGISTRY_USE_POLLED_CSC_VALUE, &initUsePolledCsc, 0,
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PCMCIA_REGISTRY_DISABLE_ISA_PCI_ROUTING, &pcmciaDisableIsaPciRouting, 0,
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PCMCIA_REGISTRY_ISA_IRQ_RESCAN_COMPLETE, &pcmciaIsaIrqRescanComplete, 0,
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PCMCIA_REGISTRY_IRQ_ROUTE_PCI_CTLR, &pcmciaIrqRouteToPciController, 0,
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PCMCIA_REGISTRY_IRQ_ROUTE_ISA_CTLR, &pcmciaIrqRouteToIsaController, 0,
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PCMCIA_REGISTRY_IRQ_ROUTE_PCI_LOC, &pcmciaIrqRouteToPciLocation, 0,
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PCMCIA_REGISTRY_IRQ_ROUTE_ISA_LOC, &pcmciaIrqRouteToIsaLocation, 0,
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PCMCIA_REGISTRY_DISABLE_ACPI_NAMESPACE_CHK, &initDisableAcpiNameSpaceCheck, 0,
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PCMCIA_REGISTRY_DEFAULT_ROUTE_R2_TO_ISA, &initDefaultRouteR2ToIsa, 0,
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PCMCIA_REGISTRY_CBMODEM_DELAY_VALUE, &CBModemReadyDelay, PCMCIA_DEFAULT_CB_MODEM_READY_DELAY,
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PCMCIA_REGISTRY_PCIC_MEMORY_WINDOW_DELAY, &PcicMemoryWindowDelay, PCMCIA_DEFAULT_PCIC_MEMORY_WINDOW_DELAY,
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PCMCIA_REGISTRY_PCIC_RESET_WIDTH_DELAY, &PcicResetWidthDelay, PCMCIA_DEFAULT_PCIC_RESET_WIDTH_DELAY,
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PCMCIA_REGISTRY_PCIC_RESET_SETUP_DELAY, &PcicResetSetupDelay, PCMCIA_DEFAULT_PCIC_RESET_SETUP_DELAY,
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PCMCIA_REGISTRY_CB_RESET_WIDTH_DELAY, &CBResetWidthDelay, PCMCIA_DEFAULT_CB_RESET_WIDTH_DELAY,
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PCMCIA_REGISTRY_CB_RESET_SETUP_DELAY, &CBResetSetupDelay, PCMCIA_DEFAULT_CB_RESET_SETUP_DELAY,
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PCMCIA_REGISTRY_CONTROLLER_POWERUP_DELAY, &ControllerPowerUpDelay, PCMCIA_DEFAULT_CONTROLLER_POWERUP_DELAY,
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PCMCIA_REGISTRY_EVENT_DPC_DELAY, &EventDpcDelay, PCMCIA_DEFAULT_EVENT_DPC_DELAY,
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PCMCIA_REGISTRY_REPORT_MTD0002_AS_ERROR, &pcmciaReportMTD0002AsError, 1
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};
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ULONG GlobalInfoCount = sizeof(GlobalRegistryInfo) / sizeof(GLOBAL_REGISTRY_INFORMATION);
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ULONG initSoundsEnabled;
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ULONG initUsePolledCsc;
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ULONG initDisableAcpiNameSpaceCheck;
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ULONG initDefaultRouteR2ToIsa;
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//
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// end of Init Data
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//
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#ifdef ALLOC_DATA_PRAGMA
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#pragma data_seg ()
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#endif
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#ifdef ALLOC_DATA_PRAGMA
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#pragma data_seg()
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#endif
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//
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// Non-Paged global variables
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//
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//
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// List of FDOs managed by this driver
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//
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PDEVICE_OBJECT FdoList;
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//
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// GLobal Flags
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//
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ULONG PcmciaGlobalFlags = 0;
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//
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// Event used by PcmciaWait
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//
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KEVENT PcmciaDelayTimerEvent;
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//
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// Objects used by PcmciaPlayTone
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//
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PPCMCIA_SOUND_EVENT PcmciaToneList;
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KTIMER PcmciaToneTimer;
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KDPC PcmciaToneDpc;
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KSPIN_LOCK PcmciaToneLock;
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KSPIN_LOCK PcmciaGlobalLock;
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PPCMCIA_NTDETECT_DATA pNtDetectDataList = NULL;
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ULONG PcicStallPower = PWRON_DELAY;
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//
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// Various values set by PcmciaLoadGlobalRegistryValues
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//
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ULONG PcicMemoryWindowDelay;
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ULONG PcicResetWidthDelay;
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ULONG PcicResetSetupDelay;
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ULONG CBResetWidthDelay;
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ULONG CBResetSetupDelay;
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ULONG CBModemReadyDelay;
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ULONG ControllerPowerUpDelay;
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ULONG EventDpcDelay;
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ULONG PcmciaPowerPolicy;
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LONG PcmciaControllerDeviceWake;
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ULONG globalOverrideIrqMask;
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ULONG globalFilterIrqMask;
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ULONG globalIoLow;
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ULONG globalIoHigh;
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ULONG globalReadyDelayIter;
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ULONG globalReadyStall;
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ULONG globalAttributeMemoryLow;
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ULONG globalAttributeMemoryHigh;
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ULONG globalAttributeMemorySize;
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ULONG pcmciaDisableIsaPciRouting;
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ULONG pcmciaIsaIrqRescanComplete;
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ULONG pcmciaIrqRouteToPciController;
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ULONG pcmciaIrqRouteToIsaController;
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ULONG pcmciaIrqRouteToPciLocation;
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ULONG pcmciaIrqRouteToIsaLocation;
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ULONG pcmciaReportMTD0002AsError;
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#if DBG
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ULONG PcmciaDebugMask;
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#endif
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#ifdef ALLOC_DATA_PRAGMA
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#pragma data_seg("PAGE")
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#endif
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//
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// Paged const tables
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//
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const
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PCI_CONTROLLER_INFORMATION PciControllerInformation[] = {
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// Vendor id Device Id Controller type
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// -------------------------------------------------------------------------------
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PCI_CIRRUSLOGIC_VENDORID, PCI_CLPD6729_DEVICEID, PcmciaCLPD6729,
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PCI_CIRRUSLOGIC_VENDORID, PCI_CLPD6832_DEVICEID, PcmciaCLPD6832,
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PCI_CIRRUSLOGIC_VENDORID, PCI_CLPD6834_DEVICEID, PcmciaCLPD6834,
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PCI_TI_VENDORID, PCI_TI1031_DEVICEID, PcmciaTI1031,
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PCI_TI_VENDORID, PCI_TI1130_DEVICEID, PcmciaTI1130,
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PCI_TI_VENDORID, PCI_TI1131_DEVICEID, PcmciaTI1131,
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PCI_TI_VENDORID, PCI_TI1250_DEVICEID, PcmciaTI1250,
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PCI_TI_VENDORID, PCI_TI1220_DEVICEID, PcmciaTI1220,
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PCI_TI_VENDORID, PCI_TI1251B_DEVICEID, PcmciaTI1251B,
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PCI_TI_VENDORID, PCI_TI1450_DEVICEID, PcmciaTI1450,
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PCI_TOSHIBA_VENDORID, PCI_TOPIC95_DEVICEID, PcmciaTopic95,
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PCI_RICOH_VENDORID, PCI_RL5C465_DEVICEID, PcmciaRL5C465,
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PCI_RICOH_VENDORID, PCI_RL5C466_DEVICEID, PcmciaRL5C466,
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PCI_RICOH_VENDORID, PCI_RL5C475_DEVICEID, PcmciaRL5C475,
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PCI_RICOH_VENDORID, PCI_RL5C476_DEVICEID, PcmciaRL5C476,
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PCI_RICOH_VENDORID, PCI_RL5C478_DEVICEID, PcmciaRL5C478,
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PCI_DATABOOK_VENDORID, PCI_DB87144_DEVICEID, PcmciaDB87144,
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PCI_OPTI_VENDORID, PCI_OPTI82C814_DEVICEID, PcmciaOpti82C814,
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PCI_OPTI_VENDORID, PCI_OPTI82C824_DEVICEID, PcmciaOpti82C824,
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PCI_TRIDENT_VENDORID, PCI_TRID82C194_DEVICEID, PcmciaTrid82C194,
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PCI_NEC_VENDORID, PCI_NEC66369_DEVICEID, PcmciaNEC66369,
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// --------------------------------------------------------------------
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// Additional database entries go above this line
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//
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PCI_INVALID_VENDORID, 0, 0,
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};
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const
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PCI_VENDOR_INFORMATION PciVendorInformation[] = {
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PCI_TI_VENDORID, PcmciaTI,
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PCI_TOSHIBA_VENDORID, PcmciaTopic,
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PCI_RICOH_VENDORID, PcmciaRicoh,
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PCI_O2MICRO_VENDORID, PcmciaO2Micro,
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PCI_NEC_VENDORID, PcmciaNEC,
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PCI_DATABOOK_VENDORID, PcmciaDatabook,
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PCI_OPTI_VENDORID, PcmciaOpti,
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PCI_TRIDENT_VENDORID, PcmciaTrid,
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PCI_INVALID_VENDORID, 0
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};
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const
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DEVICE_DISPATCH_TABLE DeviceDispatchTable[] = {
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{PcmciaIntelCompatible, NULL, PcicSetPower, NULL, NULL, NULL},
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{PcmciaPciPcmciaBridge, NULL, PcicSetPower, NULL, NULL, NULL},
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{PcmciaElcController, NULL, PcicSetPower, NULL, NULL, NULL},
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{PcmciaCardBusCompatible, NULL, CBSetPower, NULL, NULL, CBSetWindowPage},
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{PcmciaDatabook, NULL, TcicSetPower, NULL, NULL, NULL},
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{PcmciaTI, TIInitialize, CBSetPower, NULL, TISetZV, TISetWindowPage},
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{PcmciaCirrusLogic,CLInitialize, CLSetPower, NULL, CLSetZV, CBSetWindowPage},
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{PcmciaTopic, TopicInitialize, TopicSetPower, TopicSetAudio, TopicSetZV, CBSetWindowPage},
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{PcmciaRicoh, RicohInitialize, CBSetPower, NULL, RicohSetZV, CBSetWindowPage},
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{PcmciaDatabookCB, DBInitialize, CBSetPower, NULL, DBSetZV, CBSetWindowPage},
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{PcmciaOpti, OptiInitialize, OptiSetPower, NULL, OptiSetZV, NULL},
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{PcmciaTrid, NULL, CBSetPower, NULL, NULL, NULL},
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{PcmciaO2Micro, O2MInitialize, O2MSetPower, NULL, O2MSetZV, CBSetWindowPage},
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{PcmciaNEC_98, NULL, PcicSetPower, NULL, NULL, NULL},
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{PcmciaNEC, NULL, CBSetPower, NULL, NULL, NULL},
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//------------------------------------------------------------------
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// Additional dispatch table entries go above this line
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//
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{PcmciaInvalidControllerClass, NULL, NULL, NULL, NULL}
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};
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const
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PCMCIA_ID_ENTRY PcmciaAdapterHardwareIds[] = {
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PcmciaIntelCompatible, "*PNP0E00",
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PcmciaElcController, "*PNP0E02",
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PcmciaDatabook, "*DBK0000",
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PcmciaCLPD6729, "*PNP0E01",
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PcmciaNEC98, "*nEC1E01",
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PcmciaNEC98102, "*nEC8091",
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PcmciaInvalidControllerType, 0
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};
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const
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PCMCIA_REGISTER_INIT PcicRegisterInitTable[] = {
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PCIC_INTERRUPT, IGC_PCCARD_RESETLO,
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PCIC_CARD_CHANGE, 0x00,
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PCIC_CARD_INT_CONFIG, 0x00,
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PCIC_ADD_WIN_ENA, 0x00,
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PCIC_IO_CONTROL, 0x00,
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//
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// Init the 2 I/O windows
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//
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PCIC_IO_ADD0_STRT_L, 0x00,
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PCIC_IO_ADD0_STRT_H, 0x00,
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PCIC_IO_ADD0_STOP_L, 0x00,
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PCIC_IO_ADD0_STOP_H, 0x00,
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PCIC_IO_ADD1_STRT_L, 0x00,
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PCIC_IO_ADD1_STRT_H, 0x00,
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PCIC_IO_ADD1_STOP_L, 0x00,
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PCIC_IO_ADD1_STOP_H, 0x00,
|
||
|
|
//
|
||
|
|
// Init all 5 memory windows
|
||
|
|
//
|
||
|
|
PCIC_MEM_ADD0_STRT_L, 0xFF,
|
||
|
|
PCIC_MEM_ADD0_STRT_H, 0x0F,
|
||
|
|
PCIC_MEM_ADD0_STOP_L, 0xFF,
|
||
|
|
PCIC_MEM_ADD0_STOP_H, 0x0F,
|
||
|
|
PCIC_CRDMEM_OFF_ADD0_L, 0x00,
|
||
|
|
PCIC_CRDMEM_OFF_ADD0_H, 0x00,
|
||
|
|
|
||
|
|
PCIC_MEM_ADD1_STRT_L, 0xFF,
|
||
|
|
PCIC_MEM_ADD1_STRT_H, 0x0F,
|
||
|
|
PCIC_MEM_ADD1_STOP_L, 0xFF,
|
||
|
|
PCIC_MEM_ADD1_STOP_H, 0x0F,
|
||
|
|
PCIC_CRDMEM_OFF_ADD1_L, 0x00,
|
||
|
|
PCIC_CRDMEM_OFF_ADD1_H, 0x00,
|
||
|
|
|
||
|
|
PCIC_MEM_ADD2_STRT_L, 0xFF,
|
||
|
|
PCIC_MEM_ADD2_STRT_H, 0x0F,
|
||
|
|
PCIC_MEM_ADD2_STOP_L, 0xFF,
|
||
|
|
PCIC_MEM_ADD2_STOP_H, 0x0F,
|
||
|
|
PCIC_CRDMEM_OFF_ADD2_L, 0x00,
|
||
|
|
PCIC_CRDMEM_OFF_ADD2_H, 0x00,
|
||
|
|
|
||
|
|
PCIC_MEM_ADD3_STRT_L, 0xFF,
|
||
|
|
PCIC_MEM_ADD3_STRT_H, 0x0F,
|
||
|
|
PCIC_MEM_ADD3_STOP_L, 0xFF,
|
||
|
|
PCIC_MEM_ADD3_STOP_H, 0x0F,
|
||
|
|
PCIC_CRDMEM_OFF_ADD3_L, 0x00,
|
||
|
|
PCIC_CRDMEM_OFF_ADD3_H, 0x00,
|
||
|
|
|
||
|
|
PCIC_MEM_ADD4_STRT_L, 0xFF,
|
||
|
|
PCIC_MEM_ADD4_STRT_H, 0x0F,
|
||
|
|
PCIC_MEM_ADD4_STOP_L, 0xFF,
|
||
|
|
PCIC_MEM_ADD4_STOP_H, 0x0F,
|
||
|
|
PCIC_CRDMEM_OFF_ADD4_L, 0x00,
|
||
|
|
PCIC_CRDMEM_OFF_ADD4_H, 0x00,
|
||
|
|
//
|
||
|
|
// Any other registers go here
|
||
|
|
//
|
||
|
|
0xFFFFFFFF, 0x00
|
||
|
|
};
|
||
|
|
|
||
|
|
#ifdef ALLOC_DATA_PRAGMA
|
||
|
|
#pragma data_seg()
|
||
|
|
#endif
|
||
|
|
//
|
||
|
|
// Non-paged const tables
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
// This should be non-pageable since it is referenced by the
|
||
|
|
// Power management code - most of which runs at raised IRQL
|
||
|
|
// This represents the default set of registers that need to be
|
||
|
|
// saved/restored on a cardbus controller power-down/power-up
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
// Register context for the pcmcia controller
|
||
|
|
//
|
||
|
|
const
|
||
|
|
PCMCIA_CONTEXT_RANGE DefaultPciContextSave[] = {
|
||
|
|
CFGSPACE_BRIDGE_CTRL, 2,
|
||
|
|
CFGSPACE_LEGACY_MODE_BASE_ADDR, 4,
|
||
|
|
// CFGSPACE_CB_LATENCY_TIMER, 1,
|
||
|
|
0, 0
|
||
|
|
};
|
||
|
|
|
||
|
|
//
|
||
|
|
// cardbus socket registers required to be saved
|
||
|
|
//
|
||
|
|
const
|
||
|
|
PCMCIA_CONTEXT_RANGE DefaultCardbusContextSave[] = {
|
||
|
|
0, 0
|
||
|
|
};
|
||
|
|
|
||
|
|
//
|
||
|
|
// cardbus socket registers excluded from context save
|
||
|
|
//
|
||
|
|
const
|
||
|
|
PCMCIA_CONTEXT_RANGE ExcludeCardbusContextRange[] = {
|
||
|
|
CARDBUS_SOCKET_EVENT_REG, 0x4,
|
||
|
|
CARDBUS_SOCKET_PRESENT_STATE_REG, 0xc,
|
||
|
|
0, 0
|
||
|
|
};
|
||
|
|
|
||
|
|
//
|
||
|
|
// The following table defines any devices that need special
|
||
|
|
// attention during configuration. Note that values of 0xffff
|
||
|
|
// mean "don't care". The table is scanned until a match is made
|
||
|
|
// for the current device.
|
||
|
|
//
|
||
|
|
// Values are:
|
||
|
|
// validentry, devicetype, manufacturer, code, crc, configdelay1, configdelay2, configdelay3, configflags
|
||
|
|
//
|
||
|
|
// delay values are in milliseconds
|
||
|
|
//
|
||
|
|
const
|
||
|
|
PCMCIA_DEVICE_CONFIG_PARAMS DeviceConfigParams[] = {
|
||
|
|
1, PCCARD_TYPE_MODEM, 0x109, 0x505, 0xD293, 3100, 900, 0, CONFIG_WORKER_APPLY_MODEM_HACK, // motorola BitSurfr 56k
|
||
|
|
1, PCCARD_TYPE_MODEM, 0xffff, 0xffff, 0xffff, 0, 1800, 0, 0, // any other modem
|
||
|
|
1, PCCARD_TYPE_ATA, 0xffff, 0xffff, 0xffff, 0, 0, 2000, 0, // any ata device
|
||
|
|
0
|
||
|
|
};
|