173 lines
4.1 KiB
ArmAsm
173 lines
4.1 KiB
ArmAsm
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// string.s: function to concatenate 2 strings
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// Copyright (c) 2000, Intel Corporation
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// All rights reserved.
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//
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// WARRANTY DISCLAIMER
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Intel Corporation is the author of this code, and requests that all
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// problem reports or change requests be submitted to it directly at
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// http://developer.intel.com/opensource.
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//
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.file "string.s"
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.section .text
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// -- Begin strcat
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.proc strcat#
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.global strcat#
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.align 32
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strcat:
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{ .mib
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alloc r14=ar.pfs,2,6,0,8 //8 rotating registers, 7 locals
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mov r11=pr //Save predicate register file
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brp.loop.imp .bs1len, .bws1 // Put loop backedge target in TAR
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}
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// Setup for doing software pipelined loops
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{ .mib
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mov r9=r33
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mov pr.rot=0x30000 // p16=p17=1
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nop.b 0
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};;
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{ .mib
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mov r14=r32
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mov ar.ec=0
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nop.b 0
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} { .mib // Extra bundle to align bs1len.
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mov r8=r32
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nop.i 0
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brp.loop.imp .bcat, .bwcat ;; // Put loop backedge target in TAR
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}
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.bs1len:
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{ .mii
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ld1.s r37=[r14],1 // *s (r37,r38,r39)
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nop.i 0
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(p19) chk.s r39,.natfault1_0 //
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}
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.bws1:
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{ .mfb
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(p19) cmp4.ne p17,p0=r39,r0 // *s==0 (p16,p17,p18)
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nop.f 0
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(p17) br.wtop.dptk .bs1len ;; //
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}
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//
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// Now concatenate s2 into the end of s1
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//
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{ .mib
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add r14=-3,r14 // Since ld1.s is 2 stages ahead
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dep r15=1,r0,32,32 // rb = 0xffffffff00000000
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clrrrb ;;
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} { .mii
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// Setup for doing software pipelined loops
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or r32=r14,r9
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mov pr.rot=0x30000 ;; // p16=p17=1
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and r32=3,r32 ;;
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} { .mib
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cmp4.ne p10,p0=r32,r0
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mov ar.ec=0
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(p10) br.spnt .b_notaligned ;;
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}
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.bcat:
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{ .mii
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ld4.s r32=[r9],4 // *s1 (r32,r33,r34)
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(p18) chk.s r33,.natfault2_0 //
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(p18) pcmp1.eq r16=r33,r15 ;; // r16 !=0 only if a zero byte is found
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}
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.bwcat:
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{ .mib
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(p19) st4 [r14]=r34,4 // *s2=*s1
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(p18) cmp4.eq p17,p0=r16,r0 // zero byte found?
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(p17) br.wtop.dptk .bcat ;; //
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}
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{ .mfi
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nop.m 0
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nop.f 0
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czx1.r r16 = r33
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} ;;
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{ .mfi
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cmp.leu p2, p0 = 2, r16
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nop.f 0
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shr.u r35 = r33, 8
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}
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{ .mfi
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cmp.eq p4, p0 = 3, r16
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nop.f 0
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cmp.ne p5, p0 = r0, r16
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} ;;
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{ .mfi
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(p5)st1 [r14] = r33, 1
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nop.f 0
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shr.u r36 = r33, 16
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};;
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{ .mfi
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(p2)st1 [r14] = r35,1
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nop.f 0
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nop.i 0
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} ;;
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{ .mfi
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(p4)st1 [r14] = r36,1
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nop.f 0
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nop.i 0
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};;
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{ .mib
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(p0) st1 [r14] = r0
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nop.i 0
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clrrrb
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} ;;
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{ .mib
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nop.m 0
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mov pr=r11,0x1003e
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br.ret.sptk.many b0 ;;
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}
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.b_notaligned:
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{ .mmi
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ld1 r32=[r9],1 ;; // 2 cycle load causes 1 cycle stall
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st1 [r14]=r32,1 // 3 cycles between st1 to avoid flush
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cmp4.ne.unc p7,p0=r32,r0 ;; // Extra stop bit to force 3 cycles
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} { .mib
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nop.m 0
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nop.i 0
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(p7) br.cond.dptk .b_notaligned ;;
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} { .mib
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nop.m 0
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mov pr=r11,0x1003e
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br.ret.sptk.many b0 ;;
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}
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.natfault1_0:
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{ .mmi
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add r39=-3,r14 ;;
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ld1 r39=[r39] // Redo the load
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nop.i 0
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} { .mib
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nop.m 0
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nop.i 0
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br.sptk .bws1 ;;
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}
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.natfault2_0:
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{ .mmi
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add r33=-8,r9 ;;
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ld4 r33=[r33] // *s1 (r32,r33,r34)
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nop.i 0;;
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} { .mib
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nop.m 0
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(p18) pcmp1.eq r16=r33,r15 // r16 !=0 only if a zero byte is found
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br.sptk .bwcat ;;
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}
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_2_1_2auto_size == 0x0
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// -- End strcat
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.endp strcat#
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// mark_proc_addr_taken strcat;
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// End
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