721 lines
17 KiB
NASM
721 lines
17 KiB
NASM
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title "Sleep Handlers"
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;++
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;
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; Copyright (c) 1989 Microsoft Corporation
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;
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; Module Name:
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;
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; ixsstate.asm
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;
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; Abstract:
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;
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; This module implements the code for putting the machine to
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; sleep.
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;
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; Author:
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;
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; Jake Oshins (jakeo) March 13, 1997
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;
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; Environment:
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;
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; Kernel mode only.
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;
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; Revision History:
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;
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;--
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.386p
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.xlist
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include hal386.inc
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include callconv.inc ; calling convention macros
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include i386\ix8259.inc
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include i386\kimacro.inc
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include mac386.inc
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include i386\ixcmos.inc
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include xxacpi.h
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include i386\ixslpctx.inc
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.list
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EXTRNP _HalpAcpiPreSleep ,1
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EXTRNP _HalpAcpiPostSleep ,1
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EXTRNP _HalpPostSleepMP, 2
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EXTRNP _HalpReenableAcpi, 0
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EXTRNP _StartPx_BuildRealModeStart,1
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EXTRNP KfLowerIrql, 1,,FASTCALL
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EXTRNP _KeGetCurrentIrql,0
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EXTRNP _HalpSaveProcessorStateAndWait,2
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EXTRNP _KeStallExecutionProcessor, 1
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EXTRNP _HalpClearSlpSmiStsInICH,0
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extrn _HalpLowStubPhysicalAddress:DWORD
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extrn _KeSaveStateForHibernate:proc
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extrn _HalpFixedAcpiDescTable:DWORD
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extrn _HalpWakeVector:DWORD
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extrn _HalpTiledCr3Addresses:DWORD
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extrn _HalpVirtAddrForFlush:DWORD
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extrn _HalpPteForFlush:DWORD
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extrn _HalpHiberProcState:DWORD
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extrn _HalpBroken440BX:byte
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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ALIGN dword
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public HalpSleepSync
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HalpSleepSync dd 0
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public HalpBarrier
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HalpBarrier dd 0
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_DATA ends
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PAGELK SEGMENT DWORD PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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page ,132
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subttl "Sleep Handlers"
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; VOID
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; FASTCALL
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; HalpAcpiFlushCache(
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; VOID
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; )
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; /*++
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;
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; Routine Description:
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;
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; This is called to flush everything from the caches.
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;
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; Arguments:
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;
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; none
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;
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; Return Value:
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;
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; none
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;
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; --*/
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;
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; eax - offset within a page
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; ebx - stride size
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; ecx - address of PTE we are manipulating
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; edi - Physical Address of page
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; esi - Virtual Address of page used for flush
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; ebp - Flush Limit
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;
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FlushBase equ 100000h
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PageLength equ 4096
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PteValid equ 1
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PteWrite equ 2
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PteAccessed equ 20h
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PteDirty equ 40h
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PteBits equ (PteValid or PteWrite)
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cPublicFastCall HalpAcpiFlushCache, 0
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cPublicFpo 0, 0
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mov eax, [FADT_FLAGS]
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test eax, WBINVD_SUPPORTED or WBINVD_FLUSH
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jz short hafc10
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.586p
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wbinvd
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fstRET HalpAcpiFlushCache
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hafc10:
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push ebp
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push ebx
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push esi
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push edi
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movzx eax, word ptr [FLUSH_STRIDE]
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mov ebx, eax ; save the stride size
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movzx ecx, word ptr [FLUSH_SIZE]
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mul ecx
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add eax, FlushBase
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mov ebp, eax ; ebp <- ending physical address
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;
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; Iterate across all cache lines
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;
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mov edi, FlushBase ; start at 1MB, physical
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mov esi, [_HalpVirtAddrForFlush]
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mov ecx, [_HalpPteForFlush]
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hafc20:
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; put the right physical page into the PTE
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mov edx, PteBits ; mask off the page
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or edx, edi
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mov [ecx], edx
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invlpg [esi]
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add edi, PageLength ; next physical page
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xor eax, eax
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; flush a cache line
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hafc30: mov edx, [esi][eax]
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add eax, ebx
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cmp eax, PageLength
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jl short hafc30
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cmp edi, ebp
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jl short hafc20
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pop edi
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pop esi
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pop ebx
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pop ebp
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.386p
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fstRET HalpAcpiFlushCache
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fstENDP HalpAcpiFlushCache
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;++
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; UCHAR
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; FASTCALL
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; HalpSetup440BXWorkaround(
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; )
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;
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; Routine Description:
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;
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; This function provides part of the workaround for
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; broken 440BX chips.
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;
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; Arguments:
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;
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; none
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;
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; Return Value:
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;
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; the previous contents of 440BX DRAM Control Register (57h)
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;
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;--
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cPublicFastCall HalpSetup440BXWorkaround, 0
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cPublicFpo 0,0
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mov dx, 0cf8h
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mov eax, 80000054h
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out dx, eax
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mov dx, 0cffh
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in al, dx
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mov cl, al
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or al, 7
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out dx, al
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push ecx
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stdCall _KeStallExecutionProcessor <15>
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pop ecx
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mov dx, 0cf8h
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mov eax, 80000054h
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out dx, eax
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mov dx, 0cffh
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in al, dx
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and al, 0f8h
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out dx, al
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movzx eax, cl
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fstRET HalpSetup440BXWorkaround
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fstENDP HalpSetup440BXWorkaround
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;++
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; VOID
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; FASTCALL
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; HalpComplete440BXWorkaround(
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; UCHAR DramControl
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; )
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;
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; Routine Description:
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;
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; This function provides the other part of the workaround for
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; broken 440BX chips.
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;
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; Arguments:
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;
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; the previous contents of 440BX DRAM Control Register (57h)
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;
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; Return Value:
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;
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; none
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;
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;--
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cPublicFastCall HalpComplete440BXWorkaround, 1
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cPublicFpo 0,0
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mov dx, 0cf8h
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mov eax, 80000054h
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out dx, eax
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mov dx, 0cffh
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mov al, cl
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out dx, al
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fstRET HalpComplete440BXWorkaround
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fstENDP HalpComplete440BXWorkaround
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; NTSTATUS
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; HaliAcpiSleep(
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; IN PVOID Context,
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; IN PENTER_STATE_SYSTEM_HANDLER SystemHandler OPTIONAL,
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; IN PVOID SystemContext,
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; IN LONG NumberProcessors,
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; IN volatile PLONG Number
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; )
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; /*++
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;
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; Routine Description:
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;
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; This is called by the Policy Manager to enter Sx.
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;
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; Arguments:
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;
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; Context - unused
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;
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; NumberProcessors - currently unused
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;
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; Number - currently unused
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;
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; Return Value:
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;
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; none
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;
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; --*/
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Context equ [ebp+8]
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SysHandler equ [ebp+12]
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SysContext equ [ebp+16]
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NumberProc equ [ebp+20]
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Barrier equ [ebp+24]
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Pm1aEvt equ [ebp-4]
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Pm1bEvt equ [ebp-8]
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Status equ [ebp-12]
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SlpTypA equ [ebp-14]
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SlpTypB equ [ebp-16]
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ThisProc equ [ebp-20]
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OldIrql equ [ebp-24]
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PrevDRAM equ [ebp-28]
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FrameSize equ 28
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cPublicProc _HaliAcpiSleep, 5
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cPublicFpo 5, 4
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push ebp
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mov ebp, esp
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sub esp, FrameSize
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push ebx
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push esi
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push edi
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pushfd
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cli
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mov edi, HalpSleepSync ; Get current sleep sync value
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xor eax, eax
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mov Status, eax
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;
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; Get current IRQL
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;
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stdCall _KeGetCurrentIrql
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mov OldIrql, eax
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;
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; Send all
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;
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mov al, PCR[PcNumber]
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or al, al ; Is this processor 0?
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jnz has_wait ; if not, set it waiting
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mov HalpBarrier, 0 ; init Barrier, processor 0 does it
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;
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; Make sure the other processors have saved their
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; state and begun to spin.
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;
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lock inc [HalpSleepSync] ; account for this proc
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has1: YIELD
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mov eax, [HalpSleepSync]
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cmp eax, NumberProc
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jnz short has1
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;
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; Take care of chores (RTC, interrupt controller, etc.)
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stdCall _HalpAcpiPreSleep, <Context>
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or al, al ; check for failure
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jz has_slept ; if FALSE, then don't sleep at all
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;
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; If we will be losing processor state, save it
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;
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mov eax, Context
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test eax, SLEEP_STATE_FIRMWARE_RESTART shl CONTEXT_FLAG_SHIFT
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jz short has2
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lea eax, haswake
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stdCall _HalpSetupRealModeResume, <eax>
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;
|
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; Record the values in the SLP_TYP registers
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;
|
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has2:
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mov edx, [PM1a_CNT]
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in ax, dx
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mov SlpTypA, ax
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mov edx, [PM1b_CNT]
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or edx, edx
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jz short has5
|
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in ax, dx
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mov SlpTypB, ax
|
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|
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has5:
|
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;
|
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|
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; The hal has all of it's state saved into ram and is ready
|
||
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; for the power down. If there's a system state handler give
|
||
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; it a shot
|
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;
|
||
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|
||
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mov eax, SysHandler
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or eax, eax
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jz short has10
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|
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mov ecx, SysContext
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push ecx
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call eax ; Call the system state handler
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mov Status, eax
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test eax, eax
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jnz has_s4_wake ; If not success, exit
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||
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has10:
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mov esi, Context
|
||
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mov edx, [PM1a_EVT]
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||
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mov ecx, [PM1b_EVT]
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or ecx, ecx
|
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jnz short has20
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||
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mov ecx, edx
|
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has20:
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mov Pm1aEvt, ecx
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mov Pm1bEvt, edx ; save PM1a_EVT & PM1b_EVT address
|
||
|
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|
||
|
|
;
|
||
|
|
; Reset WAK_STS
|
||
|
|
;
|
||
|
|
|
||
|
|
mov eax, WAK_STS
|
||
|
|
out dx, ax ; clear PM1a WAK_STS
|
||
|
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mov edx, ecx
|
||
|
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out dx, ax ; clear PM1b WAK_STS
|
||
|
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|
||
|
|
;
|
||
|
|
; Flush the caches if necessary
|
||
|
|
;
|
||
|
|
mov eax, SLEEP_STATE_FLUSH_CACHE shl CONTEXT_FLAG_SHIFT
|
||
|
|
test eax, esi
|
||
|
|
jz short @f
|
||
|
|
fstCall HalpAcpiFlushCache
|
||
|
|
@@:
|
||
|
|
;
|
||
|
|
; Work around 440BX bug. Criteria is that we have one of
|
||
|
|
; the broken BX parts and we are not hibernating, which
|
||
|
|
; we know because the SysHandler is 0.
|
||
|
|
;
|
||
|
|
|
||
|
|
mov eax, SysHandler
|
||
|
|
.if (_HalpBroken440BX && (eax == 0))
|
||
|
|
fstCall HalpSetup440BXWorkaround
|
||
|
|
movzx eax, al
|
||
|
|
mov PrevDRAM, eax
|
||
|
|
.endif
|
||
|
|
|
||
|
|
;
|
||
|
|
; Issue SLP commands to PM1a_CNT and PM1b_CNT
|
||
|
|
;
|
||
|
|
|
||
|
|
mov edx, [PM1a_CNT]
|
||
|
|
mov ecx, esi
|
||
|
|
and ecx, 0fh ; nibble 0 is 1a sleep type
|
||
|
|
shl ecx, SLP_TYP_SHIFT ; put it in position
|
||
|
|
or ecx, SLP_EN ; enable sleep ********
|
||
|
|
|
||
|
|
in ax, dx
|
||
|
|
and ax, CTL_PRESERVE ; preserve some bits
|
||
|
|
or ax, cx
|
||
|
|
out dx, ax
|
||
|
|
|
||
|
|
mov edx, [PM1b_CNT]
|
||
|
|
or edx, edx
|
||
|
|
jz short has30
|
||
|
|
|
||
|
|
mov ecx, esi
|
||
|
|
and ecx, 0f0h ; nibble 1 is 1b sleep type
|
||
|
|
shl ecx, (SLP_TYP_SHIFT-4) ; put it in position
|
||
|
|
or ecx, SLP_EN ; enable sleep *********
|
||
|
|
|
||
|
|
in ax, dx
|
||
|
|
and ax, CTL_PRESERVE ; preserve some bits
|
||
|
|
or ax, cx
|
||
|
|
out dx, ax
|
||
|
|
|
||
|
|
has30:
|
||
|
|
;
|
||
|
|
; Wait for sleep to be over
|
||
|
|
;
|
||
|
|
|
||
|
|
mov ecx, Pm1bEvt
|
||
|
|
mov edx, Pm1aEvt ; retrieve PM1_EVT & PM1b_EVT
|
||
|
|
|
||
|
|
has40: in ax, dx
|
||
|
|
test ax, WAK_STS
|
||
|
|
xchg edx, ecx
|
||
|
|
jz short has40
|
||
|
|
|
||
|
|
;
|
||
|
|
; Finish 440BX workaround
|
||
|
|
;
|
||
|
|
|
||
|
|
mov eax, SysHandler
|
||
|
|
.if (_HalpBroken440BX && (eax == 0))
|
||
|
|
mov ecx, PrevDRAM
|
||
|
|
fstCall HalpComplete440BXWorkaround
|
||
|
|
.endif
|
||
|
|
|
||
|
|
;
|
||
|
|
; Invalidate the processor cache so that any stray gamma
|
||
|
|
; rays (I'm serious) that may have flipped cache bits
|
||
|
|
; while in S1 will be ignored.
|
||
|
|
;
|
||
|
|
; Honestly. Intel asked for this. I'm serious.
|
||
|
|
;
|
||
|
|
;.586
|
||
|
|
; invd
|
||
|
|
;.386
|
||
|
|
|
||
|
|
haswake:
|
||
|
|
;
|
||
|
|
; Hack around ICH2/ASUS BIOS.
|
||
|
|
;
|
||
|
|
|
||
|
|
stdCall _HalpClearSlpSmiStsInICH
|
||
|
|
|
||
|
|
;
|
||
|
|
; Restore the SLP_TYP registers. (So that embedded controllers
|
||
|
|
; and BIOSes can be sure that we think the machine is awake.)
|
||
|
|
;
|
||
|
|
mov edx, [PM1a_CNT]
|
||
|
|
mov ax, SlpTypA
|
||
|
|
out dx, ax
|
||
|
|
|
||
|
|
mov edx, [PM1b_CNT]
|
||
|
|
or edx, edx
|
||
|
|
jz short has60
|
||
|
|
|
||
|
|
mov ax, SlpTypB
|
||
|
|
out dx, ax
|
||
|
|
|
||
|
|
has60:
|
||
|
|
stdCall _HalpAcpiPostSleep, <Context>
|
||
|
|
|
||
|
|
has_slept:
|
||
|
|
;
|
||
|
|
; Notify other processor of completion
|
||
|
|
;
|
||
|
|
|
||
|
|
mov HalpSleepSync, 0
|
||
|
|
jmp short has_90
|
||
|
|
|
||
|
|
has_wait:
|
||
|
|
xor eax, eax
|
||
|
|
mov edx, Context
|
||
|
|
test edx, SLEEP_STATE_OFF shl CONTEXT_FLAG_SHIFT
|
||
|
|
jnz has_wait2 ; if going to S5, don't save context
|
||
|
|
|
||
|
|
mov al, PCR[PcNumber] ; get processor number
|
||
|
|
mov edx, ProcessorStateLength ; get size of proc state
|
||
|
|
mul dx ; generate an index into HalpHiberProcState
|
||
|
|
add eax, _HalpHiberProcState ; add the index to base
|
||
|
|
has_wait2:
|
||
|
|
lea edx, HalpSleepSync
|
||
|
|
stdCall _HalpSaveProcessorStateAndWait <eax, edx>
|
||
|
|
|
||
|
|
;
|
||
|
|
; Wait for next phase
|
||
|
|
;
|
||
|
|
|
||
|
|
|
||
|
|
hasw10: YIELD
|
||
|
|
cmp HalpSleepSync, 0 ; wait for barrier to move
|
||
|
|
jne short hasw10
|
||
|
|
|
||
|
|
;
|
||
|
|
; All phases complete, exit
|
||
|
|
;
|
||
|
|
|
||
|
|
has_90:
|
||
|
|
;
|
||
|
|
; Restore each processor's APIC state.
|
||
|
|
;
|
||
|
|
|
||
|
|
lea eax, HalpBarrier
|
||
|
|
stdCall _HalpPostSleepMP <NumberProc, eax>
|
||
|
|
|
||
|
|
;
|
||
|
|
; Restore caller's IRQL
|
||
|
|
;
|
||
|
|
|
||
|
|
mov ecx, OldIrql
|
||
|
|
fstCall KfLowerIrql
|
||
|
|
|
||
|
|
;
|
||
|
|
; Exit
|
||
|
|
;
|
||
|
|
|
||
|
|
mov HalpSleepSync, 0
|
||
|
|
mov eax, Status
|
||
|
|
popfd
|
||
|
|
pop edi
|
||
|
|
pop esi
|
||
|
|
pop ebx
|
||
|
|
mov esp, ebp
|
||
|
|
pop ebp
|
||
|
|
stdRET _HaliAcpiSleep
|
||
|
|
|
||
|
|
has_s4_wake:
|
||
|
|
stdCall _HalpReenableAcpi
|
||
|
|
jmp haswake
|
||
|
|
|
||
|
|
stdENDP _HaliAcpiSleep
|
||
|
|
|
||
|
|
;++
|
||
|
|
;
|
||
|
|
; BOOLEAN
|
||
|
|
; HalpSetupRealModeResume (
|
||
|
|
; )
|
||
|
|
;
|
||
|
|
; Routine Description:
|
||
|
|
;
|
||
|
|
; This routine is called by the kernel durning kernel initialization
|
||
|
|
; to obtain more processors. It is called until no more processors
|
||
|
|
; are available.
|
||
|
|
;
|
||
|
|
; If another processor exists this function is to initialize it to
|
||
|
|
; the passed in processorstate structure, and return TRUE.
|
||
|
|
;
|
||
|
|
; If another processor does not exists or if the processor fails to
|
||
|
|
; start, then a FALSE is returned.
|
||
|
|
;
|
||
|
|
; Also note that the loader block has been setup for the next processor.
|
||
|
|
; The new processor logical thread number can be obtained from it, if
|
||
|
|
; required.
|
||
|
|
;
|
||
|
|
; In order to use the Startup IPI the real mode startup code must be
|
||
|
|
; page aligned. The MpLowStubPhysicalAddress has always been page
|
||
|
|
; aligned but because the PxParamBlock was placed first in this
|
||
|
|
; segment the real mode code has been something other than page aligned.
|
||
|
|
; This has been changed by making the first entry in the PxParamBlock
|
||
|
|
; a jump instruction to the real mode startup code.
|
||
|
|
;
|
||
|
|
; Arguments:
|
||
|
|
;
|
||
|
|
; WakeupReturnAddress - address that processor should return to
|
||
|
|
; after it has been asleep
|
||
|
|
;
|
||
|
|
; Return Value:
|
||
|
|
;
|
||
|
|
;
|
||
|
|
;--
|
||
|
|
|
||
|
|
WakeupReturnAddress equ dword ptr [ebp + 20]
|
||
|
|
|
||
|
|
;
|
||
|
|
; Local variables
|
||
|
|
;
|
||
|
|
|
||
|
|
PxFrame equ [ebp - size PxParamBlock]
|
||
|
|
LWarmResetVector equ [ebp - size PxParamBlock - 4]
|
||
|
|
LStatusCode equ [ebp - size PxParamBlock - 8]
|
||
|
|
LCmosValue equ [ebp - size PxParamBlock - 12]
|
||
|
|
CallingEbp equ [ebp]
|
||
|
|
CallingEsi equ [ebp + 12]
|
||
|
|
CallingEdi equ [ebp + 8]
|
||
|
|
CallingEbx equ [ebp + 4]
|
||
|
|
CallingEsp equ 24 ; relative to current ebp
|
||
|
|
|
||
|
|
cPublicProc _HalpSetupRealModeResume ,1
|
||
|
|
cPublicFpo 4, 80
|
||
|
|
|
||
|
|
push esi ; Save required registers
|
||
|
|
push edi
|
||
|
|
push ebx
|
||
|
|
|
||
|
|
push ebp ; save ebp
|
||
|
|
mov ebp, esp ; Save Frame
|
||
|
|
sub esp, size PxParamBlock + 12 ; Make room for local vars
|
||
|
|
|
||
|
|
xor eax, eax
|
||
|
|
mov LStatusCode, eax
|
||
|
|
|
||
|
|
;
|
||
|
|
; Fill in the firmware wakeup vector
|
||
|
|
;
|
||
|
|
mov eax, _HalpLowStubPhysicalAddress
|
||
|
|
mov ecx, [_HalpWakeVector]
|
||
|
|
mov [ecx], eax
|
||
|
|
|
||
|
|
;
|
||
|
|
; Save the processor context
|
||
|
|
;
|
||
|
|
|
||
|
|
lea edi, PxFrame.SPx_PB
|
||
|
|
push edi
|
||
|
|
call _KeSaveStateForHibernate ; _cdecl function
|
||
|
|
add esp, 4
|
||
|
|
|
||
|
|
;
|
||
|
|
; Get a CR3 for the starting processor
|
||
|
|
;
|
||
|
|
mov eax, [_HalpTiledCr3Addresses] ; the low 32-bits of processor 0's CR3
|
||
|
|
mov eax, [eax] ; physical address will be here
|
||
|
|
mov PxFrame.SPx_TiledCR3, eax ; Newly contructed CR3
|
||
|
|
|
||
|
|
mov PxFrame.SPx_P0EBP, ebp ; Stack pointer
|
||
|
|
|
||
|
|
lea edi, PxFrame.SPx_PB.PsContextFrame
|
||
|
|
|
||
|
|
mov eax, WakeupReturnAddress
|
||
|
|
mov dword ptr [edi].CsEip, eax ; make a copy of remaining
|
||
|
|
mov eax, CallingEbx ; registers which need
|
||
|
|
mov dword ptr [edi].CsEbx, eax ; loaded
|
||
|
|
mov eax, CallingEsi
|
||
|
|
mov dword ptr [edi].CsEsi, eax
|
||
|
|
mov eax, CallingEdi
|
||
|
|
mov dword ptr [edi].CsEdi, eax
|
||
|
|
mov eax, CallingEbp
|
||
|
|
mov dword ptr [edi].CsEbp, eax
|
||
|
|
mov eax, ebp
|
||
|
|
add eax, CallingEsp
|
||
|
|
mov dword ptr [edi].CsEsp, eax
|
||
|
|
|
||
|
|
lea eax, PxFrame
|
||
|
|
stdCall _StartPx_BuildRealModeStart, <eax>
|
||
|
|
|
||
|
|
snp_exit:
|
||
|
|
mov esp, ebp
|
||
|
|
pop ebp
|
||
|
|
pop ebx
|
||
|
|
pop edi
|
||
|
|
pop esi
|
||
|
|
stdRET _HalpSetupRealModeResume
|
||
|
|
|
||
|
|
stdENDP _HalpSetupRealModeResume
|
||
|
|
|
||
|
|
|
||
|
|
PAGELK ends
|
||
|
|
|
||
|
|
end
|