259 lines
7.6 KiB
PHP
259 lines
7.6 KiB
PHP
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;/*
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;
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; Copyright (c) 1989 Microsoft Corporation
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;
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; Module Name:
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;
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; spmp.inc
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;
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; Abstract:
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;
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; SystemPro MP include file
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;
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; Author:
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;
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;--
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if 0 ; */
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// ---------------------------------------------------
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// C section
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// ---------------------------------------------------
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#ifndef SPMPC_INCLUDE
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#define SPMPC_INCLUDE 1
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//
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// All Values in the C section must match with the assembly.
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//
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#define SMP_SYSPRO1 1 // Original SystemPro and Compatibles
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#define SMP_SYSPRO2 2 // SystemPro XL and ProLiant 2000,4000,4500
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#define SMP_ACER 3 // Acer SystemPro Style
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#define SP_M8259 1 // Each processor has 8259 set
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#define SP_SMPDEVINTS 2 // Distribute device ints amoung all processors
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#define SP_SMPCLOCK 4 // Clock is broadcast to each processor
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#define SECOND_IPI_DISPATCH 24 // Vector offset for second level ipi dispatch
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#endif
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/*
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endif
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; ---------------------------------------------------
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; Assembly section
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; ---------------------------------------------------
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;*****************************
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; Compaq MP defines
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;
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RESET_WO_EOI equ 00ah ; Reset with out EOI
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WarmResetVector equ 467h ; warm reset vector in ROM data segment
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; Multi-Processor Control Register I/O Locations:
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PRODUCT_ID_OFFSET equ 0C80h
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EBC_OFFSET equ 0C84h
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PCR_OFFSET equ 0C6Ah
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PROC_ID_PORT equ 0c70h ; who am I
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; Multi-Processor Control Register Bit Definitions:
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INTDIS equ 080h ; INTDIS bit in Processor control register
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PINT equ 040h ; PINT bit in Processor control register
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ERR387 equ 020h ; 387ERR bit in Processor control register
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FLUSH equ 010h ; flushes the processor's cache
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SLEEP equ 008h ; puts processor in HOLD
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CACHEON equ 004h ; enables cache
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PRES387 equ 002h ; 387PRES bit in Processor control register
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RESET equ 001h ; RESET processor
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;*****************************
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; end of list
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;
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; The kernel leaves some space (64 byte) of the PCR for the HAL to use
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; as it needs. Currently this space is used for some efficiency in
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; some of the MP specific code and is highly implementation
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; dependant.
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;
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PcrE struc
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PcrNumber db 0 ; Processor's number
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PcrPic db 0 ; 1 if processor has an 8259s
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PcrIpiClockTick db 0 ; Emulate a clock tick
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db 0 ; (alignment)
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PcrIpiType dd 0 ; How to handle different IPI implementations
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PcrIpiSecondLevelDispatch dd 0 ; To exit IPI interrupt
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PcrControlPort dw 0 ; Processor's control port
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PcrPerfSkew dd 0 ; Skew to apply to this P perf counter
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PcrE ends
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SECOND_IPI_DISPATCH equ 24 ; Vector offset for second level ipi dispatch
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SWClockTick equ 10h ; Software level of emulated clock tick
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SWCLOCK_LEVEL equ 4 ; Software level of emulated clock tick
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cr equ 0ah
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lf equ 0dh
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SMP_SYSPRO1 equ 1
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SMP_SYSPRO2 equ 2
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SMP_ACER equ 3
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;
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; 8259PerProcessorMode bit mask
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;
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SP_M8259 equ 1 ; Each processor has 8259 set
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SP_SMPDEVINTS equ 2 ; Distribute device ints amoung all processors
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SP_SMPCLOCK equ 4 ; Clock is broadcast to each processor
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;*****************************
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; Compaq SMP defines
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;
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;+++EQU+++ Belize Specific defines (Symmetrical SystemProII).
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;
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; INT/MPx local registers, and their initial value. Registers are offseted
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; by 2 (except INT13-INT14) and there is 15 registers (INT does not have one,
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; it is used for cascade).
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;
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TIME_DELAY equ 0ffffffh
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SMP_MAX_PROCESSORS equ 8 ;BELIZE/PHOENIX supports 8 cpus MAX
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SMP_MPINT0 equ 0cb0h
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SMP_MPINT1 equ 0cb2h
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;SMP_MPINT2 **** DOESNOT EXIST ****
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SMP_MPINT3 equ 0cb4h
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SMP_MPINT4 equ 0cb6h
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SMP_MPINT5 equ 0cb8h
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SMP_MPINT6 equ 0cbah
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SMP_MPINT7 equ 0cbch
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SMP_MPINT8 equ 0cbeh
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SMP_MPINT9 equ 0cc0h
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SMP_MPINT10 equ 0cc2h
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SMP_MPINT11 equ 0cc4h
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SMP_MPINT12 equ 0cc6h
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SMP_MPINT13 equ 0cc8h
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SMP_MPINT14 equ 0ccch
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SMP_MPINT15 equ 0cceh
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SMP_IPI_MASKPORT equ 0cd0h ; IntrMask and IntrPort..DWORD
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SMP_IPI_PROG_INTRPORT equ 0cd3h ; IntrPort
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; IRQ assigned to IPI_LEVEL. It could be any of the above IRQs.
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;
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SMP_IPI_VECTOR equ 13 ; IRQ13 assigned to IPI
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SMP_IPI_MPINTx_PORT equ SMP_MPINT13 ; IRQ13
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; SymmetricalMpMode registers (belize mode).
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;
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SMP_MODE_PORT equ 0c67h ; Global: ModeSelectPort
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SMP_CSR_PORT equ 0c6ah ; Local: ControlStatusRegPort
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SMP_WHOAMI_PORT equ 0c70h ; Local: Whoami Port
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SMP_INDEX_PORT equ 0c74h ; Global: Index Port
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SMP_ASSIGNMENT_PORT equ 0c71h ; Global: cpu assignment port
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; Supported Modes on Symmetrical SysPro ...
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;
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SMP_ASYMMETRICAL_MODE equ 0 ; SysPro compatible mode
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SMP_SYMMETRICAL_MODE equ 1 shl 5 ; Belize mode
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; PCR, ProcessorControl/StatusRegister Port bit pattern.
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;
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SMP_CTRL_SLEEP equ 1 shl 0 ; 1: assert sleep to CPU
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SMP_CTRL_AWAKE equ 1 shl 1 ; 1: Awake processor
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SMP_CTRL_CACHEON equ 1 shl 2 ; 1: enable intr/extr cache
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SMP_CTRL_CACHEOFF equ 1 shl 3 ; 1: disable intr/extr cache
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SMP_CTRL_FLUSH equ 1 shl 4 ; 1: flush 486 secondary cache
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SMP_CTRL_RESET equ 1 shl 5 ; 1: reset CPU
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SMP_RESET_CPU equ (SMP_CTRL_RESET+SMP_CTRL_AWAKE+SMP_CTRL_CACHEON)
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SMP_STAT_NCPIN equ 1 shl 1 ; NCP installed, always 1
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SMP_STAT_CACHEON equ 1 shl 2 ; 0: in/ex cache off, 1: on
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SMP_STAT_SLEEP equ 1 shl 3 ; 0: awake, 1: Sleeping
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SMP_STAT_NCPERR equ 1 shl 5 ; 0: no NCP error, 1:NCP error
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SMP_INTx_SET_PINT equ 1 shl 0
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SMP_INTx_CLR_PINT equ 1 shl 1
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SMP_INTx_ENABLE equ 1 shl 2
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SMP_INTx_DISABLE equ 1 shl 3
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;* MP INT13 Extended Control/Status Port...
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;
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SMP_MPINT13PORT equ 0cc9h
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SMP_ENBL_NCPERR equ 1 shl 0
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SMP_DSBL_NCPERR equ 1 shl 1
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SMP_ENBL_DMACHAIN equ 1 shl 2
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SMP_DSBL_DMACHAIN equ 1 shl 3
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SMP_ENBL_MCERR equ 1 shl 4
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SMP_DSBL_MCERR equ 1 shl 5
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;
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; The following macro performs an indexed IO read to the specified
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; IO address on the specified processor. The result of the read is
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; placed in the 'al' register.
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;
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; Warning: Assumes 8254 lock is owned
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;
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INDEXED_IO_READ macro cpu,ioaddress
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push edx
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push eax
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mov dx, SMP_INDEX_PORT
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mov al, cpu
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out dx, al ;select cpu
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inc dx
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mov ax, ioaddress
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out dx, ax ;select cpu's IO address to read from
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add dx, 2
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pop eax
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in al, dx ;read from the target cpu's IO address
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pop edx
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jmp $+2
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endm ;INDEXED_IO_READ
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;
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; The following macro performs an indexed IO write to the specified
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; IO address on the specified processor.
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;
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INDEXED_IO_WRITE macro cpu,ioaddress,data
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push edx
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push eax
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mov dx, SMP_INDEX_PORT
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mov al, data
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shl eax, 16
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mov ax, ioaddress
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shl eax, 8
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mov al, cpu
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out dx, eax
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pop eax
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pop edx
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jmp $+2
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endm ;INDEXED_IO_WRITE
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;*/
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