496 lines
14 KiB
NASM
496 lines
14 KiB
NASM
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title "Stall Execution Support"
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;++
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;
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; Copyright (c) 1989 Microsoft Corporation
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;
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; Module Name:
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;
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; ixstall.asm
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;
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; Abstract:
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;
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; This module implements the code necessary to field and process the
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; interval clock interrupt.
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;
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; Author:
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;
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; Shie-Lin Tzong (shielint) 12-Jan-1990
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;
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; Environment:
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;
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; Kernel mode only.
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;
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; Revision History:
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;
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; bryanwi 20-Sep-90
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;
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; Add KiSetProfileInterval, KiStartProfileInterrupt,
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; KiStopProfileInterrupt procedures.
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; KiProfileInterrupt ISR.
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; KiProfileList, KiProfileLock are delcared here.
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;
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; shielint 10-Dec-90
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; Add performance counter support.
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; Move system clock to irq8, ie we now use RTC to generate system
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; clock. Performance count and Profile use timer 1 counter 0.
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; The interval of the irq0 interrupt can be changed by
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; KiSetProfileInterval. Performance counter does not care about the
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; interval of the interrupt as long as it knows the rollover count.
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; Note: Currently I implemented 1 performance counter for the whole
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; i386 NT.
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;
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; John Vert (jvert) 11-Jul-1991
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; Moved from ke\i386 to hal\i386. Removed non-HAL stuff
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;
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; shie-lin tzong (shielint) 13-March-92
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; Move System clock back to irq0 and use RTC (irq8) to generate
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; profile interrupt. Performance counter and system clock use time1
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; counter 0 of 8254.
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;
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; Landy Wang (corollary!landy) 04-Dec-92
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; Created this module by moving routines from ixclock.asm to here.
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;
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;--
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.386p
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.xlist
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include hal386.inc
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include callconv.inc ; calling convention macros
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include i386\ix8259.inc
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include i386\kimacro.inc
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include mac386.inc
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include i386\ixcmos.inc
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.list
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EXTRNP _DbgBreakPoint,0,IMPORT
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EXTRNP _HalpAcquireCmosSpinLock ,0
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EXTRNP _HalpReleaseCmosSpinLock ,0
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;
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; Constants used to initialize CMOS/Real Time Clock
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;
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D_INT032 EQU 8E00h ; access word for 386 ring 0 interrupt gate
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RTCIRQ EQU 8 ; IRQ number for RTC interrupt
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REGISTER_B_ENABLE_PERIODIC_INTERRUPT EQU 01000010B
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; RT/CMOS Register 'B' Init byte
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; Values for byte shown are
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; Bit 7 = Update inhibit
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; Bit 6 = Periodic interrupt enable
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; Bit 5 = Alarm interrupt disable
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; Bit 4 = Update interrupt disable
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; Bit 3 = Square wave disable
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; Bit 2 = BCD data format
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; Bit 1 = 24 hour time mode
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; Bit 0 = Daylight Savings disable
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REGISTER_B_DISABLE_PERIODIC_INTERRUPT EQU 00000010B
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;
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; RegisterAInitByte sets 8Hz clock rate, used during init to set up
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; KeStallExecutionProcessor, etc. (See RegASystemClockByte below.)
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;
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RegisterAInitByte EQU 00101101B ; RT/CMOS Register 'A' init byte
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; 32.768KHz Base divider rate
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; 8Hz int rate, period = 125.0ms
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PeriodInMicroSecond EQU 125000 ;
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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HalpStallCount dd 0
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_DATA ends
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INIT SEGMENT PARA PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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page ,132
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subttl "Initialize Stall Execution Counter"
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;++
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;
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; VOID
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; HalpInitializeStallExecution (
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; IN CCHAR ProcessorNumber
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; )
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;
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; Routine Description:
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;
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; This routine initialize the per Microsecond counter for
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; KeStallExecutionProcessor
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;
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; Arguments:
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;
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; ProcessorNumber - Processor Number
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;
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; Return Value:
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;
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; None.
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;
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; Note:
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;
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; Current implementation assumes that all the processors share
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; the same Real Time Clock. So, the dispatcher database lock is
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; acquired before entering this routine to guarantee only one
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; processor can access the routine.
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;
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;--
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KiseInterruptCount equ [ebp-12] ; local variable
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cPublicProc _HalpInitializeStallExecution ,1
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ifndef NT_UP
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;;
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;; This function currently doesn't work from any processor but the
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;; boot processor - for now stub out the others
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;;
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mov eax, PCR[PcPrcb]
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cmp byte ptr [eax].PbNumber, 0
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je @f
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mov eax, HalpStallCount
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mov PCR[PcStallScaleFactor], eax
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stdRET _HalpInitializeStallExecution
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@@:
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endif
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push ebp ; save ebp
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mov ebp, esp ; set up 12 bytes for local use
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sub esp, 12
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pushfd ; save caller's eflag
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;
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; Initialize Real Time Clock to interrupt us for every 125ms at
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; IRQ 8.
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;
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cli ; make sure interrupts are disabled
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;
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; Get and save current 8259 masks
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;
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xor eax,eax
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;
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; Assume there is no third and fourth PICs
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;
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; Get interrupt Mask on PIC2
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;
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in al,PIC2_PORT1
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shl eax, 8
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;
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; Get interrupt Mask on PIC1
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;
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in al,PIC1_PORT1
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push eax ; save the masks
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mov eax, NOT (( 1 SHL PIC_SLAVE_IRQ) + (1 SHL RTCIRQ))
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; Mask all the irqs except irq 2 and 8
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SET_8259_MASK ; Set 8259's int mask register
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;
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; Since RTC interrupt will come from IRQ 8, we need to
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; Save original irq 8 descriptor and set the descriptor to point to
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; our own handler.
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;
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sidt fword ptr [ebp-8] ; get IDT address
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mov ecx, [ebp-6] ; (ecx)->IDT
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mov eax, (RTCIRQ+PRIMARY_VECTOR_BASE)
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shl eax, 3 ; 8 bytes per IDT entry
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add ecx, eax ; now at the correct IDT RTC entry
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push dword ptr [ecx] ; (TOS) = original desc of IRQ 8
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push dword ptr [ecx + 4] ; each descriptor has 8 bytes
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;
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; Pushing the appropriate entry address now (instead of
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; the IDT start address later) to make the pop at the end simpler.
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;
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push ecx ; (TOS) -> &IDT[HalProfileVector]
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mov eax, offset FLAT:RealTimeClockHandler
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mov word ptr [ecx], ax ; Lower half of handler addr
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mov word ptr [ecx+2], KGDT_R0_CODE ; set up selector
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mov word ptr [ecx+4], D_INT032 ; 386 interrupt gate
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shr eax, 16 ; (ax)=higher half of handler addr
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mov word ptr [ecx+6], ax
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mov dword ptr KiseinterruptCount, 0 ; set no interrupt yet
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stdCall _HalpAcquireCmosSpinLock ; intr disabled
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mov ax,(RegisterAInitByte SHL 8) OR 0AH ; Register A
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CMOS_WRITE ; Initialize it
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;
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; Don't clobber the Daylight Savings Time bit in register B, because we
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; stash the LastKnownGood "environment variable" there.
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;
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mov ax, 0bh
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CMOS_READ
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and al, 1
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mov ah, al
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or ah, REGISTER_B_ENABLE_PERIODIC_INTERRUPT
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mov al, 0bh
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CMOS_WRITE ; Initialize it
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mov al,0CH ; Register C
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CMOS_READ ; Read to initialize
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mov al,0DH ; Register D
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CMOS_READ ; Read to initialize
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mov dword ptr [KiseInterruptCount], 0
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stdCall _HalpReleaseCmosSpinLock
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;
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; Now enable the interrupt and start the counter
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; (As a matter of fact, only IRQ8 can come through.)
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;
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xor eax, eax ; (eax) = 0, initialize loopcount
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ALIGN 16
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sti
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jmp kise10
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ALIGN 16
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kise10:
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sub eax, 1 ; increment the loopcount
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jnz short kise10
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if DBG
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;
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; Counter overflowed
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;
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stdCall _DbgBreakPoint
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endif
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jmp short kise10
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;
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; Our RealTimeClock interrupt handler. The control comes here through
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; irq 8.
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; Note: we discard first real time clock interrupt and compute the
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; permicrosecond loopcount on receiving of the second real time
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; interrupt. This is because the first interrupt is generated
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; based on the previous real time tick interval.
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;
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RealTimeClockHandler:
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inc dword ptr KiseInterruptCount ; increment interrupt count
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cmp dword ptr KiseInterruptCount,1 ; Is this the first interrupt?
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jnz kise25 ; no, its the second go process it
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pop eax ; get rid of original ret addr
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push offset FLAT:kise10 ; set new return addr
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stdCall _HalpAcquireCmosSpinLock ; intr disabled
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mov ax,(RegisterAInitByte SHL 8) OR 0AH ; Register A
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CMOS_WRITE ; Initialize it
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;
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; Don't clobber the Daylight Savings Time bit in register B, because we
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; stash the LastKnownGood "environment variable" there.
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;
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mov ax, 0bh
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CMOS_READ
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and al, 1
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mov ah, al
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or ah, REGISTER_B_ENABLE_PERIODIC_INTERRUPT
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mov al, 0bh
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CMOS_WRITE ; Initialize it
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mov al,0CH ; Register C
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CMOS_READ ; Read to initialize
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mov al,0DH ; Register D
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CMOS_READ ; Read to initialize
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stdCall _HalpReleaseCmosSpinLock
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;
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; Dismiss the interrupt.
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;
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mov al, OCW2_NON_SPECIFIC_EOI ; send non specific eoi to slave
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out PIC2_PORT0, al
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mov al, PIC2_EOI ; specific eoi to master for pic2 eoi
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out PIC1_PORT0, al ; send irq2 specific eoi to master
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xor eax, eax ; reset loop counter
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iretd
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kise25:
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;
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; ** temporary - check for incorrect KeStallExecutionProcessorLoopCount
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;
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if DBG
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cmp eax, 0
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jnz short kise30
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stdCall _DbgBreakPoint
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endif
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; never return
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;
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; ** End temporay code
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;
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kise30:
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neg eax
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xor edx, edx ; (edx:eax) = divident
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mov ecx, PeriodInMicroSecond; (ecx) = time spent in the loop
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div ecx ; (eax) = loop count per microsecond
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cmp edx, 0 ; Is remainder =0?
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jz short kise40 ; yes, go kise40
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inc eax ; increment loopcount by 1
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kise40:
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mov PCR[PcStallScaleFactor], eax
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mov HalpStallCount, eax
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;
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; Reset return address to kexit
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;
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pop eax ; discard original return address
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push offset FLAT:kexit ; return to kexit
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mov eax, (HIGHEST_LEVEL_FOR_8259 - RTCIRQ)
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;
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; Shutdown periodic interrupt
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;
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stdCall _HalpAcquireCmosSpinLock
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mov ax,(RegisterAInitByte SHL 8) OR 0AH ; Register A
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CMOS_WRITE ; Initialize it
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mov ax, 0bh
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CMOS_READ
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and al, 1
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mov ah, al
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or ah, REGISTER_B_DISABLE_PERIODIC_INTERRUPT
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mov al, 0bh
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CMOS_WRITE ; Initialize it
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mov al,0CH ; Register C
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CMOS_READ ; dismiss pending interrupt
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stdCall _HalpReleaseCmosSpinLock
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;
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; Dismiss the interrupt.
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;
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mov eax, RTCIRQ
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mov al, OCW2_NON_SPECIFIC_EOI ; send non specific eoi to slave
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out PIC2_PORT0, al
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mov al, PIC2_EOI ; specific eoi to master for pic2 eoi
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out PIC1_PORT0, al ; send irq2 specific eoi to master
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and word ptr [esp+8], NOT 0200H ; Disable interrupt upon return
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iretd
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kexit: ; Interrupts are disabled
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pop ecx ; (ecx) -> &IDT[HalProfileVector]
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pop [ecx+4] ; restore higher half of RTC desc
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pop [ecx] ; restore lower half of RTC desc
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pop eax ; (eax) = origianl 8259 int masks
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SET_8259_MASK
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|
|
|
||
|
|
popfd ; restore caller's eflags
|
||
|
|
mov esp, ebp
|
||
|
|
pop ebp ; restore ebp
|
||
|
|
stdRET _HalpInitializeStallExecution
|
||
|
|
|
||
|
|
stdENDP _HalpInitializeStallExecution
|
||
|
|
|
||
|
|
cPublicProc _HalpRemoveFences
|
||
|
|
mov word ptr fence1, 0c98bh
|
||
|
|
stdRET _HalpRemoveFences
|
||
|
|
stdENDP _HalpRemoveFences
|
||
|
|
|
||
|
|
INIT ends
|
||
|
|
|
||
|
|
_TEXT SEGMENT PARA PUBLIC 'CODE'
|
||
|
|
ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
|
||
|
|
|
||
|
|
page ,132
|
||
|
|
subttl "Stall Execution"
|
||
|
|
;++
|
||
|
|
;
|
||
|
|
; VOID
|
||
|
|
; KeStallExecutionProcessor (
|
||
|
|
; IN ULONG MicroSeconds
|
||
|
|
; )
|
||
|
|
;
|
||
|
|
; Routine Description:
|
||
|
|
;
|
||
|
|
; This function stalls execution for the specified number of microseconds.
|
||
|
|
; KeStallExecutionProcessor
|
||
|
|
;
|
||
|
|
; Arguments:
|
||
|
|
;
|
||
|
|
; MicroSeconds - Supplies the number of microseconds that execution is to be
|
||
|
|
; stalled.
|
||
|
|
;
|
||
|
|
; Return Value:
|
||
|
|
;
|
||
|
|
; None.
|
||
|
|
;
|
||
|
|
;--
|
||
|
|
|
||
|
|
MicroSeconds equ [esp + 4]
|
||
|
|
|
||
|
|
|
||
|
|
cPublicProc _KeStallExecutionProcessor ,1
|
||
|
|
cPublicFpo 1, 0
|
||
|
|
|
||
|
|
;
|
||
|
|
; Issue a CPUID to implement a "fence"
|
||
|
|
;
|
||
|
|
push ebx ; cpuid uses eax, ebx, ecx, edx
|
||
|
|
xor eax, eax ; Processor zero
|
||
|
|
.586p
|
||
|
|
fence1: cpuid
|
||
|
|
.386p
|
||
|
|
pop ebx
|
||
|
|
|
||
|
|
mov ecx, MicroSeconds ; (ecx) = Microseconds
|
||
|
|
jecxz short kese10 ; return if no loop needed
|
||
|
|
|
||
|
|
mov eax, PCR[PcStallScaleFactor] ; get per microsecond
|
||
|
|
; loop count for the processor
|
||
|
|
mul ecx ; (eax) = desired loop count
|
||
|
|
|
||
|
|
if DBG
|
||
|
|
;
|
||
|
|
; Make sure we the loopcount is less than 4G and is not equal to zero
|
||
|
|
;
|
||
|
|
|
||
|
|
cmp edx, 0
|
||
|
|
jz short @f
|
||
|
|
int 3
|
||
|
|
|
||
|
|
@@: cmp eax,0
|
||
|
|
jnz short @f
|
||
|
|
int 3
|
||
|
|
@@:
|
||
|
|
endif
|
||
|
|
ALIGN 16
|
||
|
|
jmp kese05
|
||
|
|
|
||
|
|
ALIGN 16
|
||
|
|
kese05: sub eax, 1 ; (eax) = (eax) - 1
|
||
|
|
jnz short kese05
|
||
|
|
kese10:
|
||
|
|
stdRET _KeStallExecutionProcessor
|
||
|
|
|
||
|
|
stdENDP _KeStallExecutionProcessor
|
||
|
|
|
||
|
|
_TEXT ends
|
||
|
|
|
||
|
|
end
|