240 lines
6.3 KiB
C
240 lines
6.3 KiB
C
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Copyright (c) 1991 NCR Corporation
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Module Name:
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mca.h
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Abstract:
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This module contains the defines and structure definitions for
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Micro Channel machines.
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Author:
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David Risner (o-ncrdr) 21-Jul-1991
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Revision History:
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--*/
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#ifndef _MCA_
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#define _MCA_
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//
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// Define the DMA page register structure (for 8237 compatibility)
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//
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typedef struct _DMA_PAGE{
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UCHAR Reserved1;
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UCHAR Channel2;
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UCHAR Channel3;
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UCHAR Channel1;
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UCHAR Reserved2[3];
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UCHAR Channel0;
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UCHAR Reserved3;
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UCHAR Channel6;
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UCHAR Channel7;
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UCHAR Channel5;
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UCHAR Reserved4[3];
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UCHAR RefreshPage;
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} DMA_PAGE, *PDMA_PAGE;
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//
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// Define DMA 1 address and count structure (for 8237 compatibility)
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//
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typedef struct _DMA1_ADDRESS_COUNT {
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UCHAR DmaBaseAddress;
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UCHAR DmaBaseCount;
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} DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;
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//
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// Define DMA 2 address and count structure (for 8237 compatibility)
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//
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typedef struct _DMA2_ADDRESS_COUNT {
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UCHAR DmaBaseAddress;
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UCHAR Reserved1;
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UCHAR DmaBaseCount;
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UCHAR Reserved2;
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} DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT;
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//
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// Define DMA 1 control register structure (for 8237 compatibility)
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//
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typedef struct _DMA1_CONTROL {
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DMA1_ADDRESS_COUNT DmaAddressCount[4];
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UCHAR DmaStatus;
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UCHAR DmaRequest;
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UCHAR SingleMask;
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UCHAR Mode;
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UCHAR ClearBytePointer;
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UCHAR MasterClear;
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UCHAR ClearMask;
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UCHAR AllMask;
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} DMA1_CONTROL, *PDMA1_CONTROL;
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//
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// Define DMA 2 control register structure (for 8237 compatibility)
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//
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typedef struct _DMA2_CONTROL {
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DMA2_ADDRESS_COUNT DmaAddressCount[4];
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UCHAR DmaStatus;
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UCHAR Reserved1;
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UCHAR DmaRequest;
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UCHAR Reserved2;
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UCHAR SingleMask;
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UCHAR Reserved3;
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UCHAR Mode;
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UCHAR Reserved4;
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UCHAR ClearBytePointer;
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UCHAR Reserved5;
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UCHAR MasterClear;
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UCHAR Reserved6;
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UCHAR ClearMask;
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UCHAR Reserved7;
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UCHAR AllMask;
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UCHAR Reserved8;
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} DMA2_CONTROL, *PDMA2_CONTROL;
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typedef struct _MCA_DMA_CONTROLLER {
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UCHAR DmaFunctionLsb; // Offset 0x018
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UCHAR DmaFunctionMsb; // Offset 0x019
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UCHAR DmaFunctionData; // Offset 0x01a
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UCHAR Reserved01;
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UCHAR ScbAttentionPort; // Offset 0x01c
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UCHAR ScbCommandPort; // Offset 0x01d
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UCHAR Reserved02;
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UCHAR ScbStatusPort; // Offset 0x01f
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} MCA_DMA_CONTROLLER, *PMCA_DMA_CONTROLLER;
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//
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// Define Programmable Option Select register set
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//
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typedef struct _PROGRAMMABLE_OPTION_SELECT {
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UCHAR AdapterIdLsb;
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UCHAR AdapterIdMsb;
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UCHAR OptionSelectData1;
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UCHAR OptionSelectData2;
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UCHAR OptionSelectData3;
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UCHAR OptionSelectData4;
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UCHAR SubaddressExtensionLsb;
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UCHAR SubaddressExtensionMsb;
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} PROGRAMMABLE_OPTION_SELECT, *PPROGRAMMABLE_OPTION_SELECT;
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//
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// Define Micro Channel i/o address map
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//
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typedef struct _MCA_CONTROL {
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DMA1_CONTROL Dma1BasePort; // Offset 0x000
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UCHAR Reserved0[8];
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UCHAR ExtendedDmaBasePort[8]; // Offset 0x018
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UCHAR Interrupt1ControlPort0; // Offset 0x020
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UCHAR Interrupt1ControlPort1; // Offset 0x021
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UCHAR Reserved1[64 - 1];
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UCHAR SystemControlPortB; // Offset 0x061
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UCHAR Reserved2[32 - 2];
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DMA_PAGE DmaPageLowPort; // Offset 0x080
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UCHAR Reserved3;
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UCHAR CardSelectedFeedback; // Offset 0x091
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UCHAR SystemControlPortA; // Offset 0x092
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UCHAR Reserved4;
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UCHAR SystemBoardSetup; // Offset 0x094
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UCHAR Reserved5;
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UCHAR AdapterSetup; // Offset 0x096
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UCHAR AdapterSetup2; // Offset 0x097
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UCHAR Reserved7[8];
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UCHAR Interrupt2ControlPort0; // Offset 0x0a0
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UCHAR Interrupt2ControlPort1; // Offset 0x0a1
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UCHAR Reserved8[32-2];
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DMA2_CONTROL Dma2BasePort; // Offset 0x0c0
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UCHAR Reserved9[32];
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PROGRAMMABLE_OPTION_SELECT Pos; // Offset 0x100
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} MCA_CONTROL, *PMCA_CONTROL;
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//
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// Define POS adapter setup equates for use with AdapterSetup field above
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//
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#define MCA_ADAPTER_SETUP_ON 0x008
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#define MCA_ADAPTER_SETUP_OFF 0x000
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//
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// Define DMA Extended Function register
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//
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typedef struct _DMA_EXTENDED_FUNCTION {
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UCHAR ChannelNumber : 3;
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UCHAR Reserved : 1;
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UCHAR Command : 4;
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} DMA_EXTENDED_FUNCTION, *PDMA_EXTENDED_FUNCTION;
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//
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// Define Command values
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//
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#define WRITE_IO_ADDRESS 0x00 // write I/O address reg
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#define WRITE_MEMORY_ADDRESS 0x20 // write memory address reg
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#define READ_MEMORY_ADDRESS 0x30 // read memory address reg
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#define WRITE_TRANSFER_COUNT 0x40 // write transfer count reg
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#define READ_TRANSFER_COUNT 0x50 // read transfer count reg
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#define READ_STATUS 0x60 // read status register
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#define WRITE_MODE 0x70 // write mode register
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#define WRITE_ARBUS 0x80 // write arbus register
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#define SET_MASK_BIT 0x90 // set bit in mask reg
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#define CLEAR_MASK_BIT 0xa0 // clear bit in mask reg
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#define MASTER_CLEAR 0xd0 // master clear
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//
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// Define DMA Extended Mode register
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//
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typedef struct _DMA_EXTENDED_MODE {
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UCHAR ProgrammedIo : 1; // 0 = do not use programmed i/o address
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UCHAR AutoInitialize : 1;
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UCHAR DmaOpcode : 1; // 0 = verify memory, 1 = data transfer
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UCHAR TransferDirection : 1; // 0 = read memory, 1 = write memory
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UCHAR Reserved1 : 2;
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UCHAR DmaWidth : 1; // 0 = 8bit, 1 = 16bit
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UCHAR Reserved2 : 1;
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} DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE;
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//
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// DMA Extended Mode equates for use with the _DMA_EXTENDED_MODE structure.
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//
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#define DMA_EXT_USE_PIO 0x01
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#define DMA_EXT_NO_PIO 0x00
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#define DMA_EXT_VERIFY 0x00
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#define DMA_EXT_DATA_XFER 0x01
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#define DMA_EXT_WIDTH_8_BIT 0x00
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#define DMA_EXT_WIDTH_16_BIT 0x01
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//
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// DMA mode option definitions
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//
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#define DMA_MODE_READ 0x00 // read data into memory
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#define DMA_MODE_WRITE 0x08 // write data from memory
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#define DMA_MODE_VERIFY 0x00 // verify data
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#define DMA_MODE_TRANSFER 0x04 // transfer data
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//
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// DMA extended mode constants
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//
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#define MAX_MCA_DMA_CHANNEL_NUMBER 0x07 // maximum MCA DMA channel number
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#endif
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