736 lines
24 KiB
NASM
736 lines
24 KiB
NASM
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title "Context Swap"
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;++
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;
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; Copyright (c) 2000 Microsoft Corporation
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;
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; Module Name:
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;
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; ctxswap.asm
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;
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; Abstract:
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;
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; This module implements the code necessary to field the dispatch interrupt
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; and perform context switching.
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;
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; Author:
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;
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; David N. Cutler (davec) 26-Aug-2000
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;
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; Environment:
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;
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; Kernel mode only.
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;
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;--
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include ksamd64.inc
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extern KeAcquireQueuedSpinLockAtDpcLevel:proc
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extern KeAcquireQueuedSpinLockRaiseToSynch:proc
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extern KeBugCheck:proc
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extern KeReleaseQueuedSpinLock:proc
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extern KeReleaseQueuedSpinLockFromDpcLevel:proc
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extern KiDeliverApc:proc
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extern KiDispatcherLock:qword
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extern KiQuantumEnd:proc
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extern KiReadyThread:proc
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extern KiRetireDpcList:proc
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extern __imp_HalRequestSoftwareInterrupt:qword
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subttl "Unlock Dispatcher Database"
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;++
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;
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; VOID
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; KiUnlockDispatcherDatabase (
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; IN KIRQL OldIrql
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; )
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;
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; Routine Description:
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;
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; This routine is entered at SYNCH_LEVEL with the dispatcher database
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; locked. Its function is to either unlock the dispatcher database and
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; return or initiate a context switch if another thread has been selected
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; for execution.
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;
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; Arguments:
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;
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; OldIrql (cl) - Supplies the IRQL when the dispatcher database lock was
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; acquired.
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;
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; Return Value:
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;
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; None.
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;
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;--
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UdFrame struct
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P1Home dq ? ; queued spin lock number parameter
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P2Home dq ? ; previous IRQL paramater
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SavedIrql db ? ; saved previous IRQL
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Fill db 7 dup (?) ; fill to 8 mod 16
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UdFrame ends
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NESTED_ENTRY KiUnlockDispatcherDatabase, _TEXT$00
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alloc_stack (sizeof UdFrame) ; allocate stack frame
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END_PROLOGUE
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;
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; Check if a new thread is scheduled for execution.
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;
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cmp qword ptr gs:[PcNextThread], 0 ; check if thread scheduled
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jne short KiUD30 ; if ne, new thread scheduled
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;
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; Release dispatcher database lock, lower IRQL to its previous level,
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; and return.
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;
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ifndef NT_UP
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KiUD10: mov dl, cl ; set old IRQL value
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mov ecx, LockQueueDispatcherLock ; set lock queue number
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call KeReleaseQueuedSpinLock ; release dispatcher lock
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else
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KiUD10: movzx ecx, cl ; set IRQL to previous level
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SetIrql ;
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endif
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add rsp, sizeof UdFrame ; deallocate stack frame
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ret ; return
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;
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; A new thread has been selected to run on the current processor, but the new
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; IRQL is not below dispatch level. If the current processor is not executing
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; a DPC, then request a dispatch interrupt on the current processor.
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;
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KiUD20: cmp qword ptr gs:[PcDpcRoutineActive], 0 ; check if DPC routine active
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jne short KiUD10 ; if ne, DPC routine is active
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mov UdFrame.SavedIrql[rsp], cl ; save previous IRQL
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mov cl, DISPATCH_LEVEL ; request dispatch interrupt
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call __imp_HalRequestSoftwareInterrupt ;
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mov cl, UdFrame.SavedIrql[rsp] ; restore previous IRQL
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jmp short KiUD10
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;
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; Check if the previous IRQL is less than dispatch level.
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;
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KiUD30: cmp cl, DISPATCH_LEVEL ; check if IRQL below dispatch level
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jge short KiUD20 ; if ge, not below dispatch level
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add rsp, sizeof UdFrame ; deallocate stack frame
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jmp short KxUnlockDispatcherDatabase ; finish in common code
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NESTED_END KiUnlockDispatcherDatabase, _TEXT$00
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;
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; There is a new thread scheduled for execution and the previous IRQL is
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; less than dispatch level. Context switch to the new thread immediately.
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;
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; N.B. The following routine is entered by falling through the from above
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; code.
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;
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; N.B. The following routine is carefully written as a nested function that
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; appears to have been called directly by the caller of the above
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; function which unlocks the dispatcher database.
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;
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; Arguments:
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;
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; OldIrql (cl) - Supplies the IRQL when the dispatcher database lock was
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; acquired.
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;
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NESTED_ENTRY KxUnlockDispatcherDatabase, _TEXT$00
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GENERATE_EXCEPTION_FRAME ; generate exception frame
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mov rbx, gs:[PcCurrentPrcb] ; get current PRCB address
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mov rsi, PbNextThread[rbx] ; get next thread address
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mov rdi, PbCurrentThread[rbx] ; get current thread address
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and qword ptr PbNextThread[rbx], 0 ; clear next thread address
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mov PbCurrentThread[rbx], rsi ; set current thread address
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mov ThWaitIrql[rdi], cl ; save previous IRQL
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ifndef NT_UP
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mov byte ptr ThIdleSwapBlock[rdi], 1 ; block swap from idle
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endif
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mov rcx, rdi ; set address of current thread
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call KiReadyThread ; reready thread for execution
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xor eax, eax ; set NPX save false
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mov cl, ThWaitIrql[rdi] ; set APC interrupt bypass disable
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ifndef NT_UP
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xor edx, edx ; set swap from idle false
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endif
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call SwapContext ; swap context
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movzx ecx, byte ptr ThWaitIrql[rsi] ; get original wait IRQL
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or al, al ; check if kernel APC pending
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jz short KiXD10 ; if z, no kernel APC pending
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mov ecx, APC_LEVEL ; set IRQL to APC level
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SetIrql ;
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xor ecx, ecx ; set previous mode to kernel
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xor edx, edx ; clear exception frame address
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xor r8, r8 ; clear trap frame address
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call KiDeliverApc ; deliver kernel mode APC
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xor ecx, ecx ; set original wait IRQL
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KiXD10: ; reference label
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SetIrql ; set IRQL to previous level
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RESTORE_EXCEPTION_STATE ; restore exception state/deallocate
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ret ; return
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NESTED_END KxUnlockDispatcherDatabase, _TEXT$00
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subttl "Swap Context"
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;++
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;
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; BOOLEAN
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; KiSwapContext (
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; IN PKTHREAD Thread
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; )
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;
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; Routine Description:
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;
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; This function is a small wrapper that marshalls arguments and calls the
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; actual swap context routine.
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;
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; Arguments:
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;
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; Thread (rcx) - Supplies the address of the new thread.
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;
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; Return Value:
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;
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; If a kernel APC is pending, then a value of TRUE is returned. Otherwise,
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; a value of FALSE is returned.
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;
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;--
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NESTED_ENTRY KiSwapContext, _TEXT$00
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GENERATE_EXCEPTION_FRAME ; generate exception frame
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mov rbx, gs:[PcCurrentPrcb] ; get current PRCB address
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mov rsi, rcx ; set next thread address
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mov rdi, PbCurrentThread[rbx] ; get current thread address
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mov PbCurrentThread[rbx], rsi ; set current thread address
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xor eax, eax ; set NPX save false
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mov cl, ThWaitIrql[rdi] ; set APC interrupt bypass disable
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ifndef NT_UP
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xor edx, edx ; set swap from idle false
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endif
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call SwapContext ; swap context
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RESTORE_EXCEPTION_STATE ; restore exception state/deallocate
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ret ; return
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NESTED_END KiSwapContext, _TEXT$00
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subttl "Dispatch Interrupt"
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;++
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;
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; Routine Description:
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;
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; This routine is entered as the result of a software interrupt generated
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; at DISPATCH_LEVEL. Its function is to process the DPC list, and then
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; perform a context switch if a new thread has been selected for execution
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; on the current processor.
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;
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; This routine is entered at DISPATCH_LEVEL with the dispatcher database
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; unlocked.
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;
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; Arguments:
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;
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; None
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;
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; Return Value:
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;
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; None.
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;
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;--
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DiFrame struct
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P1Home dq ? ; PRCB address parameter
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Fill dq ? ; fill to 8 mod 16
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SavedRbx dq ? ; saved RBX
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DiFrame ends
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NESTED_ENTRY KiDispatchInterrupt, _TEXT$00
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push_reg rbx ; save nonvolatile register
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alloc_stack (sizeof DiFrame - 8) ; allocate stack frame
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END_PROLOGUE
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mov rbx, gs:[PcCurrentPrcb] ; get current PRCB address
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and dword ptr PbDpcInterruptRequested[rbx], 0 ; clear request
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;
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; Check if the DPC queue has any entries to process.
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;
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KiDI10: cli ; disable interrupts
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mov eax, PbDpcQueueDepth[rbx] ; get DPC queue depth
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or eax, PbTimerHand[rbx] ; merge timer hand value
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jz short KiDI20 ; if z, no DPCs to process
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mov PbSavedRsp[rbx], rsp ; save current stack pointer
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mov rsp, PbDpcStack[rbx] ; set DPC stack pointer
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mov rcx, rbx ; set PRCB address parameter
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call KiRetireDpcList ; process the DPC list
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mov rsp, PbSavedRsp[rbx] ; restore current stack pointer
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;
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; Check to determine if quantum end is requested.
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;
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KiDI20: sti ; enable interrupts
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cmp dword ptr PbQuantumEnd[rbx], 0 ; check if quantum end request
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je short KiDI50 ; if e, quantum end not requested
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;
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; Process quantum end event.
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;
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; N.B. If a new thread is selected as a result of processing the quantum end
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; request, then the new thread is returned with the dispatcher database
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; locked. Otherwise, NULL is returned with the dispatcher database
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; unlocked.
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;
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and dword ptr PbQuantumEnd[rbx], 0 ; clear quantum end indicator
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call KiQuantumEnd ; process quantum end
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test rax, rax ; test if new thread selected
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jnz short KiDI60 ; if ne, new thread selected
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;
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; A new thread has not been selected for execution. Restore nonvolatile
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; registers, deallocate stack frame, and return.
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;
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KiDI30: mov rbx, DiFrame.SavedRbx[rsp] ; restore nonvolatile register
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add rsp, sizeof DiFrame ; deallocate stack frame
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ret ; return
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;
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; The dispatch lock could not be acquired. Lower IRQL to dispatch level, and
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; loop processing the DPC list and quantum end events.
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;
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KiDI40: mov ecx, DISPATCH_LEVEL ; set IRQL to DISPATCH_LEVEL
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SetIrql ;
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jmp short KiDI10 ; try again
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;
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; Check to determine if a new thread has been selected for execution on this
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; processor.
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;
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KiDI50: cmp qword ptr PbNextThread[rbx], 0 ; check if new thread selected
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je short KiDI30 ; if eq, then no new thread
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ifndef NT_UP
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mov ecx, SYNCH_LEVEL ; set IRQL to SYNCH_LEVEL
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SetIrql ;
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lea rcx, KiDispatcherLock ; get dispatcher database lock address
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lea rdx, PbLockQueue + (16 * LockQueueDispatcherLock)[rbx] ; lock queue
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xor eax, eax ; set comperand value to NULL
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lock cmpxchg [rcx], rdx ; try to acquire dispatcher lock
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jnz short KiDI40 ; if nz, dispatcher lock not acquired
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endif
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mov rax, PbNextThread[rbx] ; get next thread address
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;
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; Swap context to a new thread.
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;
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KiDI60: add rsp, sizeof DiFrame - 8 ; deallocate stack frame
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pop rbx ; restore nonvolatile register
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jmp short KxDispatchInterrupt ; finish in common code
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NESTED_END KiDispatchInterrupt, _TEXT$00
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;
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; There is a new thread scheduled for execution and the dispatcher lock
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; has been acquired. Context switch to the new thread immediately.
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||
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;
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|
; N.B. The following routine is entered by falling through from the above
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||
|
|
; routine.
|
||
|
|
;
|
||
|
|
; N.B. The following routine is carefully written as a nested function that
|
||
|
|
; appears to have been called directly by the caller of the above
|
||
|
|
; function which processes the dispatch interrupt.
|
||
|
|
;
|
||
|
|
; Arguments:
|
||
|
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;
|
||
|
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; Thread (rax) - Supplies the address of the next thread to run on the
|
||
|
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; current processor.
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||
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;
|
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NESTED_ENTRY KxDispatchInterrupt, _TEXT$00
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GENERATE_EXCEPTION_FRAME ; generate exception frame
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mov rbx, gs:[PcCurrentPrcb] ; get current PRCB address
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mov rsi, rax ; set address of next thread
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|
|
mov rdi, PbCurrentThread[rbx] ; get current thread address
|
||
|
|
and qword ptr PbNextThread[rbx], 0 ; clear next thread address
|
||
|
|
mov PbCurrentThread[rbx], rsi ; set current thread address
|
||
|
|
|
||
|
|
ifndef NT_UP
|
||
|
|
|
||
|
|
mov byte ptr ThIdleSwapBlock[rdi], 1 ; block swap from idle
|
||
|
|
|
||
|
|
endif
|
||
|
|
|
||
|
|
mov rcx, rdi ; set address of current thread
|
||
|
|
call KiReadyThread ; reready thread for execution
|
||
|
|
mov eax, TRUE ; set NPX save true
|
||
|
|
mov cl, APC_LEVEL ; set APC interrupt bypass disable
|
||
|
|
|
||
|
|
ifndef NT_UP
|
||
|
|
|
||
|
|
xor edx, edx ; set swap from idle false
|
||
|
|
|
||
|
|
endif
|
||
|
|
|
||
|
|
call SwapContext ; call context swap routine
|
||
|
|
|
||
|
|
RESTORE_EXCEPTION_STATE ; restore exception state/deallocate
|
||
|
|
|
||
|
|
ret ; return
|
||
|
|
|
||
|
|
NESTED_END KxDispatchInterrupt, _TEXT$00
|
||
|
|
|
||
|
|
subttl "Swap Context"
|
||
|
|
;++
|
||
|
|
;
|
||
|
|
; Routine Description:
|
||
|
|
;
|
||
|
|
; This routine is called to swap context from one thread to the next. It
|
||
|
|
; swaps context, flushes the translation buffer, swaps the process address
|
||
|
|
; space if necessary, and returns to its caller.
|
||
|
|
;
|
||
|
|
; N.B. This routine is only called by code within this module and the idle
|
||
|
|
; thread code and uses special register calling conventions.
|
||
|
|
;
|
||
|
|
; Arguments:
|
||
|
|
;
|
||
|
|
; al - Supplies a boolean value that determines whether the full legacy
|
||
|
|
; floating state needs to be saved.
|
||
|
|
;
|
||
|
|
; cl - Supplies the APC interrupt bypass disable IRQL value.
|
||
|
|
;
|
||
|
|
; edx - Supplies a logical value that specifies whether the context swap
|
||
|
|
; is being called from the idle thread (MP systems only).
|
||
|
|
;
|
||
|
|
; rbx - Supplies the address of the current PRCB.
|
||
|
|
;
|
||
|
|
; rdi - Supplies the address of previous thread.
|
||
|
|
;
|
||
|
|
; rsi - Supplies the address of next thread.
|
||
|
|
;
|
||
|
|
; Return value:
|
||
|
|
;
|
||
|
|
; al - Supplies the kernel APC pending flag.
|
||
|
|
;
|
||
|
|
; rbx - Supplies the address of the current PRCB.
|
||
|
|
;
|
||
|
|
; rsi - Supplies the address of current thread.
|
||
|
|
;
|
||
|
|
;--
|
||
|
|
|
||
|
|
NESTED_ENTRY SwapContext, _TEXT$00
|
||
|
|
|
||
|
|
push_reg rbp ; save nonvolatile register
|
||
|
|
alloc_stack (KSWITCH_FRAME_LENGTH - (2 * 8)) ; allocate stack frame
|
||
|
|
|
||
|
|
END_PROLOGUE
|
||
|
|
|
||
|
|
mov SwNpxSave[rsp], al ; save NPX save
|
||
|
|
mov SwApcBypass[rsp], cl ; save APC bypass disable
|
||
|
|
|
||
|
|
;
|
||
|
|
; Set the new thread state to running.
|
||
|
|
;
|
||
|
|
; N.B. The state of the new thread MUST be set to running before releasing
|
||
|
|
; the dispatcher lock.
|
||
|
|
;
|
||
|
|
|
||
|
|
mov byte ptr ThState[rsi], Running ; set thread state to running
|
||
|
|
|
||
|
|
;
|
||
|
|
; Acquire the context swap lock so the address space of the previous process
|
||
|
|
; cannot be deleted, then release the dispatcher database lock.
|
||
|
|
;
|
||
|
|
; N.B. The context swap lock is used to protect the address space until the
|
||
|
|
; context switch has sufficiently progressed to the point where the
|
||
|
|
; previous process address space is no longer needed. This lock is also
|
||
|
|
; acquired by the reaper thread before it finishes thread termination.
|
||
|
|
;
|
||
|
|
|
||
|
|
|
||
|
|
ifndef NT_UP
|
||
|
|
|
||
|
|
test edx, edx ; test if call from idle thread
|
||
|
|
jnz short KiSC05 ; if nz, call from idle thread
|
||
|
|
lea rcx, PbLockQueue + (16 * LockQueueContextSwapLock)[rbx] ; lock queue
|
||
|
|
call KeAcquireQueuedSpinLockAtDpcLevel ; acquire context swap lock
|
||
|
|
lea rcx, PbLockQueue + (16 * LockQueueDispatcherLock)[rbx] ; lock queue
|
||
|
|
call KeReleaseQueuedSpinLockFromDpcLevel ; release dispatcher lock
|
||
|
|
|
||
|
|
endif
|
||
|
|
|
||
|
|
;
|
||
|
|
; Check if an attempt is being made to context switch while in a DPC routine.
|
||
|
|
;
|
||
|
|
|
||
|
|
KiSC05: cmp dword ptr PbDpcRoutineActive[rbx], 0 ; check if DPC active
|
||
|
|
jne KiSC60 ; if ne, DPC is active
|
||
|
|
|
||
|
|
;
|
||
|
|
; Accumulate the total time spent in a thread.
|
||
|
|
;
|
||
|
|
|
||
|
|
ifdef PERF_DATA
|
||
|
|
|
||
|
|
rdtsc ; read cycle counter
|
||
|
|
sub eax, PbThreadStartCount + 0[rbx] ; sub out thread start time
|
||
|
|
sbb edx, PbThreadStartCount + 4[rbx] ;
|
||
|
|
add EtPerformanceCountLow[rdi], eax ; accumlate thread run time
|
||
|
|
adc EtPerformanceCountHigh[rdi], edx ;
|
||
|
|
add PbThreadStartCount + 4[rbx], eax ; set new thread start time
|
||
|
|
adc PbThreadStartCount + 8[rbx], edx ;
|
||
|
|
|
||
|
|
endif
|
||
|
|
|
||
|
|
;
|
||
|
|
; Save the kernel mode XMM control/status register. If the current thread
|
||
|
|
; executes in user mode, then also save the legacy floating point state.
|
||
|
|
;
|
||
|
|
|
||
|
|
stmxcsr SwMxCsr[rsp] ; save kernel mode XMM control/status
|
||
|
|
cmp byte ptr ThNpxState[rdi], UserMode ; check if user mode thread
|
||
|
|
jne short KiSC10 ; if ne, not user mode thread
|
||
|
|
mov rbp, ThInitialStack[rdi] ; get previous thread initial stack
|
||
|
|
cmp byte ptr SwNpxSave[rsp], TRUE ; check if full save required
|
||
|
|
jne short KiSC07 ; if ne, full save not required
|
||
|
|
fnsaved [rbp] ; save full legacy floating point state
|
||
|
|
jmp short KiSC10 ;
|
||
|
|
|
||
|
|
;
|
||
|
|
; Full floating save not required.
|
||
|
|
;
|
||
|
|
|
||
|
|
KiSC07: fnstenvd [rbp] ; save legacy floating environment
|
||
|
|
|
||
|
|
;
|
||
|
|
; Switch kernel stacks.
|
||
|
|
;
|
||
|
|
|
||
|
|
KiSC10: mov ThKernelStack[rdi], rsp ; save old kernel stack pointer
|
||
|
|
mov rsp, ThKernelStack[rsi] ; get new kernel stack pointer
|
||
|
|
|
||
|
|
;
|
||
|
|
; Swap the process address space if the new process is not the same as the
|
||
|
|
; previous process.
|
||
|
|
;
|
||
|
|
|
||
|
|
mov rax, ThApcState + AsProcess[rdi] ; get previous process address
|
||
|
|
cmp rax, ThApcState + AsProcess[rsi] ; check if process address match
|
||
|
|
je short KiSC20 ; if e, process addresses match
|
||
|
|
mov r14, ThApcState + AsProcess[rsi] ; get new process address
|
||
|
|
|
||
|
|
;
|
||
|
|
; Update the processor set masks.
|
||
|
|
;
|
||
|
|
|
||
|
|
ifndef NT_UP
|
||
|
|
|
||
|
|
mov rcx, PbSetMember[rbx] ; get processor set member
|
||
|
|
xor PrActiveProcessors[rax], rcx ; clear bit in previous set
|
||
|
|
xor PrActiveProcessors[r14], rcx ; set bit in new set
|
||
|
|
|
||
|
|
if DBG
|
||
|
|
|
||
|
|
test PrActiveProcessors[rax], rcx ; test if bit clear in previous set
|
||
|
|
jnz short @f ; if nz, bit not clear in previous set
|
||
|
|
test PrActiveProcessors[r14], rcx ; test if bit set in new set
|
||
|
|
jnz short KiSC15 ; if nz, bit set in new set
|
||
|
|
@@: int 3 ; debug break - incorrect active mask
|
||
|
|
|
||
|
|
endif
|
||
|
|
|
||
|
|
endif
|
||
|
|
|
||
|
|
;
|
||
|
|
; Load new CR3 value which will flush the TB and set the IOPM map offset in
|
||
|
|
; the TSS.
|
||
|
|
;
|
||
|
|
|
||
|
|
KiSC15: mov r15, gs:[PcTss] ; get processor TSS address
|
||
|
|
mov cx, PrIopmOffset[r14] ; get process IOPM offset
|
||
|
|
mov TssIoMapBase[r15], cx ; set TSS IOPM offset
|
||
|
|
mov rax, PrDirectoryTableBase[r14] ; get new directory base
|
||
|
|
mov cr3, rax ; flush TLB and set new directory base
|
||
|
|
|
||
|
|
;
|
||
|
|
; Release the context swap lock.
|
||
|
|
;
|
||
|
|
|
||
|
|
KiSC20: mov byte ptr ThIdleSwapBlock[rdi], 0 ; unblock swap from idle
|
||
|
|
|
||
|
|
ifndef NT_UP
|
||
|
|
|
||
|
|
lea rcx, PbLockQueue + (16 * LockQueueContextSwapLock)[rbx] ; lock queue
|
||
|
|
call KeReleaseQueuedSpinLockFromDpcLevel ; release context swap lock
|
||
|
|
|
||
|
|
endif
|
||
|
|
|
||
|
|
;
|
||
|
|
; Set the new kernel stack base in the TSS.
|
||
|
|
;
|
||
|
|
|
||
|
|
mov r15, gs:[PcTss] ; get processor TSS address
|
||
|
|
mov rbp, ThInitialStack[rsi] ; get new stack base address
|
||
|
|
mov TssRsp0[r15], rbp ; set stack base address in TSS
|
||
|
|
|
||
|
|
;
|
||
|
|
; If the new thread executes in user mode, then restore the legacy floating
|
||
|
|
; state, load the compatibility mode TEB address, load the native user mode
|
||
|
|
; TEB address, and reload the segment registers if needed.
|
||
|
|
;
|
||
|
|
; N.B. The upper 32-bits of the compatibility mode TEB address are always
|
||
|
|
; zero.
|
||
|
|
;
|
||
|
|
|
||
|
|
cmp byte ptr ThNpxState[rsi], UserMode ; check if user mode thread
|
||
|
|
jne KiSC30 ; if ne, not user mode thread
|
||
|
|
cmp byte ptr SwNpxSave[rsp], TRUE ; check if full restore required
|
||
|
|
jne short KiSC22 ; if ne, full restore not required
|
||
|
|
mov cx, LfControlWord[rbp] ; save current control word
|
||
|
|
mov word ptr LfControlWord[rbp], 03fh ; set to mask all exceptions
|
||
|
|
frstord [rbp] ; restore legacy floating point state
|
||
|
|
mov LfControlWord[rbp], cx ; restore control word
|
||
|
|
fldcw word ptr LfControlWord[rbp] ; load legacy control word
|
||
|
|
jmp short KiSC24 ;
|
||
|
|
|
||
|
|
;
|
||
|
|
; Full legacy floating restore not required.
|
||
|
|
;
|
||
|
|
|
||
|
|
KiSC22: fldenv [rbp] ; restore legacy floating environment
|
||
|
|
|
||
|
|
;
|
||
|
|
; Set base of compatibility mode TEB.
|
||
|
|
;
|
||
|
|
|
||
|
|
KiSC24: mov eax, ThTeb[rsi] ; compute compatibility mode TEB address
|
||
|
|
add eax, CmThreadEnvironmentBlockOffset ;
|
||
|
|
mov rcx, gs:[PcGdt] ; get GDT base address
|
||
|
|
mov KgdtBaseLow + KGDT64_R3_CMTEB[rcx], ax ; set CMTEB base address
|
||
|
|
shr eax, 16 ;
|
||
|
|
mov KgdtBaseMiddle + KGDT64_R3_CMTEB[rcx], al ;
|
||
|
|
mov KgdtBaseHigh + KGDT64_R3_CMTEB[rcx], ah ;
|
||
|
|
|
||
|
|
;
|
||
|
|
; If the user segment selectors have been changed, then reload them with
|
||
|
|
; their cannonical values.
|
||
|
|
;
|
||
|
|
|
||
|
|
mov ax, ds ; compute sum of segment selectors
|
||
|
|
mov cx, es ;
|
||
|
|
add ax, cx ;
|
||
|
|
mov cx, gs ;
|
||
|
|
add ax, cx ;
|
||
|
|
cmp ax, ((KGDT64_R3_DATA or RPL_MASK) * 3) ; check if sum matches
|
||
|
|
je short KiSC25 ; if e, sum matches expected value
|
||
|
|
mov cx, KGDT64_R3_DATA or RPL_MASK ; reload user segment selectors
|
||
|
|
mov ds, cx ;
|
||
|
|
mov es, cx ;
|
||
|
|
|
||
|
|
;
|
||
|
|
; N.B. The following reload of the GS selector destroys the system MSR_GS_BASE
|
||
|
|
; register. Thus this sequence must be done with interrupt off.
|
||
|
|
;
|
||
|
|
|
||
|
|
mov eax, gs:[PcSelf] ; get current PCR address
|
||
|
|
mov edx, gs:[PcSelf + 4] ;
|
||
|
|
cli ; disable interrupts
|
||
|
|
mov gs, cx ; reload GS segment selector
|
||
|
|
mov ecx, MSR_GS_BASE ; get GS base MSR number
|
||
|
|
wrmsr ; write system PCR base address
|
||
|
|
sti ; enable interrupts
|
||
|
|
KiSC25: mov ax, KGDT64_R3_CMTEB or RPL_MASK ; reload FS segment selector
|
||
|
|
mov fs, ax ;
|
||
|
|
mov eax, ThTeb[rsi] ; get low part of user TEB address
|
||
|
|
mov edx, ThTeb + 4[rsi] ; get high part of user TEB address
|
||
|
|
mov gs:[PcTeb], eax ; set user TEB address in PCR
|
||
|
|
mov gs:[PcTeb + 4], edx ;
|
||
|
|
mov ecx, MSR_GS_SWAP ; get GS base swap MSR number
|
||
|
|
wrmsr ; write user TEB base address
|
||
|
|
|
||
|
|
;
|
||
|
|
; Restore kernel mode XMM control/status and update context switch counters.
|
||
|
|
;
|
||
|
|
|
||
|
|
KiSC30: ldmxcsr SwMxCsr[rsp] ; kernel mode XMM control/status
|
||
|
|
inc dword ptr ThContextSwitches[rsi] ; thread count
|
||
|
|
inc dword ptr PbContextSwitches[rbx] ; processor count
|
||
|
|
|
||
|
|
;
|
||
|
|
; If the new thread has a kernel mode APC pending, then request an APC
|
||
|
|
; interrupt if APC bypass is disabled.
|
||
|
|
;
|
||
|
|
|
||
|
|
mov al, ThApcState + AsKernelApcPending[rsi] ; get APC pending
|
||
|
|
test al, al ; test if kernel APC pending
|
||
|
|
jz short KiSC50 ; if z, kernel APC not pending
|
||
|
|
cmp byte ptr SwApcBypass[rsp], APC_LEVEL ; check if APC bypass enabled
|
||
|
|
jb short KiSC40 ; if b, APC bypass is enabled
|
||
|
|
mov cl, APC_LEVEL ; request APC interrupt
|
||
|
|
call __imp_HalRequestSoftwareInterrupt ;
|
||
|
|
clc ; clear carry flag
|
||
|
|
KiSC40: setb al ; set return value
|
||
|
|
KiSC50: add rsp, KSWITCH_FRAME_LENGTH - (2 * 8) ; deallocate stack frame
|
||
|
|
pop rbp ; restore nonvolatile register
|
||
|
|
ret ; return
|
||
|
|
|
||
|
|
;
|
||
|
|
; An attempt is being made to context switch while in a DPC routine. This is
|
||
|
|
; most likely caused by a DPC routine calling one of the wait functions.
|
||
|
|
;
|
||
|
|
|
||
|
|
KiSC60: mov ecx, ATTEMPTED_SWITCH_FROM_DPC ; set bug check code
|
||
|
|
call KeBugCheck ; bug check system - no return
|
||
|
|
ret ; return
|
||
|
|
|
||
|
|
NESTED_END SwapContext, _TEXT$00
|
||
|
|
|
||
|
|
end
|