526 lines
14 KiB
C
526 lines
14 KiB
C
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/*++
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Module Name:
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iA32DEF.H
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Abstract:
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This file defines iA32 macros for iA32Trap.c and Opcode Emulation use
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Author:
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#define KERNELONLY 1
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// #include ks386.inc
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// #include callconv.inc // calling convention macros
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// #include i386\kimacro.inc
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// #include mac386.inc
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// #include i386\mi.inc
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//
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// Equates for exceptions which cause system fatal error
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//
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#define EXCEPTION_DIVIDED_BY_ZERO 0
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#define EXCEPTION_DEBUG 1
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#define EXCEPTION_NMI 2
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#define EXCEPTION_INT3 3
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#define EXCEPTION_BOUND_CHECK 5
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#define EXCEPTION_INVALID_OPCODE 6
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#define EXCEPTION_NPX_NOT_AVAILABLE 7
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#define EXCEPTION_DOUBLE_FAULT 8
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#define EXCEPTION_NPX_OVERRUN 9
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#define EXCEPTION_INVALID_TSS 0x0A
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#define EXCEPTION_SEGMENT_NOT_PRESENT 0x0B
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#define EXCEPTION_STACK_FAULT 0x0C
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#define EXCEPTION_GP_FAULT 0x0D
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#define EXCEPTION_RESERVED_TRAP 0x0F
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#define EXCEPTION_NPX_ERROR 0x010
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#define EXCEPTION_ALIGNMENT_CHECK 0x011
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#define BREAKPOINT_BREAK 0x00
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//
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// Exception flags
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//
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#define EXCEPT_UNKNOWN_ACCESS 0
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#define EXCEPT_LIMIT_ACCESS 0x10
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//
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// page fault read/write mask
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//
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#define ERR_0E_STORE 2
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//
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// Debug register 6 (dr6) BS (single step) bit mask
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//
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#define DR6_BS_MASK 0x4000
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//
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// EFLAGS single step bit
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//
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#define EFLAGS_TF_BIT 0x100
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#define EFLAGS_OF_BIT 0x4000
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//
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// The mask of selecot's table indicator (ldt or gdt)
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//
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#define TABLE_INDICATOR_MASK 4
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//
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// Opcode for Pop SegReg and iret instructions
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//
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#define POP_DS 0x01F
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#define POP_ES 0x07
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#define POP_FS 0x0A10F
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#define POP_GS 0x0A90F
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#define IRET_OP 0x0CF
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#define CLI_OP 0x0FA
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#define STI_OP 0x0FB
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#define PUSHF_OP 0x09C
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#define POPF_OP 0x09D
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#define INTNN_OP 0x00CD
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#define FRSTOR_ECX 0x0021DD9B
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#define FWAIT_OP 0x009b
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#define GATE_TYPE_386INT 0x0E00
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#define GATE_TYPE_386TRAP 0x0F00
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#define GATE_TYPE_TASK 0x0500
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#define D_GATE 0
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#define D_PRESENT 0x08000
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#define D_DPL_3 0x06000
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#define D_DPL_0 0
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//
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// Definitions for present 386 trap and interrupt gate attributes
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//
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#define D_TRAP032 D_PRESENT+D_DPL_0+D_GATE+GATE_TYPE_386TRAP
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#define D_TRAP332 D_PRESENT+D_DPL_3+D_GATE+GATE_TYPE_386TRAP
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#define D_INT032 D_PRESENT+D_DPL_0+D_GATE+GATE_TYPE_386INT
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#define D_INT332 D_PRESENT+D_DPL_3+D_GATE+GATE_TYPE_386INT
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#define D_TASK D_PRESENT+D_DPL_0+D_GATE+GATE_TYPE_TASK
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//
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// Bit patterns for Intercept_Code or Trap_Code,
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// patterns used in IIM on IA32 trap
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//
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#define TRAPCODE_TB 0x0004 // taken branch trap
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#define TRAPCODE_SS 0x0008 // single step trap
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#define TRAPCODE_B0 0x0010 // Data breakpoint trap
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#define TRAPCODE_B1 0x0020
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#define TRAPCODE_B2 0x0040
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#define TRAPCODE_B3 0x0080
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#define INTERCEPT_OS 0x0002 // Operand size
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#define INTERCEPT_AS 0x0004 // Address size
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#define INTERCEPT_LP 0x0008 // Lock Prefix
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#define INTERCEPT_RP 0x0010 // REP prefix
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#define INTERCEPT_NP 0x0020 // REPNE prefix
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#define INTERCEPT_SP 0x0040 // Segment prefix
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#define INTERCEPT_SEG 0x0380 // Segment valuse
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#define INTERCEPT_0F 0x0400 // 0F opcode series
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#define HARDWARE_VM 0x0800 // VM86 mode
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#define HARDWARE_RM 0x1000 // Real Mode
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#define HARDWARE_PM 0x2000 // Protect Mode
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#define HARDWARE_SS 0x4000 // Stack size, 32 or 16 bits
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#define HARDWARE_UR 0x8000 // User or privileged mode
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#define MI_SMSW 0x01
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#define MI_SMSW_REGOP 0x20
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//
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// Following MI_*** definitions are created from MI386.INC
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//
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#define MAX_INSTRUCTION_LENGTH 15
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#define MAX_INSTRUCTION_PREFIX_LENGTH 4
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#define MI_LOCK_PREFIX 0x0F0
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#define MI_REPNE_PREFIX 0x0F2
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#define MI_REP_PREFIX 0x0F3
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#define MI_SEGCS_PREFIX 0x02E
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#define MI_SEGSS_PREFIX 0x036
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#define MI_SEGDS_PREFIX 0x03E
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#define MI_SEGES_PREFIX 0x026
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#define MI_SEGFS_PREFIX 0x064
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#define MI_SEGGS_PREFIX 0x065
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#define MI_OPERANDSIZE_PREFIX 0x066
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#define MI_ADDRESSOVERRIDE_PREFIX 0x067
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#define MI_TWO_BYTE 0x0F
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#define MI_HLT 0x0F4
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#define MI_LTR_LLDT 0
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#define MI_LGDT_LIDT_LMSW 0x01
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#define MI_MODRM_MASK 0x38
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#define MI_LLDT_MASK 0x10
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#define MI_LTR_MASK 0x18
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#define MI_LGDT_MASK 0x10
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#define MI_LIDT_MASK 0x18
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#define MI_LMSW_MASK 0x30
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#define MI_SPECIAL_MOV_MASK 0x20
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#define MI_REP_INS_OUTS 0x0F3
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#define MI_MIN_INS_OUTS 0x06C
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#define MI_MAX_INS_OUTS 0x06F
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#define MI_LMSW_OPCODE 0x001 // second byte of lmsw
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#define MI_CLTS_OPCODE 0x006 // second byte of clts
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#define MI_GET_CRx_OPCODE 0x020 // mov r32,CRx
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#define MI_SET_CRx_OPCODE 0x022 // mov CRx,r32
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#define MI_GET_TRx_OPCODE 0x024 // mov r32,TRx
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#define MI_SET_TRx_OPCODE 0x026 // mov TRx,r32
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#define MI_REGMASK 0x038 // REG field mask
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#define MI_REGSHIFT 0x3 // REG field shift
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#define MI_REGLMSW 0x030 // REG field for lmsw
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#define MI_MODMASK 0x0C0 // MOD field mask
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#define MI_MODSHIFT 0x6 // MOD field shift
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#define MI_MODMOVSPEC 0x0C0 // MOD field for mov to/from special
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#define MI_MODNONE 0
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#define MI_RMMASK 0x007 // RM field mask
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#define MI_RMBP 0x006 // RM value for bp reg
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#define MI_RMSIB 0x004 // RM value for sib
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#define MI_SIB_BASEMASK 0x007 // SIB BASE field mask
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#define MI_SIB_BASENONE 0x005
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#define MI_SIB_BASESHIFT 0
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#define MI_SIB_INDEXMASK 0x038
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#define MI_SIB_INDEXSHIFT 3
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#define MI_SIB_INDEXNONE 0x020
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#define MI_SIB_SSMASK 0x0c0
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#define MI_SIB_SSSHIFT 0x6
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//
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// definition for floating status word error mask
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//
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#define FSW_INVALID_OPERATION 0x0001
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#define FSW_DENORMAL 0x0002
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#define FSW_ZERO_DIVIDE 0x0004
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#define FSW_OVERFLOW 0x0008
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#define FSW_UNDERFLOW 0x0010
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#define FSW_PRECISION 0x0020
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#define FSW_STACK_FAULT 0x0040
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#define FSW_ERROR_SUMMARY 0x0080
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#define FSW_CONDITION_CODE_0 0x0100
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#define FSW_CONDITION_CODE_1 0x0200
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#define FSW_CONDITION_CODE_2 0x0400
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#define FSW_CONDITION_CODE_3 0x4000
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#define FSW_ERR_MASK (FSW_INVALID_OPERATION | FSW_DENORMAL | FSW_ZERO_DIVIDE | FSW_OVERFLOW | FSW_UNDERFLOW | FSW_PRECISION | FSW_STACK_FAULT)
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//
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// Definitions of the shifts to get to the katmai status and control
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// Once the bits are shifted, they are in the same place as the
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// 387 status and control, so the masks above work as well
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// See the IA64 Application Architecture (Vol 1) for where the
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// bit shift values come from
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//
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#define KATMAI_SHIFT_CONTROL 39
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#define KATMAI_SHIFT_STATUS 32
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#define CPL_STATE(SegCs) (SegCs & RPL_MASK)
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// Use the IIPA since that points to the start of the ia32 instruction
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#define EIP(frame) ((ULONG) (frame)->StIIPA & 0xffffffff)
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#define ESP(frame) ((ULONG) (frame)->IntSp & 0xffffffff)
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#define ECX(frame) ((ULONG) (frame)->IntT2 & 0xffffffff)
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#define EDX(frame) ((ULONG) (frame)->IntT3 & 0xffffffff)
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#define ISRCode(frame) ((USHORT) ((frame)->StISR) & 0xffff)
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#define ISRVector(frame) ((UCHAR) ((frame)->StISR >> 16) & 0xff)
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//
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// Helpers for instruction decoding
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//
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BOOLEAN
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KiIa32Compute32BitEffectiveAddress (
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IN PKTRAP_FRAME Frame,
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IN OUT PUCHAR *InstAddr,
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OUT PUINT_PTR Addr,
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OUT PBOOLEAN RegisterMode
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);
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NTSTATUS
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KiIa32InterceptUnalignedLock (
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IN PKTRAP_FRAME TrapFrame
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);
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NTSTATUS
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KiIa32ValidateInstruction (
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IN PKTRAP_FRAME TrapFrame
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);
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//
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// The following register indices are valid only if called through
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// GetX86Reg (...)
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//
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#define IA32_REG_EAX 0
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#define IA32_REG_ECX 1
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#define IA32_REG_EDX 2
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#define IA32_REG_EBX 3
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#define IA32_REG_ESP 4
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#define IA32_REG_EBP 5
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#define IA32_REG_ESI 6
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#define IA32_REG_EDI 7
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#define IA32_DISP_NONE 0x00
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#define IA32_DISP8 0x01
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#define IA32_DISP16 0x02
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//
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// x86 Eflags register layout
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//
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typedef union _IA32_EFLAGS
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{
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ULONGLONG Value;
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struct
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{
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ULONGLONG cf : 1;
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ULONGLONG v1 : 1;
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ULONGLONG pf : 1;
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ULONGLONG v2 : 1;
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ULONGLONG af : 1;
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ULONGLONG v3 : 1;
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ULONGLONG zf : 1;
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ULONGLONG sf : 1;
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ULONGLONG tf : 1;
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ULONGLONG ifl : 1;
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ULONGLONG df : 1;
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ULONGLONG of : 1;
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ULONGLONG iopl : 2;
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ULONGLONG nt : 1;
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ULONGLONG v4 : 1;
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ULONGLONG rf : 1;
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ULONGLONG vm : 1;
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ULONGLONG ac : 1;
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ULONGLONG vif : 1;
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ULONGLONG vip : 1;
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ULONGLONG id : 1;
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} u;
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} IA32_EFLAGS, *PIA32_EFLAGS;
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//
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// Eflags bits to update
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//
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#define IA32_EFLAGS_CF 0x0001
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#define IA32_EFLAGS_SF 0x0002
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#define IA32_EFLAGS_OF 0x0004
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#define IA32_EFLAGS_PF 0x0008
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#define IA32_EFLAGS_ZF 0x0010
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#define IA32_EFLAGS_AF 0x0020
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//
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// Operand size
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//
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typedef enum _IA32_OPERAND_SIZE
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{
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OPERANDSIZE_NONE,
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OPERANDSIZE_ONEBYTE,
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OPERANDSIZE_TWOBYTES,
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OPERANDSIZE_FOURBYTES
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} IA32_OPERAND_SIZE;
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typedef enum _IA32_OPCODE_PARAMETERS
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{
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IA32_PARAM_RM8_IMM8,
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IA32_PARAM_RM_IMM,
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IA32_PARAM_RM_IMM8SIGN,
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IA32_PARAM_RM8_R,
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IA32_PARAM_RM_R,
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IA32_PARAM_R_RM8,
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IA32_PARAM_R_RM,
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IA32_PARAM_RM8,
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IA32_PARAM_RM,
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IA32_PARAM_SEGREG_RM8,
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IA32_PARAM_SEGREG_RM
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} IA32_OPCODE_PARAMETERS;
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//
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// Opcode decription
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//
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typedef struct _IA32_OPCODE_DESCRIPTION
|
||
|
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{
|
||
|
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|
||
|
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//
|
||
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// 1st, 2nd and 3rd byte. The 3rd byte is actually the /Reg bits
|
||
|
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//
|
||
|
|
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||
|
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UCHAR Byte1;
|
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|
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UCHAR Byte2;
|
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|
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UCHAR Byte3;
|
||
|
|
union
|
||
|
|
{
|
||
|
|
UCHAR Value;
|
||
|
|
struct
|
||
|
|
{
|
||
|
|
UCHAR Bytes : 4;
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||
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UCHAR RegOpcode : 4;
|
||
|
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} m;
|
||
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} Count;
|
||
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|
||
|
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//
|
||
|
|
// Parameter of this opcode
|
||
|
|
//
|
||
|
|
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||
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UCHAR Type;
|
||
|
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||
|
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//
|
||
|
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// Opcode
|
||
|
|
//
|
||
|
|
|
||
|
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UCHAR Opcode;
|
||
|
|
|
||
|
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} IA32_OPCODE_DESCRIPTION, *PIA32_OPCODE_DESCRIPTION;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Specific data structure to represent the lock-prefixed instruction
|
||
|
|
// operands and immediates.
|
||
|
|
//
|
||
|
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|
||
|
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typedef struct _IA32_OPERAND
|
||
|
|
{
|
||
|
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ULONG_PTR v;
|
||
|
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BOOLEAN RegisterMode;
|
||
|
|
} IA32_OPERAND, *PIA32_OPERAND;
|
||
|
|
|
||
|
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typedef union _IA32_PREFIX
|
||
|
|
{
|
||
|
|
ULONG Value;
|
||
|
|
|
||
|
|
struct _IA32_PREFIX_BITS
|
||
|
|
{
|
||
|
|
ULONG Lock : 1;
|
||
|
|
ULONG RepNe : 1;
|
||
|
|
ULONG Rep : 1;
|
||
|
|
ULONG CsOverride : 1;
|
||
|
|
ULONG SsOverride : 1;
|
||
|
|
ULONG DsOverride : 1;
|
||
|
|
ULONG EsOverride : 1;
|
||
|
|
ULONG FsOverride : 1;
|
||
|
|
ULONG GsOverride : 1;
|
||
|
|
ULONG SizeOverride : 1;
|
||
|
|
ULONG AddressOverride : 1;
|
||
|
|
} b;
|
||
|
|
|
||
|
|
} IA32_PREFIX, *PIA32_PREFIX;
|
||
|
|
|
||
|
|
typedef struct _IA32_INSTRUCTION
|
||
|
|
{
|
||
|
|
|
||
|
|
//
|
||
|
|
// Instruction EIP
|
||
|
|
//
|
||
|
|
|
||
|
|
PCHAR Eip;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Instruction description
|
||
|
|
//
|
||
|
|
|
||
|
|
PIA32_OPCODE_DESCRIPTION Description;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Eflags
|
||
|
|
//
|
||
|
|
|
||
|
|
IA32_EFLAGS Eflags;
|
||
|
|
|
||
|
|
|
||
|
|
//
|
||
|
|
// Instruction opcode
|
||
|
|
//
|
||
|
|
|
||
|
|
UCHAR Opcode;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Operands size and mask
|
||
|
|
//
|
||
|
|
|
||
|
|
UCHAR OperandSize;
|
||
|
|
ULONG OperandMask;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Instruction operands
|
||
|
|
//
|
||
|
|
|
||
|
|
IA32_OPERAND Operand1;
|
||
|
|
IA32_OPERAND Operand2;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Instruction prefixes
|
||
|
|
//
|
||
|
|
|
||
|
|
IA32_PREFIX Prefix;
|
||
|
|
|
||
|
|
|
||
|
|
} IA32_INSTRUCTION, *PIA32_INSTRUCTION;
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(IADBG)
|
||
|
|
ULONG IA32Debug = 0x000fffff;
|
||
|
|
|
||
|
|
#define IA32_DEBUG_INTERCEPTION 0x00000001
|
||
|
|
#define IA32_DEBUG_EXCEPTION 0x00000002
|
||
|
|
#define IA32_DEBUG_INTERRUPT 0x00000004
|
||
|
|
|
||
|
|
#define IA32_DEBUG_DIVIDE 0x00000010
|
||
|
|
#define IA32_DEBUG_DEBUG 0x00000020
|
||
|
|
#define IA32_DEBUG_OVERFLOW 0x00000040
|
||
|
|
#define IA32_DEBUG_BOUND 0x00000080
|
||
|
|
#define IA32_DEBUG_INSTRUCTION 0x00000100
|
||
|
|
#define IA32_DEBUG_NODEVICE 0x00000200
|
||
|
|
#define IA32_DEBUG_NOTPRESENT 0x00000400
|
||
|
|
#define IA32_DEBUG_STACK 0x00000800
|
||
|
|
#define IA32_DEBUG_GPFAULT 0x00001000
|
||
|
|
#define IA32_DEBUG_FPFAULT 0x00002000
|
||
|
|
#define IA32_DEBUG_ALIGNMENT 0x00004000
|
||
|
|
#define IA32_DEBUG_GATE 0x00008000
|
||
|
|
#define IA32_DEBUG_BREAK 0x00010000
|
||
|
|
#define IA32_DEBUG_INTNN 0x00020000
|
||
|
|
#define IA32_DEBUG_FLAG 0x00040000
|
||
|
|
#define IA32_DEBUG_LOCK 0x00080000
|
||
|
|
//
|
||
|
|
// define debug macro
|
||
|
|
//
|
||
|
|
#define IF_IA32TRAP_DEBUG( ComponentFlag ) \
|
||
|
|
if (IA32Debug & (IA32_DEBUG_ ## ComponentFlag))
|
||
|
|
|
||
|
|
|
||
|
|
#else // IADBG
|
||
|
|
|
||
|
|
#define IF_IA32TRAP_DEBUG( ComponentFlag ) if (FALSE)
|
||
|
|
|
||
|
|
#endif // IADBG
|