556 lines
16 KiB
C
556 lines
16 KiB
C
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//
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// INTEL CORPORATION PROPRIETARY INFORMATION
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// This software is supplied under the terms of a license agreement or
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// nondisclosure agreement with Intel Corporation and may not be copied
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// or disclosed except in accordance with the terms of that agreement.
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// Copyright (c) 1996 Intel Corporation. All Rights Reserved.
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//
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// Workfile: BERT.H
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//
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// Purpose:
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// This header contains the defines for the Bert Gate Array Asic
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// registers and functions
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//
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// Contents:
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//
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#ifndef _BERT_H_
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#define _BERT_H_
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// Bert register offsets
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#define BERT_CAPSTAT_REG 0x00
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#define BERT_VINSTAT_REG 0x04
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#define BERT_INTSTAT_REG 0x08
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#define BERT_INTRST_REG 0x0c
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#define BERT_IIC_REG 0x10
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#define BERT_FIFOCFG_REG 0x14
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#define BERT_RPSADR_REG 0x18
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#define BERT_UALIMIT_REG 0x20
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#define BERT_LALIMIT_REG 0x24
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#define BERT_RPSPAGE_REG 0x28
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#define BERT_YPTR_REG 0x30
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#define BERT_UPTR_REG 0x34
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#define BERT_VPTR_REG 0x38
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#define BERT_YSTRIDE_REG 0x40
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#define BERT_USTRIDE_REG 0x44
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#define BERT_VSTRIDE_REG 0x48
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#define BERT_DALI_REG 0x50
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#define BERT_EEPROM_REG 0x60
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#define BERT_DMASTAT_REG 0x70
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#define BERT_TEST_REG 0x74
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// for Pistachio's Register 97-03-21(Fri)
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#define BERT_P_SKIP_REG 0x80
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#define BERT_P_ISIZ_REG 0x84
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#define BERT_P_OSIZ_REG 0x88
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#define BERT_P_LUMI_REG 0x8c
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#define BERT_P_COL_REG 0x90
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#define BERT_P_FILT_REG 0x94
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#define BERT_P_SUP1_REG 0x98
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#define BERT_P_SUP2_REG 0x9c
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#define BERT_P_SUP3_REG 0xa0
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#define BERT_BURST_LEN 0x9c // Insert 97-03-17(Mon)
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#define BERT_FER_REG 0xf0
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#define BERT_FEMR_REG 0xf4
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#define BERT_FPSR_REG 0xf8
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#define BERT_FECREG 0xfc
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// I2C status byte bits
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#define I2C_OFFSET 0x40
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#define I2CSTATUS_ALTD 0x02
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#define I2CSTATUS_FIDT 0x20
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#define I2CSTATUS_HLCK 0x40
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// INTSTAT Interrupt status register bit defines
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#define FIELD_INT 0x00000001
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#define RPS_INT 0x00000002
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#define SYNC_LOCK_INT 0x00000004
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#define SPARE_INT 0x00000008
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#define FIFO_OVERFLOW_INT 0x00000010
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#define LINE_TIMEOUT_INT 0x00000020
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#define RPS_OOB_INT 0x00000040
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#define REG_UNDEF_INT 0x00000080
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#define CODEC_INT 0x00000100
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#define SLOW_CLOCK_INT 0x00000200
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#define OVER_RUN_INT 0x00000400
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#define REG_LOAD_INT 0x00000800
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#define LINE_SYNC_INT 0x00001000
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#define IIC_ERROR_INT 0x00002000
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#define PCI_PARITY_ERROR_INT 0x00004000
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#define PCI_ACCESS_ERROR_INT 0x00008000
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// INSTAT Interrupt enable OR mask bits
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#define FIELD_INT_MASK 0x00010000
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#define RPS_INT_MASK 0x00020000
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#define SYNC_LOCK_INT_MASK 0x00040000
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#define SPARE_INT_MASK 0x00080000
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#define FIFO_OVERFLOW_INT_MASK 0x00100000
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#define LINE_TIMEOUT_INT_MASK 0x00200000
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#define RPS_OOB_INT_MASK 0x00400000
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#define REG_UNDEF_INT_MASK 0x00800000
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#define CODEC_INT_MASK 0x01000000
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#define SLOW_CLOCK_INT_MASK 0x02000000
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#define OVER_RUN_INT_MASK 0x04000000
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#define REG_LOAD_INT_MASK 0x08000000
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#define LINE_SYNC_INT_MASK 0x10000000
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#define IIC_ERROR_INT_MASK 0x20000000
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#define PCI_PARITY_ERROR_INT_MASK 0x40000000
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#define PCI_ACCESS_ERROR_INT_MASK 0x80000000
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// INTRST Interrupt ReSeT Register bits
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// reset bits
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#define FIELD_INT_RESET 0x00000001
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#define RPS_INT_RESET 0x00000002
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#define SYNC_LOCK_INT_RESET 0x00000004
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#define SPARE_INT_RESET 0x00000008
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#define FIFO_OVERFLOW_INT_RESET 0x00000010
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#define LINE_TIMEOUT_INT_RESET 0x00000020
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#define RPS_OOB_INT_RESET 0x00000040
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#define REG_UNDEF_INT_RESET 0x00000080
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#define SLOW_CLOCK_INT_RESET 0x00000200
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#define OVER_RUN_INT_RESET 0x00000400
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#define REG_LOAD_INT_RESET 0x00000800
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#define LINE_SYNC_INT_RESET 0x00001000
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#define IIC_ERROR_INT_RESET 0x00002000
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#define PCI_PARITY_ERROR_INT_RESET 0x00004000
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#define PCI_ACCESS_ERROR_INT_RESET 0x00008000
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// set bits
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#define FIELD_INT_SET 0x00010000
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#define RPS_INT_SET 0x00020000
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#define SYNC_LOCK_INT_SET 0x00040000
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#define SPARE_INT_SET 0x00080000
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#define FIFO_OVERFLOW_INT_SET 0x00100000
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#define LINE_TIMEOUT_INT_SET 0x00200000
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#define RPS_OOB_INT_SET 0x00400000
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#define REG_UNDEF_INT_SET 0x00800000
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#define SLOW_CLOCK_INT_SET 0x02000000
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#define OVER_RUN_INT_SET 0x04000000
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#define REG_LOAD_INT_SET 0x08000000
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#define LINE_SYNC_INT_SET 0x10000000
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#define IIC_ERROR_INT_SET 0x20000000
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#define PCI_PARITY_ERROR_INT_SET 0x40000000
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#define PCI_ACCESS_ERROR_INT_SET 0x80000000
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#define TEST_MAKE_VORLON1 0x10000000
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//
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// The following values for the FIFO trip points and giving unlimited
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// PCI bus master access is reasonable for all platforms.
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//
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#define BERT_DEF_TRIP_POINTS 16
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#define BERT_DEF_PCI_BURST_LEN 3
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typedef struct _RPS_COMMAND
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{
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union
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{
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struct
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{
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ULONG RegisterOffset:8;
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ULONG Reserved:19;
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ULONG FWait:1;
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ULONG Edge:1;
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ULONG Int:1;
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ULONG ReadWrite:1;
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ULONG Continue:1;
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} bits;
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ULONG AsULONG;
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} u;
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ULONG Argument;
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} RPS_COMMAND, *PRPS_COMMAND;
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#define RPS_COMMAND_CONT 0x80000000
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#define RPS_COMMAND_STOP 0x00000000
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#define RPS_COMMAND_READ 0x40000000
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#define RPS_COMMAND_WRITE 0x00000000
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#define RPS_COMMAND_INT 0x20000000
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#define RPS_COMMAND_NOINT 0x00000000
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#define RPS_COMMAND_RISE_EDGE 0x10000000
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#define RPS_COMMAND_FALL_EDGE 0x00000000
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#define RPS_COMMAND_FWAIT 0x00000000
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#define RPS_COMMAND_DEFAULT (RPS_COMMAND_STOP | RPS_COMMAND_WRITE | \
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RPS_COMMAND_RISE_EDGE | RPS_COMMAND_FWAIT | \
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RPS_COMMAND_NOINT)
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// RPS COMMAND
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#define RPS_CONTINUE_CMD 0x80000000
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#define RPS_READ_CMD 0x40000000
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#define RPS_INT_CMD 0x20000000
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// Enable bits for the CAPSTAT register
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#define RST 0x80000000 // Reset front end.
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#define EBMV 0x10000000 // Enable Bus Master Video (i.e. DMA)
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#define EREO 0x04000000 // Enable RPS Even
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#define EROO 0x02000000 // Enable RPS Odd
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#define LOCK 0x00002000 // Sync Lock
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#define RPSS 0x00001000 // RPS Status
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#define GO0 0x00000010 // Power to camara
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#define CKRE 0x00000008 // Clock Run Enable // Add 97-05-08
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#define CKMD 0x00000004 // Clock Request Mode // Add 97-05-08
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#define ERPS 0x08000000 // Enable RPS
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#define FEMR_ENABLE 0x00008000
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#define CAMARA_OFF RST
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//#define PASSIVE_ENABLE (ERPS | GO0)
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//#define CAPTURE_EVEN (ERPS | EREO | GO0 | EBMV)
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//#define CAPTURE_ODD (ERPS | EROO | GO0 | EBMV)
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//#define SKIP_EVEN (ERPS | EREO | GO0)
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//#define SKIP_ODD (ERPS | EROO | GO0)
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#define PASSIVE_ENABLE ERPS // DEL GO0 97-04-07(Mon) BUN
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#define CAPTURE_EVEN (ERPS | EBMV) // DEL EREO ZGO0 97-04-07(Mon) BUN
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#define CAPTURE_ODD (ERPS | EBMV) // mode 97-03-29(Sat) BUN
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#define SKIP_EVEN ERPS // DEL EREO ZGO0 97-04-07(Mon) BUN
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#define SKIP_ODD ERPS // DEL EROO ZGO0 97-04-07(Mon) BUN
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// Bit positions for the INTSTAT register's ENABLE flags.
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#define FIE 0x10000 // Field Interrupt Enable
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#define RIE 0x20000 // RPS Interrupt Enable
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#define SLIE 0x40000 // Sync Lock Interrupt Enable
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#define EXIE 0x80000 // External interrupt Enable(Dilbert)
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#define SPIE 0x80000 // Spare Interrupt Enable(Bert).
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#define FOIE 0x100000 // FIFO Overflow Interrupt Enable.
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#define LTIE 0x200000 // LINE Timeout Interrupt Enable.
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#define ROIE 0x400000 // RPS Out of Bounds Interrupt Enable.
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#define RUIE 0x800000 // Register Undefined Interrupt Enable.
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#define SCIE 0x2000000 // Slock Clock Interrupt Enable.
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#define ORIE 0x4000000 // Over Run Interrupt Enable.
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#define RLIE 0x8000000 // Register Load Interrupt Enable.
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#define DEIE 0x10000000 // DCI Error Interrupt Enable(Dilbert).
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#define LSIE 0x10000000 // Line Sync Interrupt Enable(Bert).
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#define IEIE 0x20000000 // IIC Error Interrupt Enable.
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#define PPIE 0x40000000 // PCI Parity Error Interrupt Enable.
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#define PEIE 0x80000000 // PCI Access Error Interrupt Enable.
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// The active video capture interrupts mask
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//#define ACTIVE_CAPTURE_IRQS (RIE | SLIE | FOIE | ROIE | RUIE |\
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// ORIE | RLIE | IEIE | PPIE | PEIE)
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// delete PPIE & IEIE & ORIE 97-03-15(Sat)
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// Pistachi not support to PPIE and ORIE. Santaclara does not use I2c bus.
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#define ACTIVE_CAPTURE_IRQS (RIE | SLIE | FOIE | LTIE | ROIE | RUIE | RLIE | PEIE)
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// for Pistachio's flags 97-03-21(Fri)
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#define CHGCOL 0x00010000 // P_LUMI Change Color
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#define VFL 0x00010000 // P_FIL Vertical Filter
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#define EI_H 0x00000001 // P_SUP1 EI Level H
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#define EI_L 0x00000000 // P_SUP1 EI Level L
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#define EICH_2 0x00000000 // P_SUP1 EICH 2ms
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#define EICH_10 0x00000010 // P_SUP1 EICH 10ms
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#define EICH_50 0x00000020 // P_SUP1 EICH 50ms
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#define EICH_NONE 0x00000030 // P_SUP1 EICH None
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#define MSTOPI 0x00000002 // P_SUP3 IIC Stop Not Auto
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#define HSIIC 0x00000001 // P_SUP3 IIC HighSpeed Mode
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#define VSNC 0x00000008 // VINSTAT VSNC
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//
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// define the video standard constants
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//
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#define NTSC_MAX_PIXELS_PER_LINE 640
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#define NTSC_MAX_LINES_PER_FIELD 240
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#define PAL_MAX_PIXELS_PER_LINE 768
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#define PAL_MAX_LINES_PER_FIELD 288
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#define NTSC_HORIZONTAL_START 3
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#define NTSC_VERTICAL_START 14
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#define PAL_HORIZONTAL_START NTSC_HORIZONTAL_START // Same as NTSC
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#define PAL_VERTICAL_START 19
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#define MAX_CAPTURE_BUFFER_SIZE ((640*480*12)/8)
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#define DEFAULT_CAPTURE_BUFFER_SIZE ((320*240*12)/8)
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//
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// frame timing, time between vsync interrupts
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//
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#define PAL_MICROSPERFRAME (1000L/25)
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#define NTSC_MICROSPERFRAME (1000L/30)
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//#define EBMV_TIMEOUT 200000 // 20 millisec
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#define EBMV_TIMEOUT 500000 // 20 millisec
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#define DEF_RPS_FRAMES 30 // 30 default fps
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#define CAMERA_OFF_TIME 5000 // StreamFini -> CameraOFF Add 97-05-03(Sat)
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#define CAMERA_FLAG_ON 0x01 // Add 97-05-10(Sat)
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#define CAMERA_FLAG_OFF 0x00 // Add 97-05-10(Sat)
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#define CAVCE_ON 0x01 // Add 97-05-10(Sat)
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#define CAVCE_OFF 0x00 // Add 97-05-10(Sat)
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#define ZV_ENABLE 0x01l // Add 97-05-10(Sat)
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#define ZV_DISABLE 0x00l // Add 97-05-10(Sat)
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#define ZV_GETSTATUS 0xffl // Add 97-05-10(Sat)
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#define ZV_ERROR 0xffl // Add 97-05-10(Sat)
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#define MODE_VFW 0x01 // Add 97-05-10(Sat)
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#define MODE_ZV 0x02 // Add 97-05-10(Sat)
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#define MAX_HUE 0xff
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#define DEFAULT_HUE 0x80
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#define MAX_HUE 0xff
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#define MAX_BRIGHTNESS 0xff
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#define MAX_CONTRAST 0xff
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#define MAX_SATURATION 0xff
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|
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|
|
#define IGNORE100msec 0x200000l
|
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|
|
#define PCI_CFGCCR 0x08 /* offset of Pistachio Configration/Revision */
|
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|
|
#define PCI_Wake_Up 0x40 /* offset of Pistachio Wake up */
|
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|
|
#define PCI_CFGWAK 0x40 /* offset of Pistachio Wake up */
|
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|
|
#define PCI_DATA_PATH 0x44 /* offset of Pistachio Data path */
|
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|
|
#define PCI_CFGPAT 0x44 /* offset of Pistachio Data path */
|
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|
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|
|
#define SELIZV_CFGPAT 0x2l
|
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|
|
#define ZVEN_CFGPAT 0x1l
|
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|
|
#define CAVCE_CFGPAT 0x10l
|
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|
|
#define CADTE_CFGPAT 0x20l
|
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|
|
#define PXCCE_CFGPAT 0x100l
|
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|
|
#define PXCSE_CFGPAT 0x200l
|
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|
|
#define PCIFE_CFGPAT 0x400l
|
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|
|
#define PCIME_CFGPAT 0x800l
|
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|
|
#define PCIDS_CFGPAT 0x1000l
|
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|
|
#define GPB_CFGPAT 0x30000l
|
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|
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|
|
#define CASL_CFGWAK 0x00010000l
|
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|
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|
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|
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|
|
VOID HW_ApmResume(PHW_DEVICE_EXTENSION);
|
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|
|
VOID HW_ApmSuspend(PHW_DEVICE_EXTENSION);
|
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|
|
VOID HW_SetFilter(PHW_DEVICE_EXTENSION, BOOL);
|
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|
|
ULONG HW_ReadFilter(PHW_DEVICE_EXTENSION, BOOL);
|
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|
|
BOOL
|
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|
|
SetupPCILT(PHW_DEVICE_EXTENSION pHwDevExt);
|
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|
|
|
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|
|
VOID
|
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|
|
InitializeConfigDefaults(PHW_DEVICE_EXTENSION pHwDevExt);
|
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|
|
|
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|
|
BOOL
|
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|
|
CameraChkandON(PHW_DEVICE_EXTENSION pHwDevExt, ULONG ulMode);
|
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|
|
|
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|
|
BOOL
|
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|
|
CameraChkandOFF(PHW_DEVICE_EXTENSION pHwDevExt, ULONG ulMode);
|
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|
|
|
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|
|
BOOL
|
|||
|
|
CheckCameraStatus(PHW_DEVICE_EXTENSION pHwDevExt); // Add 97-05-05(Mon)
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
SetZVControl(PHW_DEVICE_EXTENSION pHwDevExt, ULONG ulZVStatus); // Add 97-05-02(Fri)
|
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|
|
|
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|
|
VOID
|
|||
|
|
WriteRegUlong(PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
ULONG,
|
|||
|
|
ULONG);
|
|||
|
|
|
|||
|
|
VOID
|
|||
|
|
ReadModifyWriteRegUlong(PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
ULONG,
|
|||
|
|
ULONG,
|
|||
|
|
ULONG);
|
|||
|
|
|
|||
|
|
ULONG
|
|||
|
|
ReadRegUlong(PHW_DEVICE_EXTENSION pHwDevExt, ULONG);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
HWInit(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
VOID
|
|||
|
|
BertInterruptEnable(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
IN BOOL bStatus
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
VOID
|
|||
|
|
BertDMAEnable(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
IN BOOL bStatus
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
BertIsLocked(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
BertFifoConfig(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
IN ULONG dwFormat
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
BertInitializeHardware(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
VOID
|
|||
|
|
BertEnableRps(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
VOID
|
|||
|
|
BertDisableRps(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
BertIsCAPSTATReady(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
VOID
|
|||
|
|
BertVsncSignalWait(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
VOID
|
|||
|
|
BertDMARestart(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
BertBuildNodes(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
BertTriBuildNodes(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
BertIsCardIn(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
VOID
|
|||
|
|
BertSetDMCHE(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
ImageSetInputImageSize(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
IN PRECT pRect
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
ImageSetOutputImageSize(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
IN ULONG ulWidth,
|
|||
|
|
IN ULONG ulHeight
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
ImageSetChangeColorAvail(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
IN ULONG ulChgCol
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
ImageSetHueBrightnessContrastSat(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
ImageSetFilterInfo(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
IN ULONG ulVFL,
|
|||
|
|
IN ULONG ulFL1,
|
|||
|
|
IN ULONG ulFL2,
|
|||
|
|
IN ULONG ulFL3,
|
|||
|
|
IN ULONG ulFL4
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
ImageFilterON(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
ImageFilterOFF(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
ImageGetFilterInfo(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
ImageGetFilteringAvailable(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
Alloc_TriBuffer(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
Free_TriBuffer(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
SetASICRev(
|
|||
|
|
IN PHW_DEVICE_EXTENSION pHwDevExt
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
VC_GetPCIRegister(
|
|||
|
|
PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
ULONG ulOffset,
|
|||
|
|
PVOID pData,
|
|||
|
|
ULONG ulLength);
|
|||
|
|
|
|||
|
|
BOOL
|
|||
|
|
VC_SetPCIRegister(
|
|||
|
|
PHW_DEVICE_EXTENSION pHwDevExt,
|
|||
|
|
ULONG ulOffset,
|
|||
|
|
PVOID pData,
|
|||
|
|
ULONG ulLength);
|
|||
|
|
|
|||
|
|
VOID VC_Delay(int nMillisecs);
|
|||
|
|
|
|||
|
|
#if DBG
|
|||
|
|
void DbgDumpPciRegister( PHW_DEVICE_EXTENSION pHwDevExt );
|
|||
|
|
void DbgDumpCaptureRegister( PHW_DEVICE_EXTENSION pHwDevExt );
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#endif // _BERT_H_
|
|||
|
|
|
|||
|
|
|