1620 lines
580 KiB
Plaintext
1620 lines
580 KiB
Plaintext
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/*
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* Copyright (c) 2000, Intel Corporation
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* All rights reserved.
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*
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* WARRANTY DISCLAIMER
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*
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* THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE
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* MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Intel Corporation is the author of the Materials, and requests that all
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* problem reports or change requests be submitted to it directly at
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* http://developer.intel.com/opensource.
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*/
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/***# Generated by encmif Revision: 1.16 ***/
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/***# Generated from EAS 2.6 Draft (23 Sep 99) ***/
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/***# Generated 23 Sep 1999, 04:18:14 PM ***/
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/*** ***/
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### @(#) EMDB $Revision: 1.2 $;
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&inst_id mnemonic template_role op1 op2 op3 op4 op5 op6 flags format major_opcode extensions impls
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?Inst_id_t Mnemonic_t Template_role_t Operand_t Operand_t Operand_t Operand_t Operand_t Operand_t Flags_t Format_t Major_opcode_t Extension_t Implementation_t
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@--- --- EM_TROLE EM_OPROLE;EM_OPTYPE EM_OPROLE;EM_OPTYPE EM_OPROLE;EM_OPTYPE EM_OPROLE;EM_OPTYPE EM_OPROLE;EM_OPTYPE EM_OPROLE;EM_OPTYPE --- EM_FORMAT --- ---;---;---;---;---;---;---;--- ---
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EM_ILLOP ILLEGAL_OP NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 NONE 0x0 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_IGNOP IGNORED_OP NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 NONE 0x0 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_ADD_R1_R2_R3 add ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A1 0x8 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_ADD_R1_R2_R3_1 add ALU DST;IREG_R1_127 SRC;IREG SRC;IREG SRC;ONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A1 0x8 0x0;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_SUB_R1_R2_R3 sub ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A1 0x8 0x0;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_SUB_R1_R2_R3_1 sub ALU DST;IREG_R1_127 SRC;IREG SRC;IREG SRC;ONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A1 0x8 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_ADDP4_R1_R2_R3 addp4 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A1 0x8 0x0;0x0;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_AND_R1_R2_R3 and ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A1 0x8 0x0;0x0;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_ANDCM_R1_R2_R3 andcm ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A1 0x8 0x0;0x0;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_OR_R1_R2_R3 or ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A1 0x8 0x0;0x0;0x3;0x2;0x0;0x0;0x0;0x0 ArchRev0
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EM_XOR_R1_R2_R3 xor ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A1 0x8 0x0;0x0;0x3;0x3;0x0;0x0;0x0;0x0 ArchRev0
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EM_SHLADD_R1_R2_COUNT2_R3 shladd ALU DST;IREG_R1_127 SRC;IREG SRC;UDEC SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000000000001 A2 0x8 0x0;0x0;0x4;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_SHLADDP4_R1_R2_COUNT2_R3 shladdp4 ALU DST;IREG_R1_127 SRC;IREG SRC;UDEC SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000000000001 A2 0x8 0x0;0x0;0x6;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_SUB_R1_IMM8_R3 sub ALU DST;IREG_R1_127 SRC;SIMM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A3 0x8 0x0;0x0;0x9;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_AND_R1_IMM8_R3 and ALU DST;IREG_R1_127 SRC;SIMM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A3 0x8 0x0;0x0;0xB;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_ANDCM_R1_IMM8_R3 andcm ALU DST;IREG_R1_127 SRC;SIMM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A3 0x8 0x0;0x0;0xB;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_OR_R1_IMM8_R3 or ALU DST;IREG_R1_127 SRC;SIMM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A3 0x8 0x0;0x0;0xB;0x2;0x0;0x0;0x0;0x0 ArchRev0
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EM_XOR_R1_IMM8_R3 xor ALU DST;IREG_R1_127 SRC;SIMM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A3 0x8 0x0;0x0;0xB;0x3;0x0;0x0;0x0;0x0 ArchRev0
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EM_ADDS_R1_IMM14_R3 adds ALU DST;IREG_R1_127 SRC;SIMM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A4 0x8 0x2;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_ADDP4_R1_IMM14_R3 addp4 ALU DST;IREG_R1_127 SRC;SIMM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A4 0x8 0x3;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_ADDL_R1_IMM22_R3 addl ALU DST;IREG_R1_127 SRC;SIMM SRC;IREG_R0_3 NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A5 0x9 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_LT_P1_P2_R2_R3 cmp.lt ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xC 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_LTU_P1_P2_R2_R3 cmp.ltu ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xD 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_EQ_P1_P2_R2_R3 cmp.eq ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xE 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_LT_UNC_P1_P2_R2_R3 cmp.lt.unc ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A6 0xC 0x0;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_LTU_UNC_P1_P2_R2_R3 cmp.ltu.unc ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A6 0xD 0x0;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_EQ_UNC_P1_P2_R2_R3 cmp.eq.unc ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A6 0xE 0x0;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_EQ_AND_P1_P2_R2_R3 cmp.eq.and ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xC 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_EQ_OR_P1_P2_R2_R3 cmp.eq.or ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xD 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_EQ_OR_ANDCM_P1_P2_R2_R3 cmp.eq.or.andcm ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xE 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_NE_AND_P1_P2_R2_R3 cmp.ne.and ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xC 0x0;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_NE_OR_P1_P2_R2_R3 cmp.ne.or ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xD 0x0;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_NE_OR_ANDCM_P1_P2_R2_R3 cmp.ne.or.andcm ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xE 0x0;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_LT_P1_P2_R2_R3 cmp4.lt ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xC 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_LTU_P1_P2_R2_R3 cmp4.ltu ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xD 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_EQ_P1_P2_R2_R3 cmp4.eq ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xE 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_LT_UNC_P1_P2_R2_R3 cmp4.lt.unc ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A6 0xC 0x0;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_LTU_UNC_P1_P2_R2_R3 cmp4.ltu.unc ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A6 0xD 0x0;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_EQ_UNC_P1_P2_R2_R3 cmp4.eq.unc ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A6 0xE 0x0;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_EQ_AND_P1_P2_R2_R3 cmp4.eq.and ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xC 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_EQ_OR_P1_P2_R2_R3 cmp4.eq.or ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xD 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_EQ_OR_ANDCM_P1_P2_R2_R3 cmp4.eq.or.andcm ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xE 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_NE_AND_P1_P2_R2_R3 cmp4.ne.and ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xC 0x0;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_NE_OR_P1_P2_R2_R3 cmp4.ne.or ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xD 0x0;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_NE_OR_ANDCM_P1_P2_R2_R3 cmp4.ne.or.andcm ALU DST;PREG DST;PREG SRC;IREG SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A6 0xE 0x0;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_GT_AND_P1_P2_R0_R3 cmp.gt.and ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xC 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_GT_OR_P1_P2_R0_R3 cmp.gt.or ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xD 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_GT_OR_ANDCM_P1_P2_R0_R3 cmp.gt.or.andcm ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xE 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_LE_AND_P1_P2_R0_R3 cmp.le.and ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xC 0x1;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_LE_OR_P1_P2_R0_R3 cmp.le.or ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xD 0x1;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_LE_OR_ANDCM_P1_P2_R0_R3 cmp.le.or.andcm ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xE 0x1;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_GE_AND_P1_P2_R0_R3 cmp.ge.and ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xC 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_GE_OR_P1_P2_R0_R3 cmp.ge.or ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xD 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_GE_OR_ANDCM_P1_P2_R0_R3 cmp.ge.or.andcm ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xE 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_LT_AND_P1_P2_R0_R3 cmp.lt.and ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xC 0x1;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_LT_OR_P1_P2_R0_R3 cmp.lt.or ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xD 0x1;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP_LT_OR_ANDCM_P1_P2_R0_R3 cmp.lt.or.andcm ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xE 0x1;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_GT_AND_P1_P2_R0_R3 cmp4.gt.and ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xC 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_GT_OR_P1_P2_R0_R3 cmp4.gt.or ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xD 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_GT_OR_ANDCM_P1_P2_R0_R3 cmp4.gt.or.andcm ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xE 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_LE_AND_P1_P2_R0_R3 cmp4.le.and ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xC 0x1;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_LE_OR_P1_P2_R0_R3 cmp4.le.or ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xD 0x1;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_LE_OR_ANDCM_P1_P2_R0_R3 cmp4.le.or.andcm ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xE 0x1;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_GE_AND_P1_P2_R0_R3 cmp4.ge.and ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xC 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
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EM_CMP4_GE_OR_P1_P2_R0_R3 cmp4.ge.or ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xD 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP4_GE_OR_ANDCM_P1_P2_R0_R3 cmp4.ge.or.andcm ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xE 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMP4_LT_AND_P1_P2_R0_R3 cmp4.lt.and ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xC 0x1;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMP4_LT_OR_P1_P2_R0_R3 cmp4.lt.or ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xD 0x1;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP4_LT_OR_ANDCM_P1_P2_R0_R3 cmp4.lt.or.andcm ALU DST;PREG DST;PREG SRC;IREG_R0 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A7 0xE 0x1;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_LT_P1_P2_IMM8_R3 cmp.lt ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xC 0x2;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_LTU_P1_P2_IMM8_R3 cmp.ltu ALU DST;PREG DST;PREG SRC;CMP_UIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xD 0x2;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMP_EQ_P1_P2_IMM8_R3 cmp.eq ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xE 0x2;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_LT_UNC_P1_P2_IMM8_R3 cmp.lt.unc ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A8 0xC 0x2;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_LTU_UNC_P1_P2_IMM8_R3 cmp.ltu.unc ALU DST;PREG DST;PREG SRC;CMP_UIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A8 0xD 0x2;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_EQ_UNC_P1_P2_IMM8_R3 cmp.eq.unc ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A8 0xE 0x2;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_EQ_AND_P1_P2_IMM8_R3 cmp.eq.and ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xC 0x2;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_EQ_OR_P1_P2_IMM8_R3 cmp.eq.or ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xD 0x2;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_EQ_OR_ANDCM_P1_P2_IMM8_R3 cmp.eq.or.andcm ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xE 0x2;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_NE_AND_P1_P2_IMM8_R3 cmp.ne.and ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xC 0x2;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_NE_OR_P1_P2_IMM8_R3 cmp.ne.or ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xD 0x2;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP_NE_OR_ANDCM_P1_P2_IMM8_R3 cmp.ne.or.andcm ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xE 0x2;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_CMP4_LT_P1_P2_IMM8_R3 cmp4.lt ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xC 0x3;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_CMP4_LTU_P1_P2_IMM8_R3 cmp4.ltu ALU DST;PREG DST;PREG SRC;CMP4_UIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xD 0x3;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMP4_EQ_P1_P2_IMM8_R3 cmp4.eq ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xE 0x3;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_CMP4_LT_UNC_P1_P2_IMM8_R3 cmp4.lt.unc ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A8 0xC 0x3;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_CMP4_LTU_UNC_P1_P2_IMM8_R3 cmp4.ltu.unc ALU DST;PREG DST;PREG SRC;CMP4_UIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A8 0xD 0x3;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_CMP4_EQ_UNC_P1_P2_IMM8_R3 cmp4.eq.unc ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000001000010000001 A8 0xE 0x3;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_CMP4_EQ_AND_P1_P2_IMM8_R3 cmp4.eq.and ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xC 0x3;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP4_EQ_OR_P1_P2_IMM8_R3 cmp4.eq.or ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xD 0x3;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP4_EQ_OR_ANDCM_P1_P2_IMM8_R3 cmp4.eq.or.andcm ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xE 0x3;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP4_NE_AND_P1_P2_IMM8_R3 cmp4.ne.and ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xC 0x3;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_CMP4_NE_OR_P1_P2_IMM8_R3 cmp4.ne.or ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xD 0x3;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_CMP4_NE_OR_ANDCM_P1_P2_IMM8_R3 cmp4.ne.or.andcm ALU DST;PREG DST;PREG SRC;SIMM SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000010000001 A8 0xE 0x3;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_PADD1_R1_R2_R3 padd1 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_PADD2_R1_R2_R3 padd2 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_PADD4_R1_R2_R3 padd4 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_PADD1_SSS_R1_R2_R3 padd1.sss ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_PADD2_SSS_R1_R2_R3 padd2.sss ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_PADD1_UUU_R1_R2_R3 padd1.uuu ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x0;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_PADD2_UUU_R1_R2_R3 padd2.uuu ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x0;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_PADD1_UUS_R1_R2_R3 padd1.uus ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x0;0x3;0x0;0x0;0x0 ArchRev0
|
||
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EM_PADD2_UUS_R1_R2_R3 padd2.uus ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x0;0x3;0x0;0x0;0x0 ArchRev0
|
||
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EM_PSUB1_R1_R2_R3 psub1 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_PSUB2_R1_R2_R3 psub2 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_PSUB4_R1_R2_R3 psub4 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x1;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_PSUB1_SSS_R1_R2_R3 psub1.sss ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
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EM_PSUB2_SSS_R1_R2_R3 psub2.sss ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
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EM_PSUB1_UUU_R1_R2_R3 psub1.uuu ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x1;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_PSUB2_UUU_R1_R2_R3 psub2.uuu ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x1;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_PSUB1_UUS_R1_R2_R3 psub1.uus ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x1;0x3;0x0;0x0;0x0 ArchRev0
|
||
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EM_PSUB2_UUS_R1_R2_R3 psub2.uus ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x1;0x3;0x0;0x0;0x0 ArchRev0
|
||
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EM_PAVG1_R1_R2_R3 pavg1 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x2;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_PAVG2_R1_R2_R3 pavg2 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x2;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_PAVG1_RAZ_R1_R2_R3 pavg1.raz ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x2;0x3;0x0;0x0;0x0 ArchRev0
|
||
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EM_PAVG2_RAZ_R1_R2_R3 pavg2.raz ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x2;0x3;0x0;0x0;0x0 ArchRev0
|
||
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EM_PAVGSUB1_R1_R2_R3 pavgsub1 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x3;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_PAVGSUB2_R1_R2_R3 pavgsub2 ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x3;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_PCMP1_EQ_R1_R2_R3 pcmp1.eq ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x9;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_PCMP2_EQ_R1_R2_R3 pcmp2.eq ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x9;0x0;0x0;0x0;0x0 ArchRev0
|
||
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|
EM_PCMP4_EQ_R1_R2_R3 pcmp4.eq ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x1;0x1;0x0;0x9;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_PCMP1_GT_R1_R2_R3 pcmp1.gt ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x0;0x9;0x1;0x0;0x0;0x0 ArchRev0
|
||
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|
EM_PCMP2_GT_R1_R2_R3 pcmp2.gt ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x0;0x1;0x1;0x9;0x1;0x0;0x0;0x0 ArchRev0
|
||
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|
EM_PCMP4_GT_R1_R2_R3 pcmp4.gt ALU DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 A9 0x8 0x1;0x1;0x0;0x9;0x1;0x0;0x0;0x0 ArchRev0
|
||
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|
EM_PSHLADD2_R1_R2_COUNT2_R3 pshladd2 ALU DST;IREG_R1_127 SRC;IREG SRC;COUNT_123 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000000000001 A10 0x8 0x0;0x1;0x1;0x4;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_PSHRADD2_R1_R2_COUNT2_R3 pshradd2 ALU DST;IREG_R1_127 SRC;IREG SRC;COUNT_123 SRC;IREG NONE;NONE NONE;NONE 00000000000000000000000000000001 A10 0x8 0x0;0x1;0x1;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_PMPYSHR2_R1_R2_R3_COUNT2 pmpyshr2 INT DST;IREG_R1_127 SRC;IREG SRC;IREG SRC;COUNT_PACK NONE;NONE NONE;NONE 00000000000000000000000000000001 I1 0x7 0x0;0x0;0x1;0x0;0x3;0x0;0x0;0x0 ArchRev0
|
||
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EM_PMPYSHR2_U_R1_R2_R3_COUNT2 pmpyshr2.u INT DST;IREG_R1_127 SRC;IREG SRC;IREG SRC;COUNT_PACK NONE;NONE NONE;NONE 00000000000000000000000000000001 I1 0x7 0x0;0x0;0x1;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
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EM_PMPY2_R_R1_R2_R3 pmpy2.r INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x1;0x0;0x3;0x1;0x0;0x0 ArchRev0
|
||
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EM_PMPY2_L_R1_R2_R3 pmpy2.l INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x1;0x0;0x3;0x3;0x0;0x0 ArchRev0
|
||
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EM_MIX1_R_R1_R2_R3 mix1.r INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x0;0x0;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_MIX2_R_R1_R2_R3 mix2.r INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x1;0x0;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_MIX4_R_R1_R2_R3 mix4.r INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x1;0x2;0x0;0x0;0x2;0x0;0x0;0x0 ArchRev0
|
||
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EM_MIX1_L_R1_R2_R3 mix1.l INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x0;0x0;0x2;0x2;0x0;0x0 ArchRev0
|
||
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EM_MIX2_L_R1_R2_R3 mix2.l INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x1;0x0;0x2;0x2;0x0;0x0 ArchRev0
|
||
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EM_MIX4_L_R1_R2_R3 mix4.l INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x1;0x2;0x0;0x0;0x2;0x2;0x0;0x0 ArchRev0
|
||
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EM_PACK2_USS_R1_R2_R3 pack2.uss INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PACK2_SSS_R1_R2_R3 pack2.sss INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x1;0x0;0x0;0x2;0x0;0x0 ArchRev0
|
||
|
|
EM_PACK4_SSS_R1_R2_R3 pack4.sss INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x1;0x2;0x0;0x0;0x0;0x2;0x0;0x0 ArchRev0
|
||
|
|
EM_UNPACK1_H_R1_R2_R3 unpack1.h INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x0;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_UNPACK2_H_R1_R2_R3 unpack2.h INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x1;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_UNPACK4_H_R1_R2_R3 unpack4.h INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x1;0x2;0x0;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_UNPACK1_L_R1_R2_R3 unpack1.l INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x0;0x0;0x1;0x2;0x0;0x0 ArchRev0
|
||
|
|
EM_UNPACK2_L_R1_R2_R3 unpack2.l INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x1;0x0;0x1;0x2;0x0;0x0 ArchRev0
|
||
|
|
EM_UNPACK4_L_R1_R2_R3 unpack4.l INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x1;0x2;0x0;0x0;0x1;0x2;0x0;0x0 ArchRev0
|
||
|
|
EM_PMIN1_U_R1_R2_R3 pmin1.u INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x0;0x0;0x0;0x1;0x0;0x0 ArchRev0
|
||
|
|
EM_PMAX1_U_R1_R2_R3 pmax1.u INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x0;0x0;0x1;0x1;0x0;0x0 ArchRev0
|
||
|
|
EM_PMIN2_R1_R2_R3 pmin2 INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x1;0x0;0x0;0x3;0x0;0x0 ArchRev0
|
||
|
|
EM_PMAX2_R1_R2_R3 pmax2 INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x1;0x0;0x1;0x3;0x0;0x0 ArchRev0
|
||
|
|
EM_PSAD1_R1_R2_R3 psad1 INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I2 0x7 0x0;0x2;0x0;0x0;0x2;0x3;0x0;0x0 ArchRev0
|
||
|
|
EM_MUX1_R1_R2_MBTYPE4 mux1 INT DST;IREG_R1_127 SRC;IREG SRC;MUX1 NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I3 0x7 0x0;0x3;0x0;0x0;0x2;0x2;0x0;0x0 ArchRev0
|
||
|
|
EM_MUX2_R1_R2_MHTYPE8 mux2 INT DST;IREG_R1_127 SRC;IREG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I4 0x7 0x0;0x3;0x1;0x0;0x2;0x2;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHR2_R1_R3_R2 pshr2 INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I5 0x7 0x0;0x0;0x1;0x0;0x0;0x2;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHR4_R1_R3_R2 pshr4 INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I5 0x7 0x1;0x0;0x0;0x0;0x0;0x2;0x0;0x0 ArchRev0
|
||
|
|
EM_SHR_R1_R3_R2 shr INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I5 0x7 0x1;0x0;0x1;0x0;0x0;0x2;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHR2_U_R1_R3_R2 pshr2.u INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I5 0x7 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHR4_U_R1_R3_R2 pshr4.u INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I5 0x7 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SHR_U_R1_R3_R2 shr.u INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I5 0x7 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHR2_R1_R3_COUNT5 pshr2 INT DST;IREG_R1_127 SRC;IREG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I6 0x7 0x0;0x1;0x1;0x0;0x0;0x3;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHR4_R1_R3_COUNT5 pshr4 INT DST;IREG_R1_127 SRC;IREG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I6 0x7 0x1;0x1;0x0;0x0;0x0;0x3;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHR2_U_R1_R3_COUNT5 pshr2.u INT DST;IREG_R1_127 SRC;IREG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I6 0x7 0x0;0x1;0x1;0x0;0x0;0x1;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHR4_U_R1_R3_COUNT5 pshr4.u INT DST;IREG_R1_127 SRC;IREG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I6 0x7 0x1;0x1;0x0;0x0;0x0;0x1;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHL2_R1_R2_R3 pshl2 INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I7 0x7 0x0;0x0;0x1;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHL4_R1_R2_R3 pshl4 INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I7 0x7 0x1;0x0;0x0;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SHL_R1_R2_R3 shl INT DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I7 0x7 0x1;0x0;0x1;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHL2_R1_R2_COUNT5 pshl2 INT DST;IREG_R1_127 SRC;IREG SRC;CCOUNT NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I8 0x7 0x0;0x3;0x1;0x0;0x1;0x1;0x0;0x0 ArchRev0
|
||
|
|
EM_PSHL4_R1_R2_COUNT5 pshl4 INT DST;IREG_R1_127 SRC;IREG SRC;CCOUNT NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I8 0x7 0x1;0x3;0x0;0x0;0x1;0x1;0x0;0x0 ArchRev0
|
||
|
|
EM_POPCNT_R1_R3 popcnt INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I9 0x7 0x0;0x1;0x1;0x0;0x2;0x1;0x0;0x0 ArchRev0
|
||
|
|
EM_SHRP_R1_R2_R3_COUNT6 shrp INT DST;IREG_R1_127 SRC;IREG SRC;IREG SRC;UIMM NONE;NONE NONE;NONE 00000000000000000000000000000001 I10 0x5 0x3;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_EXTR_U_R1_R3_POS6_LEN6 extr.u INT DST;IREG_R1_127 SRC;IREG SRC;UIMM SRC;UDEC NONE;NONE NONE;NONE 00000000000000000000000000000001 I11 0x5 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_EXTR_R1_R3_POS6_LEN6 extr INT DST;IREG_R1_127 SRC;IREG SRC;UIMM SRC;UDEC NONE;NONE NONE;NONE 00000000000000000000000000000001 I11 0x5 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_DEP_Z_R1_R2_POS6_LEN6 dep.z INT DST;IREG_R1_127 SRC;IREG SRC;CPOS SRC;UDEC NONE;NONE NONE;NONE 00000000000000000000000000000001 I12 0x5 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_DEP_Z_R1_IMM8_POS6_LEN6 dep.z INT DST;IREG_R1_127 SRC;SIMM SRC;CPOS SRC;UDEC NONE;NONE NONE;NONE 00000000000000000000000000000001 I13 0x5 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_DEP_R1_IMM1_R3_POS6_LEN6 dep INT DST;IREG_R1_127 SRC;SIMM SRC;IREG SRC;CPOS SRC;UDEC NONE;NONE 00000000000000000000000000000001 I14 0x5 0x3;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_DEP_R1_R2_R3_POS6_LEN4 dep INT DST;IREG_R1_127 SRC;IREG SRC;IREG SRC;CPOS SRC;UDEC NONE;NONE 00000000000000000000000000000001 I15 0x4 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TBIT_Z_P1_P2_R3_POS6 tbit.z INT DST;PREG DST;PREG SRC;IREG SRC;UIMM NONE;NONE NONE;NONE 00000000000000000000000010000001 I16 0x5 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TBIT_Z_UNC_P1_P2_R3_POS6 tbit.z.unc INT DST;PREG DST;PREG SRC;IREG SRC;UIMM NONE;NONE NONE;NONE 00000000000000000001000010000001 I16 0x5 0x0;0x0;0x0;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TBIT_Z_AND_P1_P2_R3_POS6 tbit.z.and INT DST;PREG DST;PREG SRC;IREG SRC;UIMM NONE;NONE NONE;NONE 00000000000000000000000010000001 I16 0x5 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TBIT_NZ_AND_P1_P2_R3_POS6 tbit.nz.and INT DST;PREG DST;PREG SRC;IREG SRC;UIMM NONE;NONE NONE;NONE 00000000000000000000000010000001 I16 0x5 0x1;0x0;0x0;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TBIT_Z_OR_P1_P2_R3_POS6 tbit.z.or INT DST;PREG DST;PREG SRC;IREG SRC;UIMM NONE;NONE NONE;NONE 00000000000000000000000010000001 I16 0x5 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TBIT_NZ_OR_P1_P2_R3_POS6 tbit.nz.or INT DST;PREG DST;PREG SRC;IREG SRC;UIMM NONE;NONE NONE;NONE 00000000000000000000000010000001 I16 0x5 0x0;0x0;0x1;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TBIT_Z_OR_ANDCM_P1_P2_R3_POS6 tbit.z.or.andcm INT DST;PREG DST;PREG SRC;IREG SRC;UIMM NONE;NONE NONE;NONE 00000000000000000000000010000001 I16 0x5 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TBIT_NZ_OR_ANDCM_P1_P2_R3_POS6 tbit.nz.or.andcm INT DST;PREG DST;PREG SRC;IREG SRC;UIMM NONE;NONE NONE;NONE 00000000000000000000000010000001 I16 0x5 0x1;0x0;0x1;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TNAT_Z_P1_P2_R3 tnat.z INT DST;PREG DST;PREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000010000001 I17 0x5 0x0;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TNAT_Z_UNC_P1_P2_R3 tnat.z.unc INT DST;PREG DST;PREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000001000010000001 I17 0x5 0x0;0x0;0x0;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TNAT_Z_AND_P1_P2_R3 tnat.z.and INT DST;PREG DST;PREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000010000001 I17 0x5 0x1;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TNAT_NZ_AND_P1_P2_R3 tnat.nz.and INT DST;PREG DST;PREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000010000001 I17 0x5 0x1;0x0;0x0;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TNAT_Z_OR_P1_P2_R3 tnat.z.or INT DST;PREG DST;PREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000010000001 I17 0x5 0x0;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TNAT_NZ_OR_P1_P2_R3 tnat.nz.or INT DST;PREG DST;PREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000010000001 I17 0x5 0x0;0x0;0x1;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TNAT_Z_OR_ANDCM_P1_P2_R3 tnat.z.or.andcm INT DST;PREG DST;PREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000010000001 I17 0x5 0x1;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TNAT_NZ_OR_ANDCM_P1_P2_R3 tnat.nz.or.andcm INT DST;PREG DST;PREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000010000001 I17 0x5 0x1;0x0;0x1;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BREAK_I_IMM21 break.i INT SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000010000000001 I19 0x0 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_NOP_I_IMM21 nop.i INT SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000010000000001 I19 0x0 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CHK_S_I_R2_TARGET25 chk.s.i INT SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I20 0x0 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_SPTK_B1_R2_TAG13 mov.sptk INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_SPTK_IMP_B1_R2_TAG13 mov.sptk.imp INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_B1_R2_TAG13 mov INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_IMP_B1_R2_TAG13 mov.imp INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_DPTK_B1_R2_TAG13 mov.dptk INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x0;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_DPTK_IMP_B1_R2_TAG13 mov.dptk.imp INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x1;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_RET_SPTK_B1_R2_TAG13 mov.ret.sptk INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_RET_SPTK_IMP_B1_R2_TAG13 mov.ret.sptk.imp INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_RET_B1_R2_TAG13 mov.ret INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_RET_IMP_B1_R2_TAG13 mov.ret.imp INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_RET_DPTK_B1_R2_TAG13 mov.ret.dptk INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x0;0x1;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_RET_DPTK_IMP_B1_R2_TAG13 mov.ret.dptk.imp INT DST;BR SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I21 0x0 0x7;0x1;0x1;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_B2 mov INT DST;IREG_R1_127 SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I22 0x0 0x0;0x31;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_PR_R2_MASK17 mov INT DST;PREGS_ALL SRC;IREG SRC;SSHIFT_1 NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I23 0x0 0x3;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_PR_ROT_IMM44 mov INT DST;PREGS_ROT SRC;SSHIFT_16 NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I24 0x0 0x2;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_IP mov INT DST;IREG_R1_127 SRC;IP NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I25 0x0 0x0;0x30;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_PR mov INT DST;IREG_R1_127 SRC;PREGS_ALL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I25 0x0 0x0;0x33;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_I_AR3_R2 mov.i INT DST;APP_REG_GRP_HIGH SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I26 0x0 0x0;0x2A;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_MOV_I_AR3_IMM8 mov.i INT DST;APP_REG_GRP_HIGH SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I27 0x0 0x0;0xA;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_MOV_I_R1_AR3 mov.i INT DST;IREG_R1_127 SRC;APP_REG_GRP_HIGH NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I28 0x0 0x0;0x32;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ZXT1_R1_R3 zxt1 INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I29 0x0 0x0;0x10;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ZXT2_R1_R3 zxt2 INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I29 0x0 0x0;0x11;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ZXT4_R1_R3 zxt4 INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I29 0x0 0x0;0x12;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SXT1_R1_R3 sxt1 INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I29 0x0 0x0;0x14;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SXT2_R1_R3 sxt2 INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I29 0x0 0x0;0x15;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SXT4_R1_R3 sxt4 INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I29 0x0 0x0;0x16;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CZX1_L_R1_R3 czx1.l INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I29 0x0 0x0;0x18;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CZX2_L_R1_R3 czx2.l INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I29 0x0 0x0;0x19;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CZX1_R_R1_R3 czx1.r INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I29 0x0 0x0;0x1C;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CZX2_R_R1_R3 czx2.r INT DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 I29 0x0 0x0;0x1D;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_R1_R3 ld1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_NT1_R1_R3 ld1.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_NTA_R1_R3 ld1.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x0;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_R1_R3 ld2 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_NT1_R1_R3 ld2.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_NTA_R1_R3 ld2.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x1;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_R1_R3 ld4 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_NT1_R1_R3 ld4.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_NTA_R1_R3 ld4.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x2;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_R1_R3 ld8 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_NT1_R1_R3 ld8.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_NTA_R1_R3 ld8.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x3;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_S_R1_R3 ld1.s MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x4;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_S_NT1_R1_R3 ld1.s.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x4;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_S_NTA_R1_R3 ld1.s.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x4;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_S_R1_R3 ld2.s MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x5;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_S_NT1_R1_R3 ld2.s.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x5;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_S_NTA_R1_R3 ld2.s.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x5;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_S_R1_R3 ld4.s MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x6;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_S_NT1_R1_R3 ld4.s.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x6;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_S_NTA_R1_R3 ld4.s.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x6;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_S_R1_R3 ld8.s MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x7;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_S_NT1_R1_R3 ld8.s.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x7;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_S_NTA_R1_R3 ld8.s.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x7;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_A_R1_R3 ld1.a MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x8;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_A_NT1_R1_R3 ld1.a.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x8;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_A_NTA_R1_R3 ld1.a.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x8;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_A_R1_R3 ld2.a MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x9;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_A_NT1_R1_R3 ld2.a.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x9;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_A_NTA_R1_R3 ld2.a.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x9;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_A_R1_R3 ld4.a MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xA;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_A_NT1_R1_R3 ld4.a.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xA;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_A_NTA_R1_R3 ld4.a.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xA;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_A_R1_R3 ld8.a MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xB;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_A_NT1_R1_R3 ld8.a.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xB;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_A_NTA_R1_R3 ld8.a.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xB;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_SA_R1_R3 ld1.sa MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xC;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_SA_NT1_R1_R3 ld1.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xC;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_SA_NTA_R1_R3 ld1.sa.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xC;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_SA_R1_R3 ld2.sa MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xD;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_SA_NT1_R1_R3 ld2.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xD;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_SA_NTA_R1_R3 ld2.sa.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xD;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_SA_R1_R3 ld4.sa MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xE;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_SA_NT1_R1_R3 ld4.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xE;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_SA_NTA_R1_R3 ld4.sa.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xE;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_SA_R1_R3 ld8.sa MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xF;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_SA_NT1_R1_R3 ld8.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xF;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_SA_NTA_R1_R3 ld8.sa.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0xF;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_BIAS_R1_R3 ld1.bias MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x10;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_BIAS_NT1_R1_R3 ld1.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x10;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_BIAS_NTA_R1_R3 ld1.bias.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x10;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_BIAS_R1_R3 ld2.bias MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x11;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_BIAS_NT1_R1_R3 ld2.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x11;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_BIAS_NTA_R1_R3 ld2.bias.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x11;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_BIAS_R1_R3 ld4.bias MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x12;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_BIAS_NT1_R1_R3 ld4.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x12;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_BIAS_NTA_R1_R3 ld4.bias.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x12;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_BIAS_R1_R3 ld8.bias MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x13;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_BIAS_NT1_R1_R3 ld8.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x13;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_BIAS_NTA_R1_R3 ld8.bias.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x13;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_ACQ_R1_R3 ld1.acq MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x14;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_ACQ_NT1_R1_R3 ld1.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x14;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_ACQ_NTA_R1_R3 ld1.acq.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x14;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_ACQ_R1_R3 ld2.acq MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x15;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_ACQ_NT1_R1_R3 ld2.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x15;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_ACQ_NTA_R1_R3 ld2.acq.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x15;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_ACQ_R1_R3 ld4.acq MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x16;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_ACQ_NT1_R1_R3 ld4.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x16;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_ACQ_NTA_R1_R3 ld4.acq.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x16;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_ACQ_R1_R3 ld8.acq MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x17;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_ACQ_NT1_R1_R3 ld8.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x17;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_ACQ_NTA_R1_R3 ld8.acq.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x17;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_FILL_R1_R3 ld8.fill MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x1B;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_FILL_NT1_R1_R3 ld8.fill.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x1B;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_FILL_NTA_R1_R3 ld8.fill.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x1B;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_R1_R3 ld1.c.clr MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x20;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_NT1_R1_R3 ld1.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x20;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_NTA_R1_R3 ld1.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x20;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_R1_R3 ld2.c.clr MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x21;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_NT1_R1_R3 ld2.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x21;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_NTA_R1_R3 ld2.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x21;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_R1_R3 ld4.c.clr MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x22;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_NT1_R1_R3 ld4.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x22;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_NTA_R1_R3 ld4.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x22;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_R1_R3 ld8.c.clr MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x23;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_NT1_R1_R3 ld8.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x23;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_NTA_R1_R3 ld8.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x23;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_NC_R1_R3 ld1.c.nc MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x24;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_NC_NT1_R1_R3 ld1.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x24;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_NC_NTA_R1_R3 ld1.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x24;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_NC_R1_R3 ld2.c.nc MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x25;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_NC_NT1_R1_R3 ld2.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x25;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_NC_NTA_R1_R3 ld2.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x25;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_NC_R1_R3 ld4.c.nc MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x26;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_NC_NT1_R1_R3 ld4.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x26;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_NC_NTA_R1_R3 ld4.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x26;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_NC_R1_R3 ld8.c.nc MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x27;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_NC_NT1_R1_R3 ld8.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x27;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_NC_NTA_R1_R3 ld8.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x27;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_ACQ_R1_R3 ld1.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x28;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_ACQ_NT1_R1_R3 ld1.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x28;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_ACQ_NTA_R1_R3 ld1.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x28;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_ACQ_R1_R3 ld2.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x29;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_ACQ_NT1_R1_R3 ld2.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x29;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_ACQ_NTA_R1_R3 ld2.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x29;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_ACQ_R1_R3 ld4.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x2A;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_ACQ_NT1_R1_R3 ld4.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x2A;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_ACQ_NTA_R1_R3 ld4.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x2A;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_ACQ_R1_R3 ld8.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x2B;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_ACQ_NT1_R1_R3 ld8.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x2B;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_ACQ_NTA_R1_R3 ld8.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M1 0x4 0x0;0x2B;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_R1_R3_R2 ld1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_NT1_R1_R3_R2 ld1.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_NTA_R1_R3_R2 ld1.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x0;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_R1_R3_R2 ld2 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_NT1_R1_R3_R2 ld2.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_NTA_R1_R3_R2 ld2.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x1;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_R1_R3_R2 ld4 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_NT1_R1_R3_R2 ld4.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_NTA_R1_R3_R2 ld4.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x2;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_R1_R3_R2 ld8 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_NT1_R1_R3_R2 ld8.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_NTA_R1_R3_R2 ld8.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x3;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_S_R1_R3_R2 ld1.s MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x4;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_S_NT1_R1_R3_R2 ld1.s.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x4;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_S_NTA_R1_R3_R2 ld1.s.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x4;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_S_R1_R3_R2 ld2.s MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x5;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_S_NT1_R1_R3_R2 ld2.s.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x5;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_S_NTA_R1_R3_R2 ld2.s.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x5;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_S_R1_R3_R2 ld4.s MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x6;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_S_NT1_R1_R3_R2 ld4.s.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x6;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_S_NTA_R1_R3_R2 ld4.s.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x6;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_S_R1_R3_R2 ld8.s MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x7;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_S_NT1_R1_R3_R2 ld8.s.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x7;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_S_NTA_R1_R3_R2 ld8.s.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x7;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
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EM_LD1_A_R1_R3_R2 ld1.a MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x8;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
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||
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EM_LD1_A_NT1_R1_R3_R2 ld1.a.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x8;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD1_A_NTA_R1_R3_R2 ld1.a.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x8;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD2_A_R1_R3_R2 ld2.a MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x9;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD2_A_NT1_R1_R3_R2 ld2.a.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x9;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD2_A_NTA_R1_R3_R2 ld2.a.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x9;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD4_A_R1_R3_R2 ld4.a MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xA;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD4_A_NT1_R1_R3_R2 ld4.a.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xA;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD4_A_NTA_R1_R3_R2 ld4.a.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xA;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD8_A_R1_R3_R2 ld8.a MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xB;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD8_A_NT1_R1_R3_R2 ld8.a.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xB;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD8_A_NTA_R1_R3_R2 ld8.a.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xB;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD1_SA_R1_R3_R2 ld1.sa MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xC;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_LD1_SA_NT1_R1_R3_R2 ld1.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xC;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD1_SA_NTA_R1_R3_R2 ld1.sa.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xC;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD2_SA_R1_R3_R2 ld2.sa MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xD;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD2_SA_NT1_R1_R3_R2 ld2.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xD;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD2_SA_NTA_R1_R3_R2 ld2.sa.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xD;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD4_SA_R1_R3_R2 ld4.sa MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xE;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD4_SA_NT1_R1_R3_R2 ld4.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xE;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD4_SA_NTA_R1_R3_R2 ld4.sa.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xE;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD8_SA_R1_R3_R2 ld8.sa MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xF;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD8_SA_NT1_R1_R3_R2 ld8.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xF;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD8_SA_NTA_R1_R3_R2 ld8.sa.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0xF;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_BIAS_R1_R3_R2 ld1.bias MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x10;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_BIAS_NT1_R1_R3_R2 ld1.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x10;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_BIAS_NTA_R1_R3_R2 ld1.bias.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x10;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_BIAS_R1_R3_R2 ld2.bias MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x11;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD2_BIAS_NT1_R1_R3_R2 ld2.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x11;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_BIAS_NTA_R1_R3_R2 ld2.bias.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x11;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_BIAS_R1_R3_R2 ld4.bias MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x12;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_BIAS_NT1_R1_R3_R2 ld4.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x12;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_BIAS_NTA_R1_R3_R2 ld4.bias.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x12;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_BIAS_R1_R3_R2 ld8.bias MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x13;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_BIAS_NT1_R1_R3_R2 ld8.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x13;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_BIAS_NTA_R1_R3_R2 ld8.bias.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x13;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_ACQ_R1_R3_R2 ld1.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x14;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_ACQ_NT1_R1_R3_R2 ld1.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x14;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_ACQ_NTA_R1_R3_R2 ld1.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x14;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_ACQ_R1_R3_R2 ld2.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x15;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_ACQ_NT1_R1_R3_R2 ld2.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x15;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_ACQ_NTA_R1_R3_R2 ld2.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x15;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_ACQ_R1_R3_R2 ld4.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x16;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_ACQ_NT1_R1_R3_R2 ld4.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x16;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_ACQ_NTA_R1_R3_R2 ld4.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x16;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_ACQ_R1_R3_R2 ld8.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x17;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_ACQ_NT1_R1_R3_R2 ld8.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x17;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_ACQ_NTA_R1_R3_R2 ld8.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x17;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_FILL_R1_R3_R2 ld8.fill MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x1B;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_FILL_NT1_R1_R3_R2 ld8.fill.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x1B;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_FILL_NTA_R1_R3_R2 ld8.fill.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x1B;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_R1_R3_R2 ld1.c.clr MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x20;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_NT1_R1_R3_R2 ld1.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x20;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_NTA_R1_R3_R2 ld1.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x20;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_R1_R3_R2 ld2.c.clr MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x21;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD2_C_CLR_NT1_R1_R3_R2 ld2.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x21;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_NTA_R1_R3_R2 ld2.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x21;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_R1_R3_R2 ld4.c.clr MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x22;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD4_C_CLR_NT1_R1_R3_R2 ld4.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x22;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_NTA_R1_R3_R2 ld4.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x22;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_R1_R3_R2 ld8.c.clr MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x23;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_NT1_R1_R3_R2 ld8.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x23;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_NTA_R1_R3_R2 ld8.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x23;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_NC_R1_R3_R2 ld1.c.nc MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x24;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_NC_NT1_R1_R3_R2 ld1.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x24;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_NC_NTA_R1_R3_R2 ld1.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x24;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_NC_R1_R3_R2 ld2.c.nc MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x25;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD2_C_NC_NT1_R1_R3_R2 ld2.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x25;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD2_C_NC_NTA_R1_R3_R2 ld2.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x25;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_NC_R1_R3_R2 ld4.c.nc MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x26;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD4_C_NC_NT1_R1_R3_R2 ld4.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x26;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD4_C_NC_NTA_R1_R3_R2 ld4.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x26;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_NC_R1_R3_R2 ld8.c.nc MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x27;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_NC_NT1_R1_R3_R2 ld8.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x27;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_NC_NTA_R1_R3_R2 ld8.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x27;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_ACQ_R1_R3_R2 ld1.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x28;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_ACQ_NT1_R1_R3_R2 ld1.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x28;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_ACQ_NTA_R1_R3_R2 ld1.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x28;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_ACQ_R1_R3_R2 ld2.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x29;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_ACQ_NT1_R1_R3_R2 ld2.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x29;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_ACQ_NTA_R1_R3_R2 ld2.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x29;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_ACQ_R1_R3_R2 ld4.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x2A;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_ACQ_NT1_R1_R3_R2 ld4.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x2A;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_ACQ_NTA_R1_R3_R2 ld4.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x2A;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_ACQ_R1_R3_R2 ld8.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x2B;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_ACQ_NT1_R1_R3_R2 ld8.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x2B;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_ACQ_NTA_R1_R3_R2 ld8.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M2 0x4 0x1;0x2B;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_R1_R3_IMM9 ld1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_NT1_R1_R3_IMM9 ld1.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_NTA_R1_R3_IMM9 ld1.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_R1_R3_IMM9 ld2 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_NT1_R1_R3_IMM9 ld2.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_NTA_R1_R3_IMM9 ld2.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_R1_R3_IMM9 ld4 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x2;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_NT1_R1_R3_IMM9 ld4.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x2;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_NTA_R1_R3_IMM9 ld4.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x2;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_R1_R3_IMM9 ld8 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x3;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_NT1_R1_R3_IMM9 ld8.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x3;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_NTA_R1_R3_IMM9 ld8.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x3;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_S_R1_R3_IMM9 ld1.s MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x4;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_S_NT1_R1_R3_IMM9 ld1.s.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x4;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_S_NTA_R1_R3_IMM9 ld1.s.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x4;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_S_R1_R3_IMM9 ld2.s MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x5;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_S_NT1_R1_R3_IMM9 ld2.s.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x5;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_S_NTA_R1_R3_IMM9 ld2.s.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x5;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_S_R1_R3_IMM9 ld4.s MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x6;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_S_NT1_R1_R3_IMM9 ld4.s.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x6;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_S_NTA_R1_R3_IMM9 ld4.s.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x6;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_S_R1_R3_IMM9 ld8.s MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x7;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_S_NT1_R1_R3_IMM9 ld8.s.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x7;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_S_NTA_R1_R3_IMM9 ld8.s.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x7;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_A_R1_R3_IMM9 ld1.a MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x8;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_A_NT1_R1_R3_IMM9 ld1.a.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x8;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_A_NTA_R1_R3_IMM9 ld1.a.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x8;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_A_R1_R3_IMM9 ld2.a MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x9;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_A_NT1_R1_R3_IMM9 ld2.a.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x9;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_A_NTA_R1_R3_IMM9 ld2.a.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x9;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_A_R1_R3_IMM9 ld4.a MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xA;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_A_NT1_R1_R3_IMM9 ld4.a.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xA;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_A_NTA_R1_R3_IMM9 ld4.a.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xA;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_A_R1_R3_IMM9 ld8.a MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xB;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_A_NT1_R1_R3_IMM9 ld8.a.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xB;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_A_NTA_R1_R3_IMM9 ld8.a.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xB;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_SA_R1_R3_IMM9 ld1.sa MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xC;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_SA_NT1_R1_R3_IMM9 ld1.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xC;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_SA_NTA_R1_R3_IMM9 ld1.sa.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xC;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_SA_R1_R3_IMM9 ld2.sa MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xD;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_SA_NT1_R1_R3_IMM9 ld2.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xD;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_SA_NTA_R1_R3_IMM9 ld2.sa.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xD;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_SA_R1_R3_IMM9 ld4.sa MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xE;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_SA_NT1_R1_R3_IMM9 ld4.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xE;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_SA_NTA_R1_R3_IMM9 ld4.sa.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xE;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_SA_R1_R3_IMM9 ld8.sa MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xF;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_SA_NT1_R1_R3_IMM9 ld8.sa.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xF;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_SA_NTA_R1_R3_IMM9 ld8.sa.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0xF;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_BIAS_R1_R3_IMM9 ld1.bias MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x10;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_BIAS_NT1_R1_R3_IMM9 ld1.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x10;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_BIAS_NTA_R1_R3_IMM9 ld1.bias.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x10;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_BIAS_R1_R3_IMM9 ld2.bias MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x11;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_BIAS_NT1_R1_R3_IMM9 ld2.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x11;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_BIAS_NTA_R1_R3_IMM9 ld2.bias.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x11;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LD4_BIAS_R1_R3_IMM9 ld4.bias MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x12;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_BIAS_NT1_R1_R3_IMM9 ld4.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x12;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_BIAS_NTA_R1_R3_IMM9 ld4.bias.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x12;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_BIAS_R1_R3_IMM9 ld8.bias MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x13;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_BIAS_NT1_R1_R3_IMM9 ld8.bias.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x13;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_BIAS_NTA_R1_R3_IMM9 ld8.bias.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x13;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_ACQ_R1_R3_IMM9 ld1.acq MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x14;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_ACQ_NT1_R1_R3_IMM9 ld1.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x14;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_ACQ_NTA_R1_R3_IMM9 ld1.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x14;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_ACQ_R1_R3_IMM9 ld2.acq MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x15;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_ACQ_NT1_R1_R3_IMM9 ld2.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x15;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_ACQ_NTA_R1_R3_IMM9 ld2.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x15;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_ACQ_R1_R3_IMM9 ld4.acq MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x16;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_ACQ_NT1_R1_R3_IMM9 ld4.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x16;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_ACQ_NTA_R1_R3_IMM9 ld4.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x16;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_ACQ_R1_R3_IMM9 ld8.acq MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x17;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_ACQ_NT1_R1_R3_IMM9 ld8.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x17;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_ACQ_NTA_R1_R3_IMM9 ld8.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x17;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_FILL_R1_R3_IMM9 ld8.fill MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x1B;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_FILL_NT1_R1_R3_IMM9 ld8.fill.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x1B;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_FILL_NTA_R1_R3_IMM9 ld8.fill.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x1B;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_R1_R3_IMM9 ld1.c.clr MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x20;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_NT1_R1_R3_IMM9 ld1.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x20;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_NTA_R1_R3_IMM9 ld1.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x20;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_R1_R3_IMM9 ld2.c.clr MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x21;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_NT1_R1_R3_IMM9 ld2.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x21;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_NTA_R1_R3_IMM9 ld2.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x21;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_R1_R3_IMM9 ld4.c.clr MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x22;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_NT1_R1_R3_IMM9 ld4.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x22;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_NTA_R1_R3_IMM9 ld4.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x22;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_R1_R3_IMM9 ld8.c.clr MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x23;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_NT1_R1_R3_IMM9 ld8.c.clr.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x23;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_NTA_R1_R3_IMM9 ld8.c.clr.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x23;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_NC_R1_R3_IMM9 ld1.c.nc MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x24;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_NC_NT1_R1_R3_IMM9 ld1.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x24;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_NC_NTA_R1_R3_IMM9 ld1.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x24;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_NC_R1_R3_IMM9 ld2.c.nc MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x25;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_NC_NT1_R1_R3_IMM9 ld2.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x25;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_NC_NTA_R1_R3_IMM9 ld2.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x25;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_NC_R1_R3_IMM9 ld4.c.nc MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x26;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_NC_NT1_R1_R3_IMM9 ld4.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x26;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_NC_NTA_R1_R3_IMM9 ld4.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x26;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_NC_R1_R3_IMM9 ld8.c.nc MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x27;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_NC_NT1_R1_R3_IMM9 ld8.c.nc.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x27;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_NC_NTA_R1_R3_IMM9 ld8.c.nc.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x27;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_ACQ_R1_R3_IMM9 ld1.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x28;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_ACQ_NT1_R1_R3_IMM9 ld1.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x28;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD1_C_CLR_ACQ_NTA_R1_R3_IMM9 ld1.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x28;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_ACQ_R1_R3_IMM9 ld2.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x29;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_ACQ_NT1_R1_R3_IMM9 ld2.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x29;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD2_C_CLR_ACQ_NTA_R1_R3_IMM9 ld2.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x29;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_ACQ_R1_R3_IMM9 ld4.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x2A;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_ACQ_NT1_R1_R3_IMM9 ld4.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x2A;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD4_C_CLR_ACQ_NTA_R1_R3_IMM9 ld4.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x2A;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_ACQ_R1_R3_IMM9 ld8.c.clr.acq MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x2B;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_ACQ_NT1_R1_R3_IMM9 ld8.c.clr.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x2B;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LD8_C_CLR_ACQ_NTA_R1_R3_IMM9 ld8.c.clr.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000010101 M3 0x5 0x2B;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST1_R3_R2 st1 MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x30;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST1_NTA_R3_R2 st1.nta MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x30;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST2_R3_R2 st2 MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x31;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST2_NTA_R3_R2 st2.nta MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x31;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST4_R3_R2 st4 MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x32;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST4_NTA_R3_R2 st4.nta MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x32;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_R3_R2 st8 MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x33;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_NTA_R3_R2 st8.nta MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x33;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST1_REL_R3_R2 st1.rel MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x34;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST1_REL_NTA_R3_R2 st1.rel.nta MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x34;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST2_REL_R3_R2 st2.rel MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x35;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST2_REL_NTA_R3_R2 st2.rel.nta MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x35;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST4_REL_R3_R2 st4.rel MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x36;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST4_REL_NTA_R3_R2 st4.rel.nta MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x36;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_REL_R3_R2 st8.rel MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x37;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_REL_NTA_R3_R2 st8.rel.nta MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x37;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_SPILL_R3_R2 st8.spill MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x3B;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_SPILL_NTA_R3_R2 st8.spill.nta MEM DST;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M4 0x4 0x0;0x3B;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST1_R3_R2_IMM9 st1 MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x30;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST1_NTA_R3_R2_IMM9 st1.nta MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x30;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST2_R3_R2_IMM9 st2 MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x31;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST2_NTA_R3_R2_IMM9 st2.nta MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x31;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST4_R3_R2_IMM9 st4 MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x32;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST4_NTA_R3_R2_IMM9 st4.nta MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x32;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_R3_R2_IMM9 st8 MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x33;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_NTA_R3_R2_IMM9 st8.nta MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x33;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST1_REL_R3_R2_IMM9 st1.rel MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x34;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST1_REL_NTA_R3_R2_IMM9 st1.rel.nta MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x34;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST2_REL_R3_R2_IMM9 st2.rel MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x35;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST2_REL_NTA_R3_R2_IMM9 st2.rel.nta MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x35;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST4_REL_R3_R2_IMM9 st4.rel MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x36;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST4_REL_NTA_R3_R2_IMM9 st4.rel.nta MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x36;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_REL_R3_R2_IMM9 st8.rel MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x37;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_REL_NTA_R3_R2_IMM9 st8.rel.nta MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x37;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_SPILL_R3_R2_IMM9 st8.spill MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x3B;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ST8_SPILL_NTA_R3_R2_IMM9 st8.spill.nta MEM DST;MEM SRC;IREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M5 0x5 0x3B;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_F1_R3 ldfs MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_NT1_F1_R3 ldfs.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_NTA_F1_R3 ldfs.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x2;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_F1_R3 ldfd MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_NT1_F1_R3 ldfd.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_NTA_F1_R3 ldfd.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x3;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_F1_R3 ldf8 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_NT1_F1_R3 ldf8.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_NTA_F1_R3 ldf8.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x1;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_F1_R3 ldfe MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_NT1_F1_R3 ldfe.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_NTA_F1_R3 ldfe.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x0;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_S_F1_R3 ldfs.s MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x6;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_S_NT1_F1_R3 ldfs.s.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x6;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_S_NTA_F1_R3 ldfs.s.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x6;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_S_F1_R3 ldfd.s MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x7;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_S_NT1_F1_R3 ldfd.s.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x7;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_S_NTA_F1_R3 ldfd.s.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x7;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_S_F1_R3 ldf8.s MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x5;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_S_NT1_F1_R3 ldf8.s.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x5;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_S_NTA_F1_R3 ldf8.s.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x5;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_S_F1_R3 ldfe.s MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x4;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_S_NT1_F1_R3 ldfe.s.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x4;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_S_NTA_F1_R3 ldfe.s.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x4;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_A_F1_R3 ldfs.a MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xA;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_A_NT1_F1_R3 ldfs.a.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xA;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_A_NTA_F1_R3 ldfs.a.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xA;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_A_F1_R3 ldfd.a MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xB;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_A_NT1_F1_R3 ldfd.a.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xB;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_A_NTA_F1_R3 ldfd.a.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xB;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_A_F1_R3 ldf8.a MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x9;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_A_NT1_F1_R3 ldf8.a.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x9;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_A_NTA_F1_R3 ldf8.a.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x9;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_A_F1_R3 ldfe.a MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x8;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_A_NT1_F1_R3 ldfe.a.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x8;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_A_NTA_F1_R3 ldfe.a.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x8;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_SA_F1_R3 ldfs.sa MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xE;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_SA_NT1_F1_R3 ldfs.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xE;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_SA_NTA_F1_R3 ldfs.sa.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xE;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_SA_F1_R3 ldfd.sa MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xF;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_SA_NT1_F1_R3 ldfd.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xF;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_SA_NTA_F1_R3 ldfd.sa.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xF;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_SA_F1_R3 ldf8.sa MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xD;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_SA_NT1_F1_R3 ldf8.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xD;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_SA_NTA_F1_R3 ldf8.sa.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xD;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_SA_F1_R3 ldfe.sa MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xC;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_SA_NT1_F1_R3 ldfe.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xC;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_SA_NTA_F1_R3 ldfe.sa.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0xC;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF_FILL_F1_R3 ldf.fill MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x1B;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF_FILL_NT1_F1_R3 ldf.fill.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x1B;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF_FILL_NTA_F1_R3 ldf.fill.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x1B;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_CLR_F1_R3 ldfs.c.clr MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x22;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_CLR_NT1_F1_R3 ldfs.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x22;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LDFS_C_CLR_NTA_F1_R3 ldfs.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x22;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_CLR_F1_R3 ldfd.c.clr MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x23;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_CLR_NT1_F1_R3 ldfd.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x23;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_CLR_NTA_F1_R3 ldfd.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x23;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_CLR_F1_R3 ldf8.c.clr MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x21;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_CLR_NT1_F1_R3 ldf8.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x21;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_CLR_NTA_F1_R3 ldf8.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x21;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_CLR_F1_R3 ldfe.c.clr MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x20;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_CLR_NT1_F1_R3 ldfe.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x20;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_CLR_NTA_F1_R3 ldfe.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x20;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_NC_F1_R3 ldfs.c.nc MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x26;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_NC_NT1_F1_R3 ldfs.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x26;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_NC_NTA_F1_R3 ldfs.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x26;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_NC_F1_R3 ldfd.c.nc MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x27;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_NC_NT1_F1_R3 ldfd.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x27;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_NC_NTA_F1_R3 ldfd.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x27;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_NC_F1_R3 ldf8.c.nc MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x25;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_NC_NT1_F1_R3 ldf8.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x25;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_NC_NTA_F1_R3 ldf8.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x25;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_NC_F1_R3 ldfe.c.nc MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x24;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_NC_NT1_F1_R3 ldfe.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x24;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_NC_NTA_F1_R3 ldfe.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M6 0x6 0x0;0x24;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_F1_R3_R2 ldfs MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_NT1_F1_R3_R2 ldfs.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_NTA_F1_R3_R2 ldfs.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x2;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_F1_R3_R2 ldfd MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_NT1_F1_R3_R2 ldfd.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_NTA_F1_R3_R2 ldfd.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x3;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_F1_R3_R2 ldf8 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_NT1_F1_R3_R2 ldf8.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_NTA_F1_R3_R2 ldf8.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x1;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_F1_R3_R2 ldfe MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_NT1_F1_R3_R2 ldfe.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_NTA_F1_R3_R2 ldfe.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x0;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_S_F1_R3_R2 ldfs.s MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x6;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_S_NT1_F1_R3_R2 ldfs.s.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x6;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_S_NTA_F1_R3_R2 ldfs.s.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x6;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_S_F1_R3_R2 ldfd.s MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x7;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_S_NT1_F1_R3_R2 ldfd.s.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x7;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_S_NTA_F1_R3_R2 ldfd.s.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x7;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_S_F1_R3_R2 ldf8.s MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x5;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_S_NT1_F1_R3_R2 ldf8.s.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x5;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_S_NTA_F1_R3_R2 ldf8.s.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x5;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_S_F1_R3_R2 ldfe.s MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x4;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_S_NT1_F1_R3_R2 ldfe.s.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x4;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_S_NTA_F1_R3_R2 ldfe.s.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x4;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_A_F1_R3_R2 ldfs.a MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xA;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_A_NT1_F1_R3_R2 ldfs.a.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xA;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_A_NTA_F1_R3_R2 ldfs.a.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xA;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_A_F1_R3_R2 ldfd.a MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xB;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_A_NT1_F1_R3_R2 ldfd.a.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xB;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_A_NTA_F1_R3_R2 ldfd.a.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xB;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_A_F1_R3_R2 ldf8.a MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x9;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_A_NT1_F1_R3_R2 ldf8.a.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x9;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_A_NTA_F1_R3_R2 ldf8.a.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x9;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_A_F1_R3_R2 ldfe.a MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x8;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_A_NT1_F1_R3_R2 ldfe.a.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x8;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_A_NTA_F1_R3_R2 ldfe.a.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x8;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_SA_F1_R3_R2 ldfs.sa MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xE;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_SA_NT1_F1_R3_R2 ldfs.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xE;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_SA_NTA_F1_R3_R2 ldfs.sa.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xE;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_SA_F1_R3_R2 ldfd.sa MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xF;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_SA_NT1_F1_R3_R2 ldfd.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xF;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_SA_NTA_F1_R3_R2 ldfd.sa.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xF;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_SA_F1_R3_R2 ldf8.sa MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xD;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_SA_NT1_F1_R3_R2 ldf8.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xD;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_SA_NTA_F1_R3_R2 ldf8.sa.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xD;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_SA_F1_R3_R2 ldfe.sa MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xC;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_SA_NT1_F1_R3_R2 ldfe.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xC;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_SA_NTA_F1_R3_R2 ldfe.sa.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0xC;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF_FILL_F1_R3_R2 ldf.fill MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x1B;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF_FILL_NT1_F1_R3_R2 ldf.fill.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x1B;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_LDF_FILL_NTA_F1_R3_R2 ldf.fill.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x1B;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_CLR_F1_R3_R2 ldfs.c.clr MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x22;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_CLR_NT1_F1_R3_R2 ldfs.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x22;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_CLR_NTA_F1_R3_R2 ldfs.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x22;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_CLR_F1_R3_R2 ldfd.c.clr MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x23;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_CLR_NT1_F1_R3_R2 ldfd.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x23;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_CLR_NTA_F1_R3_R2 ldfd.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x23;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_CLR_F1_R3_R2 ldf8.c.clr MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x21;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_CLR_NT1_F1_R3_R2 ldf8.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x21;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_CLR_NTA_F1_R3_R2 ldf8.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x21;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_CLR_F1_R3_R2 ldfe.c.clr MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x20;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_CLR_NT1_F1_R3_R2 ldfe.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x20;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_CLR_NTA_F1_R3_R2 ldfe.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x20;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_NC_F1_R3_R2 ldfs.c.nc MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x26;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_NC_NT1_F1_R3_R2 ldfs.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x26;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_NC_NTA_F1_R3_R2 ldfs.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x26;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_NC_F1_R3_R2 ldfd.c.nc MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x27;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_NC_NT1_F1_R3_R2 ldfd.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x27;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_NC_NTA_F1_R3_R2 ldfd.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x27;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_NC_F1_R3_R2 ldf8.c.nc MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x25;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_NC_NT1_F1_R3_R2 ldf8.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x25;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_NC_NTA_F1_R3_R2 ldf8.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x25;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_NC_F1_R3_R2 ldfe.c.nc MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x24;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_NC_NT1_F1_R3_R2 ldfe.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x24;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_NC_NTA_F1_R3_R2 ldfe.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M7 0x6 0x1;0x24;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_F1_R3_IMM9 ldfs MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x2;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_NT1_F1_R3_IMM9 ldfs.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x2;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_NTA_F1_R3_IMM9 ldfs.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x2;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_F1_R3_IMM9 ldfd MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x3;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_NT1_F1_R3_IMM9 ldfd.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x3;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_NTA_F1_R3_IMM9 ldfd.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x3;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_F1_R3_IMM9 ldf8 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_NT1_F1_R3_IMM9 ldf8.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_NTA_F1_R3_IMM9 ldf8.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_F1_R3_IMM9 ldfe MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_NT1_F1_R3_IMM9 ldfe.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_NTA_F1_R3_IMM9 ldfe.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_S_F1_R3_IMM9 ldfs.s MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x6;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_S_NT1_F1_R3_IMM9 ldfs.s.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x6;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_S_NTA_F1_R3_IMM9 ldfs.s.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x6;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_S_F1_R3_IMM9 ldfd.s MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x7;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_S_NT1_F1_R3_IMM9 ldfd.s.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x7;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_S_NTA_F1_R3_IMM9 ldfd.s.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x7;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_S_F1_R3_IMM9 ldf8.s MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x5;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_S_NT1_F1_R3_IMM9 ldf8.s.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x5;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_S_NTA_F1_R3_IMM9 ldf8.s.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x5;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_S_F1_R3_IMM9 ldfe.s MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x4;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_S_NT1_F1_R3_IMM9 ldfe.s.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x4;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_S_NTA_F1_R3_IMM9 ldfe.s.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x4;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_A_F1_R3_IMM9 ldfs.a MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xA;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_A_NT1_F1_R3_IMM9 ldfs.a.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xA;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_A_NTA_F1_R3_IMM9 ldfs.a.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xA;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_A_F1_R3_IMM9 ldfd.a MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xB;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_A_NT1_F1_R3_IMM9 ldfd.a.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xB;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_A_NTA_F1_R3_IMM9 ldfd.a.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xB;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_A_F1_R3_IMM9 ldf8.a MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x9;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_A_NT1_F1_R3_IMM9 ldf8.a.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x9;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_A_NTA_F1_R3_IMM9 ldf8.a.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x9;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_A_F1_R3_IMM9 ldfe.a MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x8;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_A_NT1_F1_R3_IMM9 ldfe.a.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x8;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_A_NTA_F1_R3_IMM9 ldfe.a.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x8;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_SA_F1_R3_IMM9 ldfs.sa MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xE;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_SA_NT1_F1_R3_IMM9 ldfs.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xE;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_SA_NTA_F1_R3_IMM9 ldfs.sa.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xE;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_SA_F1_R3_IMM9 ldfd.sa MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xF;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_SA_NT1_F1_R3_IMM9 ldfd.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xF;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_SA_NTA_F1_R3_IMM9 ldfd.sa.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xF;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_SA_F1_R3_IMM9 ldf8.sa MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xD;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_SA_NT1_F1_R3_IMM9 ldf8.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xD;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_SA_NTA_F1_R3_IMM9 ldf8.sa.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xD;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_SA_F1_R3_IMM9 ldfe.sa MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xC;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_SA_NT1_F1_R3_IMM9 ldfe.sa.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xC;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_SA_NTA_F1_R3_IMM9 ldfe.sa.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0xC;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF_FILL_F1_R3_IMM9 ldf.fill MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x1B;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF_FILL_NT1_F1_R3_IMM9 ldf.fill.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x1B;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF_FILL_NTA_F1_R3_IMM9 ldf.fill.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x1B;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_CLR_F1_R3_IMM9 ldfs.c.clr MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x22;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_CLR_NT1_F1_R3_IMM9 ldfs.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x22;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_CLR_NTA_F1_R3_IMM9 ldfs.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x22;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_CLR_F1_R3_IMM9 ldfd.c.clr MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x23;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_CLR_NT1_F1_R3_IMM9 ldfd.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x23;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_CLR_NTA_F1_R3_IMM9 ldfd.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x23;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_CLR_F1_R3_IMM9 ldf8.c.clr MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x21;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_CLR_NT1_F1_R3_IMM9 ldf8.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x21;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_CLR_NTA_F1_R3_IMM9 ldf8.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x21;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_CLR_F1_R3_IMM9 ldfe.c.clr MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x20;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_CLR_NT1_F1_R3_IMM9 ldfe.c.clr.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x20;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_CLR_NTA_F1_R3_IMM9 ldfe.c.clr.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x20;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_NC_F1_R3_IMM9 ldfs.c.nc MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x26;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_NC_NT1_F1_R3_IMM9 ldfs.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x26;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFS_C_NC_NTA_F1_R3_IMM9 ldfs.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x26;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_NC_F1_R3_IMM9 ldfd.c.nc MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x27;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_NC_NT1_F1_R3_IMM9 ldfd.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x27;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFD_C_NC_NTA_F1_R3_IMM9 ldfd.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x27;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_NC_F1_R3_IMM9 ldf8.c.nc MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x25;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_NC_NT1_F1_R3_IMM9 ldf8.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x25;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDF8_C_NC_NTA_F1_R3_IMM9 ldf8.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x25;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_NC_F1_R3_IMM9 ldfe.c.nc MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x24;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_NC_NT1_F1_R3_IMM9 ldfe.c.nc.nt1 MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x24;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFE_C_NC_NTA_F1_R3_IMM9 ldfe.c.nc.nta MEM DST;FREG_F2_127 SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M8 0x7 0x24;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFS_R3_F2 stfs MEM DST;MEM SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M9 0x6 0x0;0x32;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFS_NTA_R3_F2 stfs.nta MEM DST;MEM SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M9 0x6 0x0;0x32;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFD_R3_F2 stfd MEM DST;MEM SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M9 0x6 0x0;0x33;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFD_NTA_R3_F2 stfd.nta MEM DST;MEM SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M9 0x6 0x0;0x33;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STF8_R3_F2 stf8 MEM DST;MEM SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M9 0x6 0x0;0x31;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STF8_NTA_R3_F2 stf8.nta MEM DST;MEM SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M9 0x6 0x0;0x31;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFE_R3_F2 stfe MEM DST;MEM SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M9 0x6 0x0;0x30;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFE_NTA_R3_F2 stfe.nta MEM DST;MEM SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M9 0x6 0x0;0x30;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STF_SPILL_R3_F2 stf.spill MEM DST;MEM SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M9 0x6 0x0;0x3B;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STF_SPILL_NTA_R3_F2 stf.spill.nta MEM DST;MEM SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M9 0x6 0x0;0x3B;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFS_R3_F2_IMM9 stfs MEM DST;MEM SRC;FREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M10 0x7 0x32;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFS_NTA_R3_F2_IMM9 stfs.nta MEM DST;MEM SRC;FREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M10 0x7 0x32;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFD_R3_F2_IMM9 stfd MEM DST;MEM SRC;FREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M10 0x7 0x33;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFD_NTA_R3_F2_IMM9 stfd.nta MEM DST;MEM SRC;FREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M10 0x7 0x33;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STF8_R3_F2_IMM9 stf8 MEM DST;MEM SRC;FREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M10 0x7 0x31;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STF8_NTA_R3_F2_IMM9 stf8.nta MEM DST;MEM SRC;FREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M10 0x7 0x31;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFE_R3_F2_IMM9 stfe MEM DST;MEM SRC;FREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M10 0x7 0x30;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STFE_NTA_R3_F2_IMM9 stfe.nta MEM DST;MEM SRC;FREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M10 0x7 0x30;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STF_SPILL_R3_F2_IMM9 stf.spill MEM DST;MEM SRC;FREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M10 0x7 0x3B;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_STF_SPILL_NTA_R3_F2_IMM9 stf.spill.nta MEM DST;MEM SRC;FREG SRC;SIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001001 M10 0x7 0x3B;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_F1_F2_R3 ldfps MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x2;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_NT1_F1_F2_R3 ldfps.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x2;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_NTA_F1_F2_R3 ldfps.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x2;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_F1_F2_R3 ldfpd MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x3;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_NT1_F1_F2_R3 ldfpd.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x3;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_NTA_F1_F2_R3 ldfpd.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x3;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_F1_F2_R3 ldfp8 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_NT1_F1_F2_R3 ldfp8.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_NTA_F1_F2_R3 ldfp8.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x1;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_S_F1_F2_R3 ldfps.s MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x6;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_S_NT1_F1_F2_R3 ldfps.s.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x6;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_S_NTA_F1_F2_R3 ldfps.s.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x6;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_S_F1_F2_R3 ldfpd.s MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x7;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_S_NT1_F1_F2_R3 ldfpd.s.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x7;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_S_NTA_F1_F2_R3 ldfpd.s.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x7;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_S_F1_F2_R3 ldfp8.s MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x5;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_S_NT1_F1_F2_R3 ldfp8.s.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x5;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_S_NTA_F1_F2_R3 ldfp8.s.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x5;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_A_F1_F2_R3 ldfps.a MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xA;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_A_NT1_F1_F2_R3 ldfps.a.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xA;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_A_NTA_F1_F2_R3 ldfps.a.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xA;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_A_F1_F2_R3 ldfpd.a MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xB;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_A_NT1_F1_F2_R3 ldfpd.a.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xB;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_A_NTA_F1_F2_R3 ldfpd.a.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xB;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_A_F1_F2_R3 ldfp8.a MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x9;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_A_NT1_F1_F2_R3 ldfp8.a.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x9;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_A_NTA_F1_F2_R3 ldfp8.a.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x9;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_SA_F1_F2_R3 ldfps.sa MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xE;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_SA_NT1_F1_F2_R3 ldfps.sa.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xE;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_SA_NTA_F1_F2_R3 ldfps.sa.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xE;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_SA_F1_F2_R3 ldfpd.sa MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xF;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_SA_NT1_F1_F2_R3 ldfpd.sa.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xF;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_SA_NTA_F1_F2_R3 ldfpd.sa.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xF;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_SA_F1_F2_R3 ldfp8.sa MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xD;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_SA_NT1_F1_F2_R3 ldfp8.sa.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xD;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_SA_NTA_F1_F2_R3 ldfp8.sa.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0xD;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_CLR_F1_F2_R3 ldfps.c.clr MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x22;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_CLR_NT1_F1_F2_R3 ldfps.c.clr.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x22;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_CLR_NTA_F1_F2_R3 ldfps.c.clr.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x22;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_CLR_F1_F2_R3 ldfpd.c.clr MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x23;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_CLR_NT1_F1_F2_R3 ldfpd.c.clr.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x23;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_CLR_NTA_F1_F2_R3 ldfpd.c.clr.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x23;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_CLR_F1_F2_R3 ldfp8.c.clr MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x21;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_CLR_NT1_F1_F2_R3 ldfp8.c.clr.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x21;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_CLR_NTA_F1_F2_R3 ldfp8.c.clr.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x21;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_NC_F1_F2_R3 ldfps.c.nc MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x26;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_NC_NT1_F1_F2_R3 ldfps.c.nc.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x26;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_NC_NTA_F1_F2_R3 ldfps.c.nc.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x26;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_NC_F1_F2_R3 ldfpd.c.nc MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x27;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_NC_NT1_F1_F2_R3 ldfpd.c.nc.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x27;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_NC_NTA_F1_F2_R3 ldfpd.c.nc.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x27;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_NC_F1_F2_R3 ldfp8.c.nc MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x25;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_NC_NT1_F1_F2_R3 ldfp8.c.nc.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x25;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_NC_NTA_F1_F2_R3 ldfp8.c.nc.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000100000000101 M11 0x6 0x0;0x25;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_F1_F2_R3_8 ldfps MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x2;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_NT1_F1_F2_R3_8 ldfps.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x2;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_NTA_F1_F2_R3_8 ldfps.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x2;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_F1_F2_R3_16 ldfpd MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x3;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_NT1_F1_F2_R3_16 ldfpd.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x3;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_NTA_F1_F2_R3_16 ldfpd.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x3;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_F1_F2_R3_16 ldfp8 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_NT1_F1_F2_R3_16 ldfp8.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_NTA_F1_F2_R3_16 ldfp8.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x1;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_S_F1_F2_R3_8 ldfps.s MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x6;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_S_NT1_F1_F2_R3_8 ldfps.s.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x6;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_S_NTA_F1_F2_R3_8 ldfps.s.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x6;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_S_F1_F2_R3_16 ldfpd.s MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x7;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_S_NT1_F1_F2_R3_16 ldfpd.s.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x7;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_S_NTA_F1_F2_R3_16 ldfpd.s.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x7;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_S_F1_F2_R3_16 ldfp8.s MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x5;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_S_NT1_F1_F2_R3_16 ldfp8.s.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x5;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_S_NTA_F1_F2_R3_16 ldfp8.s.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x5;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_A_F1_F2_R3_8 ldfps.a MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xA;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_A_NT1_F1_F2_R3_8 ldfps.a.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xA;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_A_NTA_F1_F2_R3_8 ldfps.a.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xA;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_A_F1_F2_R3_16 ldfpd.a MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xB;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_A_NT1_F1_F2_R3_16 ldfpd.a.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xB;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_A_NTA_F1_F2_R3_16 ldfpd.a.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xB;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_A_F1_F2_R3_16 ldfp8.a MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x9;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_A_NT1_F1_F2_R3_16 ldfp8.a.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x9;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_A_NTA_F1_F2_R3_16 ldfp8.a.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x9;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_SA_F1_F2_R3_8 ldfps.sa MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xE;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_SA_NT1_F1_F2_R3_8 ldfps.sa.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xE;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_SA_NTA_F1_F2_R3_8 ldfps.sa.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xE;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_SA_F1_F2_R3_16 ldfpd.sa MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xF;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_SA_NT1_F1_F2_R3_16 ldfpd.sa.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xF;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_SA_NTA_F1_F2_R3_16 ldfpd.sa.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xF;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_SA_F1_F2_R3_16 ldfp8.sa MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xD;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_SA_NT1_F1_F2_R3_16 ldfp8.sa.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xD;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_SA_NTA_F1_F2_R3_16 ldfp8.sa.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0xD;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_CLR_F1_F2_R3_8 ldfps.c.clr MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x22;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_CLR_NT1_F1_F2_R3_8 ldfps.c.clr.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x22;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_CLR_NTA_F1_F2_R3_8 ldfps.c.clr.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x22;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_CLR_F1_F2_R3_16 ldfpd.c.clr MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x23;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_CLR_NT1_F1_F2_R3_16 ldfpd.c.clr.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x23;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_CLR_NTA_F1_F2_R3_16 ldfpd.c.clr.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x23;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_CLR_F1_F2_R3_16 ldfp8.c.clr MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x21;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_CLR_NT1_F1_F2_R3_16 ldfp8.c.clr.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x21;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_CLR_NTA_F1_F2_R3_16 ldfp8.c.clr.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x21;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_NC_F1_F2_R3_8 ldfps.c.nc MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x26;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_NC_NT1_F1_F2_R3_8 ldfps.c.nc.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x26;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPS_C_NC_NTA_F1_F2_R3_8 ldfps.c.nc.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;EIGHT NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x26;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_NC_F1_F2_R3_16 ldfpd.c.nc MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x27;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_NC_NT1_F1_F2_R3_16 ldfpd.c.nc.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x27;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFPD_C_NC_NTA_F1_F2_R3_16 ldfpd.c.nc.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x27;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_NC_F1_F2_R3_16 ldfp8.c.nc MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x25;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_NC_NT1_F1_F2_R3_16 ldfp8.c.nc.nt1 MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x25;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LDFP8_C_NC_NTA_F1_F2_R3_16 ldfp8.c.nc.nta MEM DST;FREG_F2_127 DST;FREG_F2_127 SRC;MEM SRC;SIXTEEN NONE;NONE NONE;NONE 00000000000000000000100000000101 M12 0x6 0x1;0x25;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_R3 lfetch MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2C;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_NT1_R3 lfetch.nt1 MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2C;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_NT2_R3 lfetch.nt2 MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2C;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_NTA_R3 lfetch.nta MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2C;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_R3 lfetch.excl MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2D;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_NT1_R3 lfetch.excl.nt1 MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2D;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_NT2_R3 lfetch.excl.nt2 MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2D;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_NTA_R3 lfetch.excl.nta MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2D;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_R3 lfetch.fault MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2E;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_NT1_R3 lfetch.fault.nt1 MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2E;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_NT2_R3 lfetch.fault.nt2 MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2E;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_NTA_R3 lfetch.fault.nta MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2E;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_R3 lfetch.fault.excl MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2F;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_NT1_R3 lfetch.fault.excl.nt1 MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2F;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_NT2_R3 lfetch.fault.excl.nt2 MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2F;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_NTA_R3 lfetch.fault.excl.nta MEM SRC;MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M13 0x6 0x0;0x2F;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_R3_R2 lfetch MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2C;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_NT1_R3_R2 lfetch.nt1 MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2C;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_NT2_R3_R2 lfetch.nt2 MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2C;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_NTA_R3_R2 lfetch.nta MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2C;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_R3_R2 lfetch.excl MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2D;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_NT1_R3_R2 lfetch.excl.nt1 MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2D;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_NT2_R3_R2 lfetch.excl.nt2 MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2D;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_NTA_R3_R2 lfetch.excl.nta MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2D;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_R3_R2 lfetch.fault MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2E;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_NT1_R3_R2 lfetch.fault.nt1 MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2E;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_NT2_R3_R2 lfetch.fault.nt2 MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2E;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_NTA_R3_R2 lfetch.fault.nta MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2E;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_R3_R2 lfetch.fault.excl MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2F;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_NT1_R3_R2 lfetch.fault.excl.nt1 MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2F;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_NT2_R3_R2 lfetch.fault.excl.nt2 MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2F;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_NTA_R3_R2 lfetch.fault.excl.nta MEM SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M14 0x6 0x1;0x2F;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_R3_IMM9 lfetch MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2C;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_NT1_R3_IMM9 lfetch.nt1 MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2C;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_NT2_R3_IMM9 lfetch.nt2 MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2C;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_NTA_R3_IMM9 lfetch.nta MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2C;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_R3_IMM9 lfetch.excl MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2D;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_NT1_R3_IMM9 lfetch.excl.nt1 MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2D;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_NT2_R3_IMM9 lfetch.excl.nt2 MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2D;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_EXCL_NTA_R3_IMM9 lfetch.excl.nta MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2D;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_R3_IMM9 lfetch.fault MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2E;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_NT1_R3_IMM9 lfetch.fault.nt1 MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2E;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_NT2_R3_IMM9 lfetch.fault.nt2 MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2E;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_NTA_R3_IMM9 lfetch.fault.nta MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2E;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_R3_IMM9 lfetch.fault.excl MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2F;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_NT1_R3_IMM9 lfetch.fault.excl.nt1 MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2F;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_NT2_R3_IMM9 lfetch.fault.excl.nt2 MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2F;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LFETCH_FAULT_EXCL_NTA_R3_IMM9 lfetch.fault.excl.nta MEM SRC;MEM SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000101 M15 0x7 0x2F;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG1_ACQ_R1_R3_R2_AR_CCV cmpxchg1.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG1_ACQ_NT1_R1_R3_R2_AR_CCV cmpxchg1.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG1_ACQ_NTA_R1_R3_R2_AR_CCV cmpxchg1.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x0;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG2_ACQ_R1_R3_R2_AR_CCV cmpxchg2.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG2_ACQ_NT1_R1_R3_R2_AR_CCV cmpxchg2.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG2_ACQ_NTA_R1_R3_R2_AR_CCV cmpxchg2.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x1;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG4_ACQ_R1_R3_R2_AR_CCV cmpxchg4.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x2;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG4_ACQ_NT1_R1_R3_R2_AR_CCV cmpxchg4.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x2;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG4_ACQ_NTA_R1_R3_R2_AR_CCV cmpxchg4.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x2;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG8_ACQ_R1_R3_R2_AR_CCV cmpxchg8.acq MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x3;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG8_ACQ_NT1_R1_R3_R2_AR_CCV cmpxchg8.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x3;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG8_ACQ_NTA_R1_R3_R2_AR_CCV cmpxchg8.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x3;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG1_REL_R1_R3_R2_AR_CCV cmpxchg1.rel MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x4;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG1_REL_NT1_R1_R3_R2_AR_CCV cmpxchg1.rel.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x4;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG1_REL_NTA_R1_R3_R2_AR_CCV cmpxchg1.rel.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x4;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG2_REL_R1_R3_R2_AR_CCV cmpxchg2.rel MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x5;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG2_REL_NT1_R1_R3_R2_AR_CCV cmpxchg2.rel.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x5;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG2_REL_NTA_R1_R3_R2_AR_CCV cmpxchg2.rel.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x5;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG4_REL_R1_R3_R2_AR_CCV cmpxchg4.rel MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x6;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG4_REL_NT1_R1_R3_R2_AR_CCV cmpxchg4.rel.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x6;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG4_REL_NTA_R1_R3_R2_AR_CCV cmpxchg4.rel.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x6;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG8_REL_R1_R3_R2_AR_CCV cmpxchg8.rel MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x7;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG8_REL_NT1_R1_R3_R2_AR_CCV cmpxchg8.rel.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x7;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CMPXCHG8_REL_NTA_R1_R3_R2_AR_CCV cmpxchg8.rel.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG SRC;APP_CCV NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x7;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG1_R1_R3_R2 xchg1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x8;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG1_NT1_R1_R3_R2 xchg1.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x8;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG1_NTA_R1_R3_R2 xchg1.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x8;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG2_R1_R3_R2 xchg2 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x9;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG2_NT1_R1_R3_R2 xchg2.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x9;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG2_NTA_R1_R3_R2 xchg2.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0x9;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG4_R1_R3_R2 xchg4 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0xA;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG4_NT1_R1_R3_R2 xchg4.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0xA;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG4_NTA_R1_R3_R2 xchg4.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0xA;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG8_R1_R3_R2 xchg8 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0xB;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG8_NT1_R1_R3_R2 xchg8.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0xB;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XCHG8_NTA_R1_R3_R2 xchg8.nta MEM DST;IREG_R1_127 SRC;MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M16 0x4 0x0;0xB;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD4_ACQ_R1_R3_INC3 fetchadd4.acq MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x12;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD4_ACQ_NT1_R1_R3_INC3 fetchadd4.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x12;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD4_ACQ_NTA_R1_R3_INC3 fetchadd4.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x12;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD8_ACQ_R1_R3_INC3 fetchadd8.acq MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x13;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD8_ACQ_NT1_R1_R3_INC3 fetchadd8.acq.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x13;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD8_ACQ_NTA_R1_R3_INC3 fetchadd8.acq.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x13;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD4_REL_R1_R3_INC3 fetchadd4.rel MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x16;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD4_REL_NT1_R1_R3_INC3 fetchadd4.rel.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x16;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD4_REL_NTA_R1_R3_INC3 fetchadd4.rel.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x16;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD8_REL_R1_R3_INC3 fetchadd8.rel MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x17;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD8_REL_NT1_R1_R3_INC3 fetchadd8.rel.nt1 MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x17;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FETCHADD8_REL_NTA_R1_R3_INC3 fetchadd8.rel.nta MEM DST;IREG_R1_127 SRC;MEM SRC;SEMAPHORE_INC NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000001101 M17 0x4 0x0;0x17;0x3;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SETF_SIG_F1_R2 setf.sig MEM DST;FREG_F2_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M18 0x6 0x0;0x1C;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SETF_EXP_F1_R2 setf.exp MEM DST;FREG_F2_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M18 0x6 0x0;0x1D;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SETF_S_F1_R2 setf.s MEM DST;FREG_F2_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M18 0x6 0x0;0x1E;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SETF_D_F1_R2 setf.d MEM DST;FREG_F2_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M18 0x6 0x0;0x1F;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_GETF_SIG_R1_F2 getf.sig MEM DST;IREG_R1_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M19 0x4 0x0;0x1C;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_GETF_EXP_R1_F2 getf.exp MEM DST;IREG_R1_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M19 0x4 0x0;0x1D;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_GETF_S_R1_F2 getf.s MEM DST;IREG_R1_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M19 0x4 0x0;0x1E;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_GETF_D_R1_F2 getf.d MEM DST;IREG_R1_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M19 0x4 0x0;0x1F;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CHK_S_M_R2_TARGET25 chk.s.m MEM SRC;IREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M20 0x1 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CHK_S_F2_TARGET25 chk.s MEM SRC;FREG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M21 0x1 0x3;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CHK_A_NC_R1_TARGET25 chk.a.nc MEM SRC;IREG_NUM SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M22 0x0 0x4;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CHK_A_CLR_R1_TARGET25 chk.a.clr MEM SRC;IREG_NUM SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M22 0x0 0x5;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CHK_A_NC_F1_TARGET25 chk.a.nc MEM SRC;FREG_NUM SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M23 0x0 0x6;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CHK_A_CLR_F1_TARGET25 chk.a.clr MEM SRC;FREG_NUM SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M23 0x0 0x7;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_INVALA invala MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M24 0x0 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FWB fwb MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M24 0x0 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MF mf MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M24 0x0 0x0;0x2;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MF_A mf.a MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M24 0x0 0x0;0x2;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SRLZ_D srlz.d MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M24 0x0 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SRLZ_I srlz.i MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M24 0x0 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SYNC_I sync.i MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M24 0x0 0x0;0x3;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FLUSHRS flushrs MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000101000 M25 0x0 0x0;0x0;0xC;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_LOADRS loadrs MEM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000100100 M25 0x0 0x0;0x0;0xA;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_INVALA_E_R1 invala.e MEM SRC;IREG_NUM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M26 0x0 0x0;0x1;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_INVALA_E_F1 invala.e MEM SRC;FREG_NUM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M27 0x0 0x0;0x1;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FC_R3 fc MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M28 0x1 0x0;0x30;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PTC_E_R3 ptc.e MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M28 0x1 0x0;0x34;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_M_AR3_R2 mov.m MEM DST;APP_REG_GRP_LOW SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M29 0x1 0x0;0x2A;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_M_AR3_IMM8 mov.m MEM DST;APP_REG_GRP_LOW SRC;SIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M30 0x0 0x0;0x2;0x8;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_M_R1_AR3 mov.m MEM DST;IREG_R1_127 SRC;APP_REG_GRP_LOW NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M31 0x1 0x0;0x22;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_CR3_R2 mov MEM DST;CR SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M32 0x1 0x0;0x2C;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_CR3 mov MEM DST;IREG_R1_127 SRC;CR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M33 0x1 0x0;0x24;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ALLOC_R1_AR_PFS_I_L_O_R alloc MEM DST;IREG_R1_127 SRC;APP_PFS SRC;ALLOC_IOL SRC;ALLOC_IOL SRC;ALLOC_IOL SRC;ALLOC_ROT 00000000000000000000000000100000 M34 0x1 0x6;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_PSR_L_R2 mov MEM DST;PSR_L SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M35 0x1 0x0;0x2D;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_PSR_UM_R2 mov MEM DST;PSR_UM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M35 0x1 0x0;0x29;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_PSR mov MEM DST;IREG_R1_127 SRC;PSR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M36 0x1 0x0;0x25;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_PSR_UM mov MEM DST;IREG_R1_127 SRC;PSR_UM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M36 0x1 0x0;0x21;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BREAK_M_IMM21 break.m MEM SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M37 0x0 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_NOP_M_IMM21 nop.m MEM SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M37 0x0 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PROBE_R_R1_R3_R2 probe.r MEM DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M38 0x1 0x0;0x38;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PROBE_W_R1_R3_R2 probe.w MEM DST;IREG_R1_127 SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M38 0x1 0x0;0x39;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PROBE_R_R1_R3_IMM2 probe.r MEM DST;IREG_R1_127 SRC;IREG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M39 0x1 0x0;0x18;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PROBE_W_R1_R3_IMM2 probe.w MEM DST;IREG_R1_127 SRC;IREG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M39 0x1 0x0;0x19;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PROBE_RW_FAULT_R3_IMM2 probe.rw.fault MEM SRC;IREG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M40 0x1 0x0;0x31;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PROBE_R_FAULT_R3_IMM2 probe.r.fault MEM SRC;IREG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M40 0x1 0x0;0x32;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PROBE_W_FAULT_R3_IMM2 probe.w.fault MEM SRC;IREG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M40 0x1 0x0;0x33;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ITC_D_R2 itc.d MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000001000011 M41 0x1 0x0;0x2E;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ITC_I_R2 itc.i MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000001000011 M41 0x1 0x0;0x2F;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_RR_R3_R2 mov MEM DST;RR SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M42 0x1 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_DBR_R3_R2 mov MEM DST;DBR SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M42 0x1 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_IBR_R3_R2 mov MEM DST;IBR SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M42 0x1 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_PKR_R3_R2 mov MEM DST;PKR SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M42 0x1 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_PMC_R3_R2 mov MEM DST;PMC SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M42 0x1 0x0;0x4;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_PMD_R3_R2 mov MEM DST;PMD SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M42 0x1 0x0;0x5;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_MSR_R3_R2 mov MEM DST;MSR SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M42 0x1 0x0;0x6;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Itanium
|
||
|
|
EM_ITR_D_DTR_R3_R2 itr.d MEM DST;DTR SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M42 0x1 0x0;0xE;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_ITR_I_ITR_R3_R2 itr.i MEM DST;ITR SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M42 0x1 0x0;0xF;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_RR_R3 mov MEM DST;IREG_R1_127 SRC;RR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M43 0x1 0x0;0x10;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_DBR_R3 mov MEM DST;IREG_R1_127 SRC;DBR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M43 0x1 0x0;0x11;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_IBR_R3 mov MEM DST;IREG_R1_127 SRC;IBR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M43 0x1 0x0;0x12;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_PKR_R3 mov MEM DST;IREG_R1_127 SRC;PKR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M43 0x1 0x0;0x13;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_PMC_R3 mov MEM DST;IREG_R1_127 SRC;PMC NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M43 0x1 0x0;0x14;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_MSR_R3 mov MEM DST;IREG_R1_127 SRC;MSR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M43 0x1 0x0;0x16;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Itanium
|
||
|
|
EM_MOV_R1_PMD_R3 mov MEM DST;IREG_R1_127 SRC;PMD NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M43 0x1 0x0;0x15;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOV_R1_CPUID_R3 mov MEM DST;IREG_R1_127 SRC;CPUID NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M43 0x1 0x0;0x17;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SUM_IMM24 sum MEM SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M44 0x0 0x0;0x4;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_RUM_IMM24 rum MEM SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M44 0x0 0x0;0x5;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_SSM_IMM24 ssm MEM SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M44 0x0 0x0;0x6;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_RSM_IMM24 rsm MEM SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M44 0x0 0x0;0x7;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PTC_L_R3_R2 ptc.l MEM SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M45 0x1 0x0;0x9;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PTC_G_R3_R2 ptc.g MEM SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000001000011 M45 0x1 0x0;0xA;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PTC_GA_R3_R2 ptc.ga MEM SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000001000011 M45 0x1 0x0;0xB;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PTR_D_R3_R2 ptr.d MEM SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M45 0x1 0x0;0xC;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_PTR_I_R3_R2 ptr.i MEM SRC;IREG SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M45 0x1 0x0;0xD;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_THASH_R1_R3 thash MEM DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M46 0x1 0x0;0x1A;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TTAG_R1_R3 ttag MEM DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 M46 0x1 0x0;0x1B;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TPA_R1_R3 tpa MEM DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M46 0x1 0x0;0x1E;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_TAK_R1_R3 tak MEM DST;IREG_R1_127 SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000011 M46 0x1 0x0;0x1F;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_HALT_R3 halt MEM SRC;IREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000010 M1001 0x1 0x0;0x3C;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Itanium
|
||
|
|
EM_BR_COND_SPTK_FEW_TARGET25 br.cond.sptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPTK_MANY_TARGET25 br.cond.sptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPNT_FEW_TARGET25 br.cond.spnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPNT_MANY_TARGET25 br.cond.spnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPTK_FEW_TARGET25 br.cond.dptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPTK_MANY_TARGET25 br.cond.dptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x0;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPNT_FEW_TARGET25 br.cond.dpnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPNT_MANY_TARGET25 br.cond.dpnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPTK_FEW_CLR_TARGET25 br.cond.sptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPTK_MANY_CLR_TARGET25 br.cond.sptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPNT_FEW_CLR_TARGET25 br.cond.spnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPNT_MANY_CLR_TARGET25 br.cond.spnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPTK_FEW_CLR_TARGET25 br.cond.dptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPTK_MANY_CLR_TARGET25 br.cond.dptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x1;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPNT_FEW_CLR_TARGET25 br.cond.dpnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPNT_MANY_CLR_TARGET25 br.cond.dpnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B1 0x4 0x1;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_SPTK_FEW_TARGET25 br.wexit.sptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x0;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_SPTK_MANY_TARGET25 br.wexit.sptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x0;0x1;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_SPNT_FEW_TARGET25 br.wexit.spnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x1;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_SPNT_MANY_TARGET25 br.wexit.spnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x1;0x1;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_DPTK_FEW_TARGET25 br.wexit.dptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x2;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_DPTK_MANY_TARGET25 br.wexit.dptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x2;0x1;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_DPNT_FEW_TARGET25 br.wexit.dpnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x3;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_DPNT_MANY_TARGET25 br.wexit.dpnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x3;0x1;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_SPTK_FEW_CLR_TARGET25 br.wexit.sptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x0;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_SPTK_MANY_CLR_TARGET25 br.wexit.sptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x0;0x1;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_SPNT_FEW_CLR_TARGET25 br.wexit.spnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x1;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_SPNT_MANY_CLR_TARGET25 br.wexit.spnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x1;0x1;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_DPTK_FEW_CLR_TARGET25 br.wexit.dptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x2;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_DPTK_MANY_CLR_TARGET25 br.wexit.dptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x2;0x1;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_DPNT_FEW_CLR_TARGET25 br.wexit.dpnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x3;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WEXIT_DPNT_MANY_CLR_TARGET25 br.wexit.dpnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x3;0x1;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_SPTK_FEW_TARGET25 br.wtop.sptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x0;0x0;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_SPTK_MANY_TARGET25 br.wtop.sptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x0;0x1;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_SPNT_FEW_TARGET25 br.wtop.spnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x1;0x0;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_SPNT_MANY_TARGET25 br.wtop.spnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x1;0x1;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_DPTK_FEW_TARGET25 br.wtop.dptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x2;0x0;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_DPTK_MANY_TARGET25 br.wtop.dptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x2;0x1;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_DPNT_FEW_TARGET25 br.wtop.dpnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x3;0x0;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_DPNT_MANY_TARGET25 br.wtop.dpnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x0;0x3;0x1;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_SPTK_FEW_CLR_TARGET25 br.wtop.sptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x0;0x0;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_SPTK_MANY_CLR_TARGET25 br.wtop.sptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x0;0x1;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_SPNT_FEW_CLR_TARGET25 br.wtop.spnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x1;0x0;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_SPNT_MANY_CLR_TARGET25 br.wtop.spnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x1;0x1;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_DPTK_FEW_CLR_TARGET25 br.wtop.dptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x2;0x0;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_DPTK_MANY_CLR_TARGET25 br.wtop.dptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x2;0x1;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_DPNT_FEW_CLR_TARGET25 br.wtop.dpnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x3;0x0;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_WTOP_DPNT_MANY_CLR_TARGET25 br.wtop.dpnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000001 B1 0x4 0x1;0x3;0x1;0x3;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_SPTK_FEW_TARGET25 br.cloop.sptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x0;0x0;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_SPTK_MANY_TARGET25 br.cloop.sptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x0;0x1;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_SPNT_FEW_TARGET25 br.cloop.spnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x1;0x0;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_SPNT_MANY_TARGET25 br.cloop.spnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x1;0x1;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_DPTK_FEW_TARGET25 br.cloop.dptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x2;0x0;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_DPTK_MANY_TARGET25 br.cloop.dptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x2;0x1;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_DPNT_FEW_TARGET25 br.cloop.dpnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x3;0x0;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_DPNT_MANY_TARGET25 br.cloop.dpnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x3;0x1;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_SPTK_FEW_CLR_TARGET25 br.cloop.sptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x0;0x0;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_SPTK_MANY_CLR_TARGET25 br.cloop.sptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x0;0x1;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_SPNT_FEW_CLR_TARGET25 br.cloop.spnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x1;0x0;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_SPNT_MANY_CLR_TARGET25 br.cloop.spnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x1;0x1;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_DPTK_FEW_CLR_TARGET25 br.cloop.dptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x2;0x0;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_DPTK_MANY_CLR_TARGET25 br.cloop.dptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x2;0x1;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_DPNT_FEW_CLR_TARGET25 br.cloop.dpnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x3;0x0;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CLOOP_DPNT_MANY_CLR_TARGET25 br.cloop.dpnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x3;0x1;0x5;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_SPTK_FEW_TARGET25 br.cexit.sptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x0;0x0;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_SPTK_MANY_TARGET25 br.cexit.sptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x0;0x1;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_SPNT_FEW_TARGET25 br.cexit.spnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x1;0x0;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_SPNT_MANY_TARGET25 br.cexit.spnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x1;0x1;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_DPTK_FEW_TARGET25 br.cexit.dptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x2;0x0;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_DPTK_MANY_TARGET25 br.cexit.dptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x2;0x1;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_DPNT_FEW_TARGET25 br.cexit.dpnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x3;0x0;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_DPNT_MANY_TARGET25 br.cexit.dpnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x3;0x1;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_SPTK_FEW_CLR_TARGET25 br.cexit.sptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x0;0x0;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_SPTK_MANY_CLR_TARGET25 br.cexit.sptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x0;0x1;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_SPNT_FEW_CLR_TARGET25 br.cexit.spnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x1;0x0;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_SPNT_MANY_CLR_TARGET25 br.cexit.spnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x1;0x1;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_DPTK_FEW_CLR_TARGET25 br.cexit.dptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x2;0x0;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_DPTK_MANY_CLR_TARGET25 br.cexit.dptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x2;0x1;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_DPNT_FEW_CLR_TARGET25 br.cexit.dpnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x3;0x0;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CEXIT_DPNT_MANY_CLR_TARGET25 br.cexit.dpnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x3;0x1;0x6;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_SPTK_FEW_TARGET25 br.ctop.sptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x0;0x0;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_SPTK_MANY_TARGET25 br.ctop.sptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x0;0x1;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_SPNT_FEW_TARGET25 br.ctop.spnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x1;0x0;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_SPNT_MANY_TARGET25 br.ctop.spnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x1;0x1;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_DPTK_FEW_TARGET25 br.ctop.dptk.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x2;0x0;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_DPTK_MANY_TARGET25 br.ctop.dptk.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x2;0x1;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_DPNT_FEW_TARGET25 br.ctop.dpnt.few BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x3;0x0;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_DPNT_MANY_TARGET25 br.ctop.dpnt.many BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x0;0x3;0x1;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_SPTK_FEW_CLR_TARGET25 br.ctop.sptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x0;0x0;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_SPTK_MANY_CLR_TARGET25 br.ctop.sptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x0;0x1;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_SPNT_FEW_CLR_TARGET25 br.ctop.spnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x1;0x0;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_SPNT_MANY_CLR_TARGET25 br.ctop.spnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x1;0x1;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_DPTK_FEW_CLR_TARGET25 br.ctop.dptk.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x2;0x0;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_DPTK_MANY_CLR_TARGET25 br.ctop.dptk.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x2;0x1;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_DPNT_FEW_CLR_TARGET25 br.ctop.dpnt.few.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x3;0x0;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CTOP_DPNT_MANY_CLR_TARGET25 br.ctop.dpnt.many.clr BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000100000000 B2 0x4 0x1;0x3;0x1;0x7;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPTK_FEW_B1_TARGET25 br.call.sptk.few BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPTK_MANY_B1_TARGET25 br.call.sptk.many BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPNT_FEW_B1_TARGET25 br.call.spnt.few BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPNT_MANY_B1_TARGET25 br.call.spnt.many BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPTK_FEW_B1_TARGET25 br.call.dptk.few BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPTK_MANY_B1_TARGET25 br.call.dptk.many BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x0;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPNT_FEW_B1_TARGET25 br.call.dpnt.few BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPNT_MANY_B1_TARGET25 br.call.dpnt.many BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPTK_FEW_CLR_B1_TARGET25 br.call.sptk.few.clr BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPTK_MANY_CLR_B1_TARGET25 br.call.sptk.many.clr BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPNT_FEW_CLR_B1_TARGET25 br.call.spnt.few.clr BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPNT_MANY_CLR_B1_TARGET25 br.call.spnt.many.clr BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPTK_FEW_CLR_B1_TARGET25 br.call.dptk.few.clr BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPTK_MANY_CLR_B1_TARGET25 br.call.dptk.many.clr BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x1;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPNT_FEW_CLR_B1_TARGET25 br.call.dpnt.few.clr BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPNT_MANY_CLR_B1_TARGET25 br.call.dpnt.many.clr BR DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B3 0x5 0x1;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPTK_FEW_B2 br.cond.sptk.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x0;0x20;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPTK_MANY_B2 br.cond.sptk.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x0;0x20;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPNT_FEW_B2 br.cond.spnt.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x1;0x20;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPNT_MANY_B2 br.cond.spnt.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x1;0x20;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPTK_FEW_B2 br.cond.dptk.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x2;0x20;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPTK_MANY_B2 br.cond.dptk.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x2;0x20;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPNT_FEW_B2 br.cond.dpnt.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x3;0x20;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPNT_MANY_B2 br.cond.dpnt.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x3;0x20;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPTK_FEW_CLR_B2 br.cond.sptk.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x0;0x20;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPTK_MANY_CLR_B2 br.cond.sptk.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x0;0x20;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPNT_FEW_CLR_B2 br.cond.spnt.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x1;0x20;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_SPNT_MANY_CLR_B2 br.cond.spnt.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x1;0x20;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPTK_FEW_CLR_B2 br.cond.dptk.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x2;0x20;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPTK_MANY_CLR_B2 br.cond.dptk.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x2;0x20;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPNT_FEW_CLR_B2 br.cond.dpnt.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x3;0x20;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_COND_DPNT_MANY_CLR_B2 br.cond.dpnt.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x3;0x20;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_SPTK_FEW_B2 br.ia.sptk.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x0;0x20;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_SPTK_MANY_B2 br.ia.sptk.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x0;0x20;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_SPNT_FEW_B2 br.ia.spnt.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x1;0x20;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_SPNT_MANY_B2 br.ia.spnt.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x1;0x20;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_DPTK_FEW_B2 br.ia.dptk.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x2;0x20;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_DPTK_MANY_B2 br.ia.dptk.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x2;0x20;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_DPNT_FEW_B2 br.ia.dpnt.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x3;0x20;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_DPNT_MANY_B2 br.ia.dpnt.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x3;0x20;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_SPTK_FEW_CLR_B2 br.ia.sptk.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x0;0x20;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_SPTK_MANY_CLR_B2 br.ia.sptk.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x0;0x20;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_SPNT_FEW_CLR_B2 br.ia.spnt.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x1;0x20;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_SPNT_MANY_CLR_B2 br.ia.spnt.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x1;0x20;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_DPTK_FEW_CLR_B2 br.ia.dptk.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x2;0x20;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_DPTK_MANY_CLR_B2 br.ia.dptk.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x2;0x20;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_DPNT_FEW_CLR_B2 br.ia.dpnt.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x3;0x20;0x0;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_IA_DPNT_MANY_CLR_B2 br.ia.dpnt.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x3;0x20;0x1;0x1;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_SPTK_FEW_B2 br.ret.sptk.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x0;0x21;0x0;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_SPTK_MANY_B2 br.ret.sptk.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x0;0x21;0x1;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_SPNT_FEW_B2 br.ret.spnt.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x1;0x21;0x0;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_SPNT_MANY_B2 br.ret.spnt.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x1;0x21;0x1;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_DPTK_FEW_B2 br.ret.dptk.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x2;0x21;0x0;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_DPTK_MANY_B2 br.ret.dptk.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x2;0x21;0x1;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_DPNT_FEW_B2 br.ret.dpnt.few BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x3;0x21;0x0;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_DPNT_MANY_B2 br.ret.dpnt.many BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x0;0x3;0x21;0x1;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_SPTK_FEW_CLR_B2 br.ret.sptk.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x0;0x21;0x0;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_SPTK_MANY_CLR_B2 br.ret.sptk.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x0;0x21;0x1;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_SPNT_FEW_CLR_B2 br.ret.spnt.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x1;0x21;0x0;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_SPNT_MANY_CLR_B2 br.ret.spnt.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x1;0x21;0x1;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_DPTK_FEW_CLR_B2 br.ret.dptk.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x2;0x21;0x0;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_DPTK_MANY_CLR_B2 br.ret.dptk.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x2;0x21;0x1;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_DPNT_FEW_CLR_B2 br.ret.dpnt.few.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x3;0x21;0x0;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_RET_DPNT_MANY_CLR_B2 br.ret.dpnt.many.clr BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B4 0x0 0x1;0x3;0x21;0x1;0x4;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPTK_FEW_B1_B2 br.call.sptk.few BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPTK_MANY_B1_B2 br.call.sptk.many BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPNT_FEW_B1_B2 br.call.spnt.few BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPNT_MANY_B1_B2 br.call.spnt.many BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPTK_FEW_B1_B2 br.call.dptk.few BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x0;0x5;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPTK_MANY_B1_B2 br.call.dptk.many BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x0;0x5;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPNT_FEW_B1_B2 br.call.dpnt.few BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x0;0x7;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPNT_MANY_B1_B2 br.call.dpnt.many BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x0;0x7;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPTK_FEW_CLR_B1_B2 br.call.sptk.few.clr BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPTK_MANY_CLR_B1_B2 br.call.sptk.many.clr BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPNT_FEW_CLR_B1_B2 br.call.spnt.few.clr BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_SPNT_MANY_CLR_B1_B2 br.call.spnt.many.clr BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x1;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPTK_FEW_CLR_B1_B2 br.call.dptk.few.clr BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x1;0x5;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPTK_MANY_CLR_B1_B2 br.call.dptk.many.clr BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x1;0x5;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPNT_FEW_CLR_B1_B2 br.call.dpnt.few.clr BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x1;0x7;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BR_CALL_DPNT_MANY_CLR_B1_B2 br.call.dpnt.many.clr BR DST;BR SRC;BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B5 0x1 0x1;0x7;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_SPTK_TARGET25_TAG13 brp.sptk BR SRC;SSHIFT_REL SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B6 0x7 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_SPTK_IMP_TARGET25_TAG13 brp.sptk.imp BR SRC;SSHIFT_REL SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B6 0x7 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_LOOP_TARGET25_TAG13 brp.loop BR SRC;SSHIFT_REL SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B6 0x7 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_LOOP_IMP_TARGET25_TAG13 brp.loop.imp BR SRC;SSHIFT_REL SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B6 0x7 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_DPTK_TARGET25_TAG13 brp.dptk BR SRC;SSHIFT_REL SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B6 0x7 0x0;0x0;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_DPTK_IMP_TARGET25_TAG13 brp.dptk.imp BR SRC;SSHIFT_REL SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B6 0x7 0x1;0x0;0x2;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_EXIT_TARGET25_TAG13 brp.exit BR SRC;SSHIFT_REL SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B6 0x7 0x0;0x0;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_EXIT_IMP_TARGET25_TAG13 brp.exit.imp BR SRC;SSHIFT_REL SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B6 0x7 0x1;0x0;0x3;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_SPTK_B2_TAG13 brp.sptk BR SRC;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B7 0x2 0x0;0x10;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_SPTK_IMP_B2_TAG13 brp.sptk.imp BR SRC;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B7 0x2 0x1;0x10;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_DPTK_B2_TAG13 brp.dptk BR SRC;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B7 0x2 0x0;0x10;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_DPTK_IMP_B2_TAG13 brp.dptk.imp BR SRC;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B7 0x2 0x1;0x10;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_RET_SPTK_B2_TAG13 brp.ret.sptk BR SRC;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B7 0x2 0x0;0x11;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_RET_SPTK_IMP_B2_TAG13 brp.ret.sptk.imp BR SRC;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B7 0x2 0x1;0x11;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_RET_DPTK_B2_TAG13 brp.ret.dptk BR SRC;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B7 0x2 0x0;0x11;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRP_RET_DPTK_IMP_B2_TAG13 brp.ret.dptk.imp BR SRC;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B7 0x2 0x1;0x11;0x0;0x2;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_COVER cover BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000001000000 B8 0x0 0x2;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CLRRRB clrrrb BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000001000000 B8 0x0 0x4;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_CLRRRB_PR clrrrb.pr BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000001000000 B8 0x0 0x5;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_RFI rfi BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000001000010 B8 0x0 0x8;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_RFI_X rfi.x BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000001000010 B8 0x0 0x9;0x0;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Itanium
|
||
|
|
EM_BSW_0 bsw.0 BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000001000010 B8 0x0 0xC;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BSW_1 bsw.1 BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000001000010 B8 0x0 0xD;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_EPC epc BR NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000000 B8 0x0 0x10;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BREAK_B_IMM21 break.b BR SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000000000000001 B9 0x0 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_NOP_B_IMM21 nop.b BR SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 B9 0x2 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_S0_F1_F3_F4_F2 fma.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x8 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_S1_F1_F3_F4_F2 fma.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x8 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_S2_F1_F3_F4_F2 fma.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x8 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_S3_F1_F3_F4_F2 fma.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x8 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_S_S0_F1_F3_F4_F2 fma.s.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x8 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_S_S1_F1_F3_F4_F2 fma.s.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x8 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_S_S2_F1_F3_F4_F2 fma.s.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x8 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_S_S3_F1_F3_F4_F2 fma.s.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x8 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_D_S0_F1_F3_F4_F2 fma.d.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x9 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_D_S1_F1_F3_F4_F2 fma.d.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x9 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_D_S2_F1_F3_F4_F2 fma.d.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x9 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMA_D_S3_F1_F3_F4_F2 fma.d.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x9 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMA_S0_F1_F3_F4_F2 fpma.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x9 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMA_S1_F1_F3_F4_F2 fpma.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x9 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMA_S2_F1_F3_F4_F2 fpma.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x9 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMA_S3_F1_F3_F4_F2 fpma.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0x9 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_S0_F1_F3_F4_F2 fms.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xA 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_S1_F1_F3_F4_F2 fms.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xA 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_S2_F1_F3_F4_F2 fms.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xA 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_S3_F1_F3_F4_F2 fms.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xA 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_S_S0_F1_F3_F4_F2 fms.s.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xA 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_S_S1_F1_F3_F4_F2 fms.s.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xA 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_S_S2_F1_F3_F4_F2 fms.s.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xA 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_S_S3_F1_F3_F4_F2 fms.s.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xA 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_D_S0_F1_F3_F4_F2 fms.d.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xB 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_D_S1_F1_F3_F4_F2 fms.d.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xB 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_D_S2_F1_F3_F4_F2 fms.d.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xB 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMS_D_S3_F1_F3_F4_F2 fms.d.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xB 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMS_S0_F1_F3_F4_F2 fpms.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xB 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMS_S1_F1_F3_F4_F2 fpms.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xB 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMS_S2_F1_F3_F4_F2 fpms.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xB 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMS_S3_F1_F3_F4_F2 fpms.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xB 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FNMA_S0_F1_F3_F4_F2 fnma.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xC 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FNMA_S1_F1_F3_F4_F2 fnma.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xC 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FNMA_S2_F1_F3_F4_F2 fnma.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xC 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FNMA_S3_F1_F3_F4_F2 fnma.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xC 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FNMA_S_S0_F1_F3_F4_F2 fnma.s.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xC 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FNMA_S_S1_F1_F3_F4_F2 fnma.s.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xC 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FNMA_S_S2_F1_F3_F4_F2 fnma.s.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xC 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FNMA_S_S3_F1_F3_F4_F2 fnma.s.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xC 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FNMA_D_S0_F1_F3_F4_F2 fnma.d.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xD 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_FNMA_D_S1_F1_F3_F4_F2 fnma.d.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xD 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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EM_FNMA_D_S2_F1_F3_F4_F2 fnma.d.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xD 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FNMA_D_S3_F1_F3_F4_F2 fnma.d.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xD 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPNMA_S0_F1_F3_F4_F2 fpnma.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xD 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_FPNMA_S1_F1_F3_F4_F2 fpnma.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xD 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_FPNMA_S2_F1_F3_F4_F2 fpnma.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xD 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_FPNMA_S3_F1_F3_F4_F2 fpnma.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F1 0xD 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
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EM_XMA_L_F1_F3_F4_F2 xma.l FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F2 0xE 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XMA_H_F1_F3_F4_F2 xma.h FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F2 0xE 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_XMA_HU_F1_F3_F4_F2 xma.hu FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F2 0xE 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FSELECT_F1_F3_F4_F2 fselect FP DST;FREG_F2_127 SRC;FREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F3 0xE 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_EQ_S0_P1_P2_F2_F3 fcmp.eq.s0 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_EQ_S1_P1_P2_F2_F3 fcmp.eq.s1 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_EQ_S2_P1_P2_F2_F3 fcmp.eq.s2 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_EQ_S3_P1_P2_F2_F3 fcmp.eq.s3 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LT_S0_P1_P2_F2_F3 fcmp.lt.s0 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LT_S1_P1_P2_F2_F3 fcmp.lt.s1 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LT_S2_P1_P2_F2_F3 fcmp.lt.s2 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LT_S3_P1_P2_F2_F3 fcmp.lt.s3 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LE_S0_P1_P2_F2_F3 fcmp.le.s0 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LE_S1_P1_P2_F2_F3 fcmp.le.s1 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LE_S2_P1_P2_F2_F3 fcmp.le.s2 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x0;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LE_S3_P1_P2_F2_F3 fcmp.le.s3 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_UNORD_S0_P1_P2_F2_F3 fcmp.unord.s0 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_UNORD_S1_P1_P2_F2_F3 fcmp.unord.s1 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_UNORD_S2_P1_P2_F2_F3 fcmp.unord.s2 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x1;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_UNORD_S3_P1_P2_F2_F3 fcmp.unord.s3 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000010000001 F4 0x4 0x1;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_EQ_UNC_S0_P1_P2_F2_F3 fcmp.eq.unc.s0 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x0;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_EQ_UNC_S1_P1_P2_F2_F3 fcmp.eq.unc.s1 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x0;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_EQ_UNC_S2_P1_P2_F2_F3 fcmp.eq.unc.s2 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x0;0x2;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_EQ_UNC_S3_P1_P2_F2_F3 fcmp.eq.unc.s3 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x0;0x3;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LT_UNC_S0_P1_P2_F2_F3 fcmp.lt.unc.s0 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x1;0x0;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LT_UNC_S1_P1_P2_F2_F3 fcmp.lt.unc.s1 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x1;0x1;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LT_UNC_S2_P1_P2_F2_F3 fcmp.lt.unc.s2 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x1;0x2;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LT_UNC_S3_P1_P2_F2_F3 fcmp.lt.unc.s3 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x1;0x3;0x0;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LE_UNC_S0_P1_P2_F2_F3 fcmp.le.unc.s0 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x0;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LE_UNC_S1_P1_P2_F2_F3 fcmp.le.unc.s1 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x0;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LE_UNC_S2_P1_P2_F2_F3 fcmp.le.unc.s2 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x0;0x2;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_LE_UNC_S3_P1_P2_F2_F3 fcmp.le.unc.s3 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x0;0x3;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_UNORD_UNC_S0_P1_P2_F2_F3 fcmp.unord.unc.s0 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x1;0x0;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_UNORD_UNC_S1_P1_P2_F2_F3 fcmp.unord.unc.s1 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x1;0x1;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_UNORD_UNC_S2_P1_P2_F2_F3 fcmp.unord.unc.s2 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x1;0x2;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCMP_UNORD_UNC_S3_P1_P2_F2_F3 fcmp.unord.unc.s3 FP DST;PREG DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000001000010000001 F4 0x4 0x1;0x3;0x1;0x1;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCLASS_M_P1_P2_F2_FCLASS9 fclass.m FP DST;PREG DST;PREG SRC;FREG SRC;FCLASS NONE;NONE NONE;NONE 00000000000000000000000010000001 F5 0x5 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCLASS_M_UNC_P1_P2_F2_FCLASS9 fclass.m.unc FP DST;PREG DST;PREG SRC;FREG SRC;FCLASS NONE;NONE NONE;NONE 00000000000000000001000010000001 F5 0x5 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FRCPA_S0_F1_P2_F2_F3 frcpa.s0 FP DST;FREG_F2_127 DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F6 0x0 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FRCPA_S1_F1_P2_F2_F3 frcpa.s1 FP DST;FREG_F2_127 DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F6 0x0 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FRCPA_S2_F1_P2_F2_F3 frcpa.s2 FP DST;FREG_F2_127 DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F6 0x0 0x0;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FRCPA_S3_F1_P2_F2_F3 frcpa.s3 FP DST;FREG_F2_127 DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F6 0x0 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPRCPA_S0_F1_P2_F2_F3 fprcpa.s0 FP DST;FREG_F2_127 DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F6 0x1 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPRCPA_S1_F1_P2_F2_F3 fprcpa.s1 FP DST;FREG_F2_127 DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F6 0x1 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPRCPA_S2_F1_P2_F2_F3 fprcpa.s2 FP DST;FREG_F2_127 DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F6 0x1 0x0;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPRCPA_S3_F1_P2_F2_F3 fprcpa.s3 FP DST;FREG_F2_127 DST;PREG SRC;FREG SRC;FREG NONE;NONE NONE;NONE 00000000000000000000000000000001 F6 0x1 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FRSQRTA_S0_F1_P2_F3 frsqrta.s0 FP DST;FREG_F2_127 DST;PREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F7 0x0 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FRSQRTA_S1_F1_P2_F3 frsqrta.s1 FP DST;FREG_F2_127 DST;PREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F7 0x0 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FRSQRTA_S2_F1_P2_F3 frsqrta.s2 FP DST;FREG_F2_127 DST;PREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F7 0x0 0x1;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FRSQRTA_S3_F1_P2_F3 frsqrta.s3 FP DST;FREG_F2_127 DST;PREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F7 0x0 0x1;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPRSQRTA_S0_F1_P2_F3 fprsqrta.s0 FP DST;FREG_F2_127 DST;PREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F7 0x1 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPRSQRTA_S1_F1_P2_F3 fprsqrta.s1 FP DST;FREG_F2_127 DST;PREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F7 0x1 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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|
EM_FPRSQRTA_S2_F1_P2_F3 fprsqrta.s2 FP DST;FREG_F2_127 DST;PREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F7 0x1 0x1;0x2;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPRSQRTA_S3_F1_P2_F3 fprsqrta.s3 FP DST;FREG_F2_127 DST;PREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F7 0x1 0x1;0x3;0x1;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMIN_S0_F1_F2_F3 fmin.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x0;0x0;0x14;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMIN_S1_F1_F2_F3 fmin.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x1;0x0;0x14;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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|
EM_FMIN_S2_F1_F2_F3 fmin.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x2;0x0;0x14;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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|
EM_FMIN_S3_F1_F2_F3 fmin.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x3;0x0;0x14;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMAX_S0_F1_F2_F3 fmax.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x0;0x0;0x15;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMAX_S1_F1_F2_F3 fmax.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x1;0x0;0x15;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMAX_S2_F1_F2_F3 fmax.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x2;0x0;0x15;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
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|
EM_FMAX_S3_F1_F2_F3 fmax.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x3;0x0;0x15;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FAMIN_S0_F1_F2_F3 famin.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x0;0x0;0x16;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FAMIN_S1_F1_F2_F3 famin.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x1;0x0;0x16;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FAMIN_S2_F1_F2_F3 famin.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x2;0x0;0x16;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FAMIN_S3_F1_F2_F3 famin.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x3;0x0;0x16;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FAMAX_S0_F1_F2_F3 famax.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x0;0x0;0x17;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FAMAX_S1_F1_F2_F3 famax.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x1;0x0;0x17;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FAMAX_S2_F1_F2_F3 famax.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x2;0x0;0x17;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FAMAX_S3_F1_F2_F3 famax.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x0 0x3;0x0;0x17;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMIN_S0_F1_F2_F3 fpmin.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x14;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMIN_S1_F1_F2_F3 fpmin.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x14;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMIN_S2_F1_F2_F3 fpmin.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x14;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMIN_S3_F1_F2_F3 fpmin.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x14;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMAX_S0_F1_F2_F3 fpmax.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x15;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMAX_S1_F1_F2_F3 fpmax.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x15;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMAX_S2_F1_F2_F3 fpmax.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x15;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMAX_S3_F1_F2_F3 fpmax.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x15;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPAMIN_S0_F1_F2_F3 fpamin.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x16;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPAMIN_S1_F1_F2_F3 fpamin.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x16;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPAMIN_S2_F1_F2_F3 fpamin.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x16;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPAMIN_S3_F1_F2_F3 fpamin.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x16;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPAMAX_S0_F1_F2_F3 fpamax.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x17;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPAMAX_S1_F1_F2_F3 fpamax.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x17;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPAMAX_S2_F1_F2_F3 fpamax.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x17;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPAMAX_S3_F1_F2_F3 fpamax.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x17;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_EQ_S0_F1_F2_F3 fpcmp.eq.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x30;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_EQ_S1_F1_F2_F3 fpcmp.eq.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x30;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_EQ_S2_F1_F2_F3 fpcmp.eq.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x30;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_EQ_S3_F1_F2_F3 fpcmp.eq.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x30;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_LT_S0_F1_F2_F3 fpcmp.lt.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x31;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_LT_S1_F1_F2_F3 fpcmp.lt.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x31;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_LT_S2_F1_F2_F3 fpcmp.lt.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x31;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_LT_S3_F1_F2_F3 fpcmp.lt.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x31;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_LE_S0_F1_F2_F3 fpcmp.le.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x32;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_LE_S1_F1_F2_F3 fpcmp.le.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x32;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_LE_S2_F1_F2_F3 fpcmp.le.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x32;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_LE_S3_F1_F2_F3 fpcmp.le.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x32;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_UNORD_S0_F1_F2_F3 fpcmp.unord.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x33;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_UNORD_S1_F1_F2_F3 fpcmp.unord.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x33;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_UNORD_S2_F1_F2_F3 fpcmp.unord.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x33;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_UNORD_S3_F1_F2_F3 fpcmp.unord.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x33;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NEQ_S0_F1_F2_F3 fpcmp.neq.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x34;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NEQ_S1_F1_F2_F3 fpcmp.neq.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x34;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NEQ_S2_F1_F2_F3 fpcmp.neq.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x34;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NEQ_S3_F1_F2_F3 fpcmp.neq.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x34;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NLT_S0_F1_F2_F3 fpcmp.nlt.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x35;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NLT_S1_F1_F2_F3 fpcmp.nlt.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x35;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NLT_S2_F1_F2_F3 fpcmp.nlt.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x35;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NLT_S3_F1_F2_F3 fpcmp.nlt.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x35;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NLE_S0_F1_F2_F3 fpcmp.nle.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x36;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NLE_S1_F1_F2_F3 fpcmp.nle.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x36;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NLE_S2_F1_F2_F3 fpcmp.nle.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x36;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_NLE_S3_F1_F2_F3 fpcmp.nle.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x36;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_ORD_S0_F1_F2_F3 fpcmp.ord.s0 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x0;0x0;0x37;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_ORD_S1_F1_F2_F3 fpcmp.ord.s1 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x1;0x0;0x37;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_ORD_S2_F1_F2_F3 fpcmp.ord.s2 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x2;0x0;0x37;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCMP_ORD_S3_F1_F2_F3 fpcmp.ord.s3 FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F8 0x1 0x3;0x0;0x37;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMERGE_S_F1_F2_F3 fmerge.s FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x10;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMERGE_NS_F1_F2_F3 fmerge.ns FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x11;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMERGE_SE_F1_F2_F3 fmerge.se FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x12;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMIX_LR_F1_F2_F3 fmix.lr FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x39;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMIX_R_F1_F2_F3 fmix.r FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x3A;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FMIX_L_F1_F2_F3 fmix.l FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x3B;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FSXT_R_F1_F2_F3 fsxt.r FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x3C;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FSXT_L_F1_F2_F3 fsxt.l FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x3D;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPACK_F1_F2_F3 fpack FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x28;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FSWAP_F1_F2_F3 fswap FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x34;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FSWAP_NL_F1_F2_F3 fswap.nl FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x35;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FSWAP_NR_F1_F2_F3 fswap.nr FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x36;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FAND_F1_F2_F3 fand FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x2C;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FANDCM_F1_F2_F3 fandcm FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x2D;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FOR_F1_F2_F3 for FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x2E;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FXOR_F1_F2_F3 fxor FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x0 0x0;0x2F;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMERGE_S_F1_F2_F3 fpmerge.s FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x1 0x0;0x10;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMERGE_NS_F1_F2_F3 fpmerge.ns FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x1 0x0;0x11;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPMERGE_SE_F1_F2_F3 fpmerge.se FP DST;FREG_F2_127 SRC;FREG SRC;FREG NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F9 0x1 0x0;0x12;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FX_S0_F1_F2 fcvt.fx.s0 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x0;0x0;0x18;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FX_S1_F1_F2 fcvt.fx.s1 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x1;0x0;0x18;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FX_S2_F1_F2 fcvt.fx.s2 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x2;0x0;0x18;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FX_S3_F1_F2 fcvt.fx.s3 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x3;0x0;0x18;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FXU_S0_F1_F2 fcvt.fxu.s0 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x0;0x0;0x19;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FXU_S1_F1_F2 fcvt.fxu.s1 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x1;0x0;0x19;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FXU_S2_F1_F2 fcvt.fxu.s2 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x2;0x0;0x19;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FXU_S3_F1_F2 fcvt.fxu.s3 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x3;0x0;0x19;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FX_TRUNC_S0_F1_F2 fcvt.fx.trunc.s0 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x0;0x0;0x1A;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FX_TRUNC_S1_F1_F2 fcvt.fx.trunc.s1 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x1;0x0;0x1A;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FX_TRUNC_S2_F1_F2 fcvt.fx.trunc.s2 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x2;0x0;0x1A;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FX_TRUNC_S3_F1_F2 fcvt.fx.trunc.s3 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x3;0x0;0x1A;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FXU_TRUNC_S0_F1_F2 fcvt.fxu.trunc.s0 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x0;0x0;0x1B;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FXU_TRUNC_S1_F1_F2 fcvt.fxu.trunc.s1 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x1;0x0;0x1B;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FXU_TRUNC_S2_F1_F2 fcvt.fxu.trunc.s2 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x2;0x0;0x1B;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_FXU_TRUNC_S3_F1_F2 fcvt.fxu.trunc.s3 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x0 0x3;0x0;0x1B;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FX_S0_F1_F2 fpcvt.fx.s0 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x0;0x0;0x18;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FX_S1_F1_F2 fpcvt.fx.s1 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x1;0x0;0x18;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FX_S2_F1_F2 fpcvt.fx.s2 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x2;0x0;0x18;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FX_S3_F1_F2 fpcvt.fx.s3 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x3;0x0;0x18;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FXU_S0_F1_F2 fpcvt.fxu.s0 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x0;0x0;0x19;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FXU_S1_F1_F2 fpcvt.fxu.s1 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x1;0x0;0x19;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FXU_S2_F1_F2 fpcvt.fxu.s2 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x2;0x0;0x19;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FXU_S3_F1_F2 fpcvt.fxu.s3 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x3;0x0;0x19;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FX_TRUNC_S0_F1_F2 fpcvt.fx.trunc.s0 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x0;0x0;0x1A;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FX_TRUNC_S1_F1_F2 fpcvt.fx.trunc.s1 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x1;0x0;0x1A;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FX_TRUNC_S2_F1_F2 fpcvt.fx.trunc.s2 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x2;0x0;0x1A;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FX_TRUNC_S3_F1_F2 fpcvt.fx.trunc.s3 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x3;0x0;0x1A;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FXU_TRUNC_S0_F1_F2 fpcvt.fxu.trunc.s0 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x0;0x0;0x1B;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FXU_TRUNC_S1_F1_F2 fpcvt.fxu.trunc.s1 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x1;0x0;0x1B;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FXU_TRUNC_S2_F1_F2 fpcvt.fxu.trunc.s2 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x2;0x0;0x1B;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FPCVT_FXU_TRUNC_S3_F1_F2 fpcvt.fxu.trunc.s3 FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F10 0x1 0x3;0x0;0x1B;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCVT_XF_F1_F2 fcvt.xf FP DST;FREG_F2_127 SRC;FREG NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F11 0x0 0x0;0x1C;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FSETC_S0_AMASK7_OMASK7 fsetc.s0 FP SRC;UIMM SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F12 0x0 0x0;0x0;0x4;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FSETC_S1_AMASK7_OMASK7 fsetc.s1 FP SRC;UIMM SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F12 0x0 0x1;0x0;0x4;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FSETC_S2_AMASK7_OMASK7 fsetc.s2 FP SRC;UIMM SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F12 0x0 0x2;0x0;0x4;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FSETC_S3_AMASK7_OMASK7 fsetc.s3 FP SRC;UIMM SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F12 0x0 0x3;0x0;0x4;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCLRF_S0 fclrf.s0 FP NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F13 0x0 0x0;0x0;0x5;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCLRF_S1 fclrf.s1 FP NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F13 0x0 0x1;0x0;0x5;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCLRF_S2 fclrf.s2 FP NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F13 0x0 0x2;0x0;0x5;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCLRF_S3 fclrf.s3 FP NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F13 0x0 0x3;0x0;0x5;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCHKF_S0_TARGET25 fchkf.s0 FP SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F14 0x0 0x0;0x0;0x8;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCHKF_S1_TARGET25 fchkf.s1 FP SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F14 0x0 0x1;0x0;0x8;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCHKF_S2_TARGET25 fchkf.s2 FP SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F14 0x0 0x2;0x0;0x8;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_FCHKF_S3_TARGET25 fchkf.s3 FP SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F14 0x0 0x3;0x0;0x8;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BREAK_F_IMM21 break.f FP SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F15 0x0 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_NOP_F_IMM21 nop.f FP SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000000000000001 F15 0x0 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BREAK_X_IMM62 break.x LONG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000001000000001 X1 0x0 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_NOP_X_IMM62 nop.x LONG SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000001000000001 X1 0x0 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_MOVL_R1_IMM64 movl LONG DST;IREG_R1_127 SRC;UIMM NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000000000011000000001 X2 0x6 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 ArchRev0
|
||
|
|
EM_BRL_COND_SPTK_FEW_TARGET64 brl.cond.sptk.few LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_SPTK_MANY_TARGET64 brl.cond.sptk.many LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_SPNT_FEW_TARGET64 brl.cond.spnt.few LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_SPNT_MANY_TARGET64 brl.cond.spnt.many LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_DPTK_FEW_TARGET64 brl.cond.dptk.few LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_DPTK_MANY_TARGET64 brl.cond.dptk.many LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x0;0x2;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_DPNT_FEW_TARGET64 brl.cond.dpnt.few LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_DPNT_MANY_TARGET64 brl.cond.dpnt.many LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_SPTK_FEW_CLR_TARGET64 brl.cond.sptk.few.clr LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_SPTK_MANY_CLR_TARGET64 brl.cond.sptk.many.clr LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_SPNT_FEW_CLR_TARGET64 brl.cond.spnt.few.clr LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_SPNT_MANY_CLR_TARGET64 brl.cond.spnt.many.clr LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_DPTK_FEW_CLR_TARGET64 brl.cond.dptk.few.clr LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_DPTK_MANY_CLR_TARGET64 brl.cond.dptk.many.clr LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x1;0x2;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_DPNT_FEW_CLR_TARGET64 brl.cond.dpnt.few.clr LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_COND_DPNT_MANY_CLR_TARGET64 brl.cond.dpnt.many.clr LONG SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X3 0xC 0x1;0x3;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_CALL_SPTK_FEW_B1_TARGET64 brl.call.sptk.few LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x0;0x0;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_CALL_SPTK_MANY_B1_TARGET64 brl.call.sptk.many LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x0;0x0;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
|
|
EM_BRL_CALL_SPNT_FEW_B1_TARGET64 brl.call.spnt.few LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x0;0x1;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
|
||
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EM_BRL_CALL_SPNT_MANY_B1_TARGET64 brl.call.spnt.many LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x0;0x1;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_DPTK_FEW_B1_TARGET64 brl.call.dptk.few LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x0;0x2;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_DPTK_MANY_B1_TARGET64 brl.call.dptk.many LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x0;0x2;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_DPNT_FEW_B1_TARGET64 brl.call.dpnt.few LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x0;0x3;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_DPNT_MANY_B1_TARGET64 brl.call.dpnt.many LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x0;0x3;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_SPTK_FEW_CLR_B1_TARGET64 brl.call.sptk.few.clr LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x1;0x0;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_SPTK_MANY_CLR_B1_TARGET64 brl.call.sptk.many.clr LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x1;0x0;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_SPNT_FEW_CLR_B1_TARGET64 brl.call.spnt.few.clr LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x1;0x1;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_SPNT_MANY_CLR_B1_TARGET64 brl.call.spnt.many.clr LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x1;0x1;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_DPTK_FEW_CLR_B1_TARGET64 brl.call.dptk.few.clr LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x1;0x2;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_DPTK_MANY_CLR_B1_TARGET64 brl.call.dptk.many.clr LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x1;0x2;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_DPNT_FEW_CLR_B1_TARGET64 brl.call.dpnt.few.clr LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x1;0x3;0x0;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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EM_BRL_CALL_DPNT_MANY_CLR_B1_TARGET64 brl.call.dpnt.many.clr LONG DST;BR SRC;SSHIFT_REL NONE;NONE NONE;NONE NONE;NONE NONE;NONE 00000000000000010000001001000001 X4 0xD 0x1;0x3;0x1;0x0;0x0;0x0;0x0;0x0 Impl_Brl
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