516 lines
12 KiB
C
516 lines
12 KiB
C
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/*++
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Copyright (c) 1997 Microsoft Corporation
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Copyright (c) 1992 Intel Corporation
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All rights reserved
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INTEL CORPORATION PROPRIETARY INFORMATION
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This software is supplied to Microsoft under the terms
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of a license agreement with Intel Corporation and may not be
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copied nor disclosed except in accordance with the terms
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of that agreement.
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Module Name:
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mpprocst.c
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Abstract:
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This code has been moved from mpsproc.c so that it
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can be included from both the MPS hal and the ACPI hal.
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Author:
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Ken Reneris (kenr) 22-Jan-1991
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Environment:
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Kernel mode only.
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Revision History:
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Ron Mosgrove (Intel) - Modified to support the PC+MP
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Jake Oshins (jakeo) - moved from mpsproc.c
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--*/
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#include "halp.h"
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#include "pcmp_nt.inc"
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#include "apic.inc"
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#include "stdio.h"
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VOID
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HalpMapCR3 (
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IN ULONG VirtAddress,
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IN PHYSICAL_ADDRESS PhysicalAddress,
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IN ULONG Length
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);
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ULONG
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HalpBuildTiledCR3 (
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IN PKPROCESSOR_STATE ProcessorState
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);
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VOID
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HalpFreeTiledCR3 (
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VOID
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);
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VOID
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StartPx_PMStub (
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VOID
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);
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ULONG
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HalpBuildTiledCR3Ex (
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IN PKPROCESSOR_STATE ProcessorState,
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IN ULONG ProcNum
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);
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VOID
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HalpMapCR3Ex (
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IN ULONG VirtAddress,
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IN PHYSICAL_ADDRESS PhysicalAddress,
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IN ULONG Length,
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IN ULONG ProcNum
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);
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VOID
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HalpFreeTiledCR3Ex (
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ULONG ProcNum
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);
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#define MAX_PT 16
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PVOID HiberFreeCR3[MAX_PROCESSORS][MAX_PT]; // remember pool memory to free
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PVOID HalpLowStubPhysicalAddress; // pointer to low memory bootup stub
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PUCHAR HalpLowStub; // pointer to low memory bootup stub
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(PAGELK,HalpBuildTiledCR3)
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#pragma alloc_text(PAGELK,HalpMapCR3)
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#pragma alloc_text(PAGELK,HalpFreeTiledCR3)
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#pragma alloc_text(PAGELK,HalpBuildTiledCR3Ex)
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#pragma alloc_text(PAGELK,HalpMapCR3Ex)
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#pragma alloc_text(PAGELK,HalpFreeTiledCR3Ex)
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#endif
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#define PTES_PER_PAGE (PAGE_SIZE / HalPteSize())
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PHARDWARE_PTE
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GetPdeAddressEx(
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ULONG Va,
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ULONG ProcessorNumber
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)
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{
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PHARDWARE_PTE pageDirectories;
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PHARDWARE_PTE pageDirectoryEntry;
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ULONG pageDirectoryIndex;
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pageDirectories = (PHARDWARE_PTE)(HiberFreeCR3[ ProcessorNumber ][0]);
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if (HalPaeEnabled() != FALSE) {
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//
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// Skip over the first page, which contains the page directory pointer
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// table.
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//
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HalpAdvancePte( &pageDirectories, PTES_PER_PAGE );
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}
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pageDirectoryIndex = Va >> MiGetPdiShift();
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//
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// Note that in the case of PAE, pageDirectoryIndex includes the PDPT
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// bits. This works because we know that the four page directory tables
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// are adjacent.
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//
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pageDirectoryEntry = HalpIndexPteArray( pageDirectories,
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pageDirectoryIndex );
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return pageDirectoryEntry;
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}
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PHARDWARE_PTE
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GetPteAddress(
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IN ULONG Va,
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IN PHARDWARE_PTE PageTable
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)
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{
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PHARDWARE_PTE pointerPte;
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ULONG index;
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index = MiGetPteIndex( (PVOID)Va );
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pointerPte = HalpIndexPteArray( PageTable, index );
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return pointerPte;
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}
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ULONG
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HalpBuildTiledCR3 (
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IN PKPROCESSOR_STATE ProcessorState
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)
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/*++
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Routine Description:
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When the x86 processor is reset it starts in real-mode.
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In order to move the processor from real-mode to protected
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mode with flat addressing the segment which loads CR0 needs
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to have its linear address mapped to the physical
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location of the segment for said instruction so the
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processor can continue to execute the following instruction.
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This function is called to build such a tiled page directory.
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In addition, other flat addresses are tiled to match the
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current running flat address for the new state. Once the
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processor is in flat mode, we move to a NT tiled page which
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can then load up the remaining processor state.
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Arguments:
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ProcessorState - The state the new processor should start in.
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Return Value:
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Physical address of Tiled page directory
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--*/
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{
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return(HalpBuildTiledCR3Ex(ProcessorState,0));
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}
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ULONG
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HalpBuildTiledCR3Ex (
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IN PKPROCESSOR_STATE ProcessorState,
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IN ULONG ProcNum
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)
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/*++
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Routine Description:
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When the x86 processor is reset it starts in real-mode.
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In order to move the processor from real-mode to protected
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mode with flat addressing the segment which loads CR0 needs
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to have its linear address mapped to machine the physical
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location of the segment for said instruction so the
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processor can continue to execute the following instruction.
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This function is called to build such a tiled page directory.
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In addition, other flat addresses are tiled to match the
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current running flat address for the new state. Once the
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processor is in flat mode, we move to a NT tiled page which
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can then load up the remaining processor state.
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Arguments:
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ProcessorState - The state the new processor should start in.
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Return Value:
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Physical address of Tiled page directory
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--*/
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{
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ULONG allocationSize;
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PHARDWARE_PTE pte;
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PHARDWARE_PTE pdpt;
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PHARDWARE_PTE pdpte;
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PHARDWARE_PTE pageDirectory;
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PHYSICAL_ADDRESS physicalAddress;
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ULONG i;
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if (HalPaeEnabled() != FALSE) {
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//
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// Need 5 pages for PAE mode: one for the page directory pointer
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// table and one for each of the four page directories. Note that
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// only the single PDPT page really needs to come from memory below 4GB
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// physical.
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//
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allocationSize = PAGE_SIZE * 5;
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physicalAddress.HighPart = 0;
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physicalAddress.LowPart = 0xffffffff;
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HiberFreeCR3[ProcNum][0] =
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MmAllocateContiguousMemory (allocationSize, physicalAddress);
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} else {
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//
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// Just one page for the page directory.
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//
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allocationSize = PAGE_SIZE;
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HiberFreeCR3[ProcNum][0] =
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ExAllocatePoolWithTag (NonPagedPool, allocationSize, HAL_POOL_TAG);
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}
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if (!HiberFreeCR3[ProcNum][0]) {
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// Failed to allocate memory.
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return 0;
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}
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RtlZeroMemory (HiberFreeCR3[ProcNum][0], allocationSize);
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if (HalPaeEnabled() != FALSE) {
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//
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// Initialize each of the four page directory pointer table entries
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//
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pdpt = (PHARDWARE_PTE)HiberFreeCR3[ProcNum][0];
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pageDirectory = pdpt;
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for (i = 0; i < 4; i++) {
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//
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// Get a pointer to the page directory pointer table entry
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//
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pdpte = HalpIndexPteArray( pdpt, i );
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//
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// Skip to the first (next) page directory.
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//
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HalpAdvancePte( &pageDirectory, PTES_PER_PAGE );
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//
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// Find its physical address and update the page directory pointer
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// table entry.
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//
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physicalAddress = MmGetPhysicalAddress( pageDirectory );
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pdpte->Valid = 1;
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HalpSetPageFrameNumber( pdpte,
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physicalAddress.QuadPart >> PAGE_SHIFT );
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}
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}
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//
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// Map page for real mode stub (one page)
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//
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HalpMapCR3Ex ((ULONG) HalpLowStubPhysicalAddress,
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HalpPtrToPhysicalAddress( HalpLowStubPhysicalAddress ),
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PAGE_SIZE,
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ProcNum);
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//
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// Map page for protect mode stub (one page)
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//
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HalpMapCR3Ex ((ULONG) &StartPx_PMStub,
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HalpPtrToPhysicalAddress( NULL ),
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PAGE_SIZE,
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ProcNum);
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//
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// Map page(s) for processors GDT
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//
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HalpMapCR3Ex (ProcessorState->SpecialRegisters.Gdtr.Base,
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HalpPtrToPhysicalAddress( NULL ),
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ProcessorState->SpecialRegisters.Gdtr.Limit,
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ProcNum);
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//
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// Map page(s) for processors IDT
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//
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HalpMapCR3Ex (ProcessorState->SpecialRegisters.Idtr.Base,
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HalpPtrToPhysicalAddress( NULL ),
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ProcessorState->SpecialRegisters.Idtr.Limit,
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ProcNum);
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ASSERT (MmGetPhysicalAddress (HiberFreeCR3[ProcNum][0]).HighPart == 0);
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return MmGetPhysicalAddress (HiberFreeCR3[ProcNum][0]).LowPart;
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}
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VOID
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HalpMapCR3 (
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IN ULONG VirtAddress,
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IN PHYSICAL_ADDRESS PhysicalAddress,
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IN ULONG Length
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)
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/*++
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Routine Description:
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Called to build a page table entry for the passed page
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directory. Used to build a tiled page directory with
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real-mode & flat mode.
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Arguments:
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VirtAddress - Current virtual address
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PhysicalAddress - Optional. Physical address to be mapped
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to, if passed as a NULL then the physical
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address of the passed virtual address
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is assumed.
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Length - number of bytes to map
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Return Value:
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none.
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--*/
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{
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HalpMapCR3Ex(VirtAddress,PhysicalAddress,Length,0);
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}
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VOID
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HalpMapCR3Ex (
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IN ULONG VirtAddress,
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IN PHYSICAL_ADDRESS PhysicalAddress,
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IN ULONG Length,
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IN ULONG ProcNum
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)
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/*++
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Routine Description:
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Called to build a page table entry for the passed page
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directory. Used to build a tiled page directory with
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real-mode & flat mode.
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Arguments:
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VirtAddress - Current virtual address
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PhysicalAddress - Optional. Physical address to be mapped
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to, if passed as a NULL then the physical
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address of the passed virtual address
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is assumed.
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Length - number of bytes to map
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Return Value:
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none.
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--*/
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{
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ULONG i;
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PHARDWARE_PTE PTE;
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PVOID pPageTable;
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PHYSICAL_ADDRESS pPhysicalPage;
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while (Length) {
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PTE = GetPdeAddressEx (VirtAddress,ProcNum);
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if (HalpIsPteFree( PTE ) != FALSE) {
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pPageTable = ExAllocatePoolWithTag(NonPagedPool,
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PAGE_SIZE,
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HAL_POOL_TAG);
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if (!pPageTable) {
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//
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// This allocation is critical.
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//
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KeBugCheckEx(HAL_MEMORY_ALLOCATION,
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PAGE_SIZE,
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6,
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(ULONG)__FILE__,
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__LINE__
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);
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}
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RtlZeroMemory (pPageTable, PAGE_SIZE);
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for (i=0; i < MAX_PT; i++) {
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if (!(HiberFreeCR3[ProcNum][i])) {
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HiberFreeCR3[ProcNum][i] = pPageTable;
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break;
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}
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}
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ASSERT (i < MAX_PT);
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pPhysicalPage = MmGetPhysicalAddress (pPageTable);
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||
|
|
HalpSetPageFrameNumber( PTE, pPhysicalPage.QuadPart >> PAGE_SHIFT );
|
||
|
|
PTE->Valid = 1;
|
||
|
|
PTE->Write = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
pPhysicalPage.QuadPart =
|
||
|
|
HalpGetPageFrameNumber( PTE ) << PAGE_SHIFT;
|
||
|
|
|
||
|
|
pPageTable = MmMapIoSpace (pPhysicalPage, PAGE_SIZE, TRUE);
|
||
|
|
|
||
|
|
PTE = GetPteAddress (VirtAddress, pPageTable);
|
||
|
|
|
||
|
|
if (PhysicalAddress.QuadPart == 0) {
|
||
|
|
PhysicalAddress = MmGetPhysicalAddress((PVOID)VirtAddress);
|
||
|
|
}
|
||
|
|
|
||
|
|
HalpSetPageFrameNumber( PTE, PhysicalAddress.QuadPart >> PAGE_SHIFT );
|
||
|
|
PTE->Valid = 1;
|
||
|
|
PTE->Write = 1;
|
||
|
|
|
||
|
|
MmUnmapIoSpace (pPageTable, PAGE_SIZE);
|
||
|
|
|
||
|
|
PhysicalAddress.QuadPart = 0;
|
||
|
|
VirtAddress += PAGE_SIZE;
|
||
|
|
if (Length > PAGE_SIZE) {
|
||
|
|
Length -= PAGE_SIZE;
|
||
|
|
} else {
|
||
|
|
Length = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
VOID
|
||
|
|
HalpFreeTiledCR3 (
|
||
|
|
VOID
|
||
|
|
)
|
||
|
|
/*++
|
||
|
|
|
||
|
|
Routine Description:
|
||
|
|
Frees any memory allocated when the tiled page directory
|
||
|
|
was built.
|
||
|
|
|
||
|
|
Arguments:
|
||
|
|
none
|
||
|
|
|
||
|
|
Return Value:
|
||
|
|
none
|
||
|
|
--*/
|
||
|
|
{
|
||
|
|
HalpFreeTiledCR3Ex(0);
|
||
|
|
}
|
||
|
|
|
||
|
|
VOID
|
||
|
|
HalpFreeTiledCR3Ex (
|
||
|
|
ULONG ProcNum
|
||
|
|
)
|
||
|
|
/*++
|
||
|
|
|
||
|
|
Routine Description:
|
||
|
|
Frees any memory allocated when the tiled page directory
|
||
|
|
was built.
|
||
|
|
|
||
|
|
Arguments:
|
||
|
|
none
|
||
|
|
|
||
|
|
Return Value:
|
||
|
|
none
|
||
|
|
--*/
|
||
|
|
{
|
||
|
|
ULONG i;
|
||
|
|
|
||
|
|
for (i = 0; HiberFreeCR3[ProcNum][i]; i++) {
|
||
|
|
|
||
|
|
//
|
||
|
|
// Only the very first entry for each processor might have been
|
||
|
|
// allocated via MmAllocateContiguousMemory. So only this one can
|
||
|
|
// (and MUST) be freed via MmFreeContiguousMemory.
|
||
|
|
//
|
||
|
|
|
||
|
|
if ((i == 0) && (HalPaeEnabled() != FALSE)) {
|
||
|
|
MmFreeContiguousMemory (HiberFreeCR3[ProcNum][i]);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
ExFreePool (HiberFreeCR3[ProcNum][i]);
|
||
|
|
}
|
||
|
|
HiberFreeCR3[ProcNum][i] = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|