290 lines
5 KiB
NASM
290 lines
5 KiB
NASM
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;Copyright (c) 2000 Microsoft Corporation
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;
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;Module Name:
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;
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; amd64s.asm
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;
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;Abstract:
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;
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; Contains routines to aid in detecting and enabling Amd64 long mode.
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;
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;Author:
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;
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; Forrest Foltz (forrestf) 04-20-00
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;
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;
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;Revision History:
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;
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;--
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.586p
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.xlist
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include ks386.inc
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.list
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extrn _BlAmd64GdtDescriptor:QWORD
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extrn _BlAmd64IdtDescriptor:QWORD
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extrn _BlAmd64IdleStack64:QWORD
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extrn _BlAmd64TopLevelPte:QWORD
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extrn _BlAmd64KernelEntry:QWORD
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extrn _BlAmd64LoaderParameterBlock:QWORD
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extrn _BlAmd64_MSR_EFER:DWORD
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extrn _BlAmd64_MSR_EFER_Flags:DWORD
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extrn _BlAmd64_MSR_GS_BASE:DWORD
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extrn _BlAmd64_KGDT64_SYS_TSS:WORD
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extrn _BlAmd32GdtDescriptor:QWORD
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OP64 macro
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db 048h
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endm
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;
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; LOADREG loads the 64-bit contents of a memory location specified by
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; a 32-bit immediate address.
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;
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; The resultant 64-bit address is zero-extended, as a result this macro
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; only works with addresses < 2^32.
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;
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; This macro also assumes that esi is zero.
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;
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LDREG64 macro reg, address
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OP64
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mov reg, ds:[esi + offset address]
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endm
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_TEXT SEGMENT PARA PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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EFLAGS_ID equ 200000h
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;++
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;
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; BOOLEAN
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; BlIsAmd64Supported (
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; VOID
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; )
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;
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; Routine Description:
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;
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; This rouine determines whether the current processor supports AMD64
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; mode, a.k.a. "long mode".
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;
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; Arguments:
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;
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; None.
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;
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; Return value:
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;
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; 0 if long mode is not supported, non-zero otherwise.
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;
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;--
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public _BlIsAmd64Supported@0
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_BlIsAmd64Supported@0 proc
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;
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; First determine whether the CPUID instruction is supported. If
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; the EFLAGS_ID bit "sticks" when popped into the flags
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; register then the CPUID instruction is available.
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;
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mov ecx, EFLAGS_ID
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pushfd
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pop eax ; eax == flags
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xor ecx, eax ; ecx == flags ^ EFLAGS_ID
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push ecx
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popfd ; load new flags
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pushfd
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pop ecx ; ecx == result of flag load
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xor eax, ecx ; Q: did the EFLAGS_ID bit stick?
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jz done ; N: CPUID is not available
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;
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; We can use the CPUID instruction. Detect whether this is an
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; AMD processor and if so whether long mode is supported.
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;
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push ebx ; CPUID steps on eax, ebx, ecx, edx
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xor eax, eax ; eax = 0
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cpuid
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xor eax, eax ; Assume no long mode
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cmp ebx, 'htuA' ; Q: ebx == 'Auth' ?
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jne nolong ; N: no long mode
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;
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; We have an AMD processor, now determine whether long mode is
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; available.
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;
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mov eax, 80000001h
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xor edx, edx
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cpuid
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bt edx, 29 ; Q: Bit 29 is long mode bit, is it set?
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sbb eax, eax ; Yes (eax != 0) if carry set, else eax == 0
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nolong: pop ebx
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done: ret
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_BlIsAmd64Supported@0 endp
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;++
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;
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; VOID
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; BlAmd64SwitchToLongMode (
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; VOID
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; )
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;
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; Routine Description:
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;
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; Arguments:
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;
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; None.
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;
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; Return value:
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;
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; None.
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;
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;--
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public _BlAmd64SwitchToLongMode@0
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_BlAmd64SwitchToLongMode@0 proc
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cli
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;
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; Disable paging
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;
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mov eax, cr0
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and eax, NOT CR0_PG
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mov cr0, eax
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jmp $+2
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;
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; Enable XMM and physical address extensions (paging still off)
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;
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mov eax, cr4
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or eax, CR4_PAE OR CR4_FXSR OR CR4_XMMEXCPT
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mov cr4, eax
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;
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; Reference the four-level paging structure. This must exist
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; below 4G physical (in fact it is somewhere in the low 32MB)
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;
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mov eax, DWORD PTR [_BlAmd64TopLevelPte]
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and eax, 0FFFFF000h
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mov cr3, eax
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;
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; Set Long Mode enable and enable syscall
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;
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mov ecx, [_BlAmd64_MSR_EFER]
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rdmsr
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or eax, [_BlAmd64_MSR_EFER_Flags]
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wrmsr
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;
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; Turn paging on
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;
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mov eax, cr0
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or eax, CR0_PG
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mov cr0, eax
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jmp $+2
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;
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; Load the new global descriptor table. Note that because we're
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; not in long mode (current code selector indicates compatibility
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; mode), only a 32-bit base is loaded here.
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;
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lgdt fword ptr _BlAmd32GdtDescriptor
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;
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; Far jump to the 64-bit code segment.
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;
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db 0eah
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dd start64
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;
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; The following selector is set in amd64.c, BlAmd64BuildAmd64GDT, and
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; is included as part of the far jump instruction.
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;
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public _BlAmd64_KGDT64_R0_CODE
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_BlAmd64_KGDT64_R0_CODE:
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dw ?
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start64:
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;
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; Zero rsi so that the LDREG64 macros work
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;
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OP64
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sub esi, esi
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;
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; Running in long mode now. Execute another lgdt, this one
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; referencing the 64-bit mapping of the gdt.
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;
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; Note that an esi-relative address is used to avoid RIP-relative
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; addressing.
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;
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lgdt fword ptr ds:[esi + offset _BlAmd64GdtDescriptor]
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;
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; Load the new interrupt descriptor table
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;
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lidt fword ptr ds:[esi + offset _BlAmd64IdtDescriptor]
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;
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; Switch stacks to the 64-bit idle stack
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;
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LDREG64 esp, _BlAmd64IdleStack64
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;
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; Set the current TSS
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;
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LDREG64 eax, _BlAmd64_KGDT64_SYS_TSS
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ltr ax
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;
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; Set ss to the kernel-mode SS value (0)
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;
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sub eax, eax
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mov ss, ax
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;
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; Allocate space on the stack for a parameter target area and jump
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; to the kernel entrypoint.
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;
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OP64
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sub esp, 16
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LDREG64 ecx, _BlAmd64LoaderParameterBlock
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LDREG64 eax, _BlAmd64KernelEntry
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call eax
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_BlAmd64SwitchToLongMode@0 endp
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_TEXT ends
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