674 lines
18 KiB
C
674 lines
18 KiB
C
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/*****************************************************************************
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** **
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** COPYRIGHT (C) 2000, 2001 MKNET CORPORATION **
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** DEVELOPED FOR THE MK7100-BASED VFIR PCI CONTROLLER. **
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** **
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*****************************************************************************/
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/**********************************************************************
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Module Name:
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INTERRUP.C
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Procedures:
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MKMiniportIsr
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MKMiniportHandleInterrupt
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ProcessRXComp
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ProcessTXComp
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ProcessRXCompIsr
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ProcessTXCompIsr
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Comments:
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**********************************************************************/
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#include "precomp.h"
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#pragma hdrstop
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#include "protot.h"
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//-----------------------------------------------------------------------------
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// Procedure: [MKMiniportIsr] (miniport)
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//
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// Description: This is the interrupt service routine running at interrupt level.
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// It checks to see if there is an interrupt pending. If yes, it
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// disables board interrupts and schedules HandleInterrupt callback.
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//
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// Arguments:
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// MiniportAdapterContext - The context value returned by the Miniport
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// when the adapter was initialized (see the call
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// NdisMSetAttributes). In reality, it is a pointer to MK7_ADAPTER.
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//
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// Returns:
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// InterruptRecognized - Returns True if the interrupt belonges to this
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// adapter, and false otherwise.
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// QueueMiniportHandleInterrupt - Returns True if we want a callback to
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// HandleInterrupt.
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//
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//-----------------------------------------------------------------------------
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VOID
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MKMiniportIsr( OUT PBOOLEAN InterruptRecognized,
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OUT PBOOLEAN QueueMiniportHandleInterrupt,
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IN NDIS_HANDLE MiniportAdapterContext )
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{
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MK7REG mk7reg, ReadInt;
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PMK7_ADAPTER Adapter = PMK7_ADAPTER_FROM_CONTEXT_HANDLE(MiniportAdapterContext);
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DBGLOG("=> INT", 0);
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//****************************************
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// Read the Interrupt Event Reg and save to context area for
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// DPC processing.
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//
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// IMPORTANT NOTE: The ISR runs at DIRQL level and is, thus, higher
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// proiority than other miniport routines. We need to be careful
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// about shared resources. Example: If our multi-pkt send is running
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// when an int occurs, the send routine can be preempted. If the ISR
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// and the send routine access shared resource then we have problems.
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//
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// We save the interrupt in recentInt because the interrupt event
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// register may be cleared upon a Read. (This has been verified.)
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//****************************************
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//MK7Reg_Read(Adapter, R_INTS, &Adapter->recentInt);
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MK7Reg_Read(Adapter, R_INTS, &ReadInt);
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if (MK7OurInterrupt(ReadInt)) {
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// Int enable should happen only after DPC is done.
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// Also disabling interrupt clears Interrupt Status.
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MK7DisableInterrupt(Adapter);
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Adapter->recentInt = ReadInt;
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MK7Reg_Read(Adapter, R_CFG3, &mk7reg);
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if ((mk7reg & 0x1000) != 0){
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mk7reg &= 0xEFFF;
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MK7Reg_Write(Adapter, R_CFG3, mk7reg);
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mk7reg |= 0x1000;
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MK7Reg_Write(Adapter, R_CFG3, mk7reg);
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// mk7reg = mk7reg; //For Debugging
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}
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#if DBG
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GDbgStat.isrCnt++;
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DBGLOG(" INT status", Adapter->recentInt);
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#endif
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// Don't do TX processing in ISR. I saw a condition where SetSpeed()
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// was called while tcbused = 1. I set the change-speed flags correctly.
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// But the TX processing in ISR cleared tcbused resulting in the code
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// not chaning speed in DPC.
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// ProcessTXCompIsr(Adapter);
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ProcessRXCompIsr(Adapter);
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*InterruptRecognized = TRUE;
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*QueueMiniportHandleInterrupt = TRUE;
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}
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else {
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*InterruptRecognized = FALSE;
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*QueueMiniportHandleInterrupt = FALSE;
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}
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}
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//-----------------------------------------------------------------------------
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// Procedure: [MKMiniportHandleInterrupt]
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//
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// Description: This is the DPC for the ISR. It goes on to do RX & TX
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// completion processing.
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//
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// Arguments:
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// MiniportAdapterContext (miniport) - The context value returned by the
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// Miniport when the adapter was initialized (see the call
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// NdisMSetAttributes). In reality, it is a pointer to MK7_ADAPTER.
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//
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// Returns: (none)
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//-----------------------------------------------------------------------------
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VOID
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MKMiniportHandleInterrupt(NDIS_HANDLE MiniportAdapterContext)
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{
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MK7REG mk7reg;
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PMK7_ADAPTER Adapter = PMK7_ADAPTER_FROM_CONTEXT_HANDLE(MiniportAdapterContext);
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NdisAcquireSpinLock(&Adapter->Lock);
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DBGLOG("=> MKMiniportHandleInterrupt", Adapter->recentInt);
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//****************************************
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// DPC runs at Dispatch Level IRQL (just below ISR's DIRQL in proiority).
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// Note that recentInt can be modified in the ISR routine, which is
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// higher IRQL. But since this is DPC w/ int disabled, recentInt can
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// be safely queried.
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//****************************************
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ProcessTXComp(Adapter);
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ProcessRXComp(Adapter);
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Adapter->recentInt = 0; // clear the saved int
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NdisReleaseSpinLock(&Adapter->Lock);
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MK7EnableInterrupt(Adapter);
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}
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//-----------------------------------------------------------------------------
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// Procedure: [ProcessRXComp]
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//
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// Description: This is the DPC for RX completions.
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//
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// Arguments:
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// Adapter - ptr to Adapter object instance
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//
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// Returns: (none)
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//-----------------------------------------------------------------------------
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VOID ProcessRXComp(PMK7_ADAPTER Adapter)
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{
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UINT PacketArrayCount, i;
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// 4.0.1 BOC
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UINT PacketFreeCount;
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// 4.0.1 EOC
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PNDIS_PACKET PacketArray[MAX_ARRAY_RECEIVE_PACKETS];
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PRCB rcb;
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PRRD rrd;
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PRPD rpd;
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UINT rrdstatus;
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BOOLEAN done=FALSE;
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BOOLEAN gotdata=FALSE;
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MK7REG intereg;
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UINT rcvcnt;
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// 4.0.1 BOC
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BOOLEAN LowResource;
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// 4.0.1 EOC
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// Process only if we get the corresponding int.
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if (!(Adapter->recentInt & B_RX_INTS)) {
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return;
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}
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DBGLOG("=> RX comp", 0);
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#if DBG
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GDbgStat.rxIsrCnt++;
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#endif
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// 1.0.0
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// If we have just started receiving a packet, indicate media-busy
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// to the protocol.
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// if (Adapter->mediaBusy && !Adapter->haveIndicatedMediaBusy) {
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// if (Adapter->CurrentSpeed > MAX_SIR_SPEED) {
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//#if DBG
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// DBGLOG("Error: MKMiniportHandleInterrupt is in wrong state",
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// Adapter->CurrentSpeed);
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//#endif
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// ASSERT(0);
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// }
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// NdisMIndicateStatus(Adapter->MK7AdapterHandle,
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// NDIS_STATUS_MEDIA_BUSY, NULL, 0);
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// NdisMIndicateStatusComplete(Adapter->MK7AdapterHandle);
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// RYM-5+
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// May need to protect this because ISR also writes to this?
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// Adapter->haveIndicatedMediaBusy = TRUE;
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// }
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rcb = Adapter->pRcbArray[Adapter->nextRxRcbIdx];
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rrd = rcb->rrd;
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rrdstatus = rrd->status; // for debug
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do {
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PacketArrayCount = 0;
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// 4.0.1 BOC
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LowResource = FALSE;
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// 4.0.1 EOC.
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// 4.0.1 BOC
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PacketFreeCount = 0;
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// 4.0.1 EOC.
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// inner loop
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while ( !HwOwnsRrd(rrd) &&
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(PacketArrayCount < MAX_ARRAY_RECEIVE_PACKETS) ) {
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// 4.0.1 BOC
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if (QueueEmpty(&Adapter->FreeRpdList))
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{
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break;
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}
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// 4.0.1 EOC.
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#if DBG
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// DBG_STAT
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if (RrdAnyError(rrd)) {
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GDbgStat.rxErrCnt++;
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GDbgStat.rxErr |= rrd->status;
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DBGSTATUS1(" RX err: %x \n\r", rrd->status);
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}
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if (Adapter->recentInt & B_RX_INTS)
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GDbgStat.rxComp++;
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else
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GDbgStat.rxCompNoInt++;
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#endif
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if (RrdError(rrd)) {
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// If error just give RRD back to hw and continue.
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// (NOTE: This may indicate errors for MIR & FIR only.
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// The sw does the FCS for SIR.)
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// (Note that hw may not detect all SIR errors.)
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rrd->count = 0;
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GrantRrdToHw(rrd);
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// Next receive to read from
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Adapter->nextRxRcbIdx++;
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Adapter->nextRxRcbIdx %= Adapter->NumRcb;
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rcb = Adapter->pRcbArray[Adapter->nextRxRcbIdx];
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rrd = rcb->rrd;
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rrdstatus = rrd->status; // for debug
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// break; // this to do 1 rx per int
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DBGLOG(" RX err", 0);
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continue; // this to do > 1 rx per int
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}
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// Additional software processing for SIR frames
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if (Adapter->CurrentSpeed <= MAX_SIR_SPEED) {
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if (!ProcRXSir(rcb->rpd->databuff, (UINT)rrd->count)) {
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// If error just give RRD back to hw and continue.
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rrd->count = 0;
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GrantRrdToHw(rrd);
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// Next receive to read from
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Adapter->nextRxRcbIdx++;
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Adapter->nextRxRcbIdx %= Adapter->NumRcb;
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rcb = Adapter->pRcbArray[Adapter->nextRxRcbIdx];
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rrd = rcb->rrd;
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rrdstatus = rrd->status; // for debug
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#if DBG
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GDbgStat.rxErrCnt++;
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GDbgStat.rxErrSirCrc++;
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#endif
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// break; // this to do 1 rx per int
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DBGLOG(" RX err", 0);
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continue; // this to do > 1 rx per int
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}
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}
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// Remove count of FCS bytes:
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// SIR/MIR = 2 (16 bits)
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// FIR/VFIR = 4 (32 bits)
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if (Adapter->CurrentSpeed < MIN_FIR_SPEED) {
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rcvcnt = (UINT) rrd->count - SIR_FCS_SIZE;
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DBGLOG(" RX comp (slow)", 0);
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}
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else {
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rcvcnt = (UINT) rrd->count - FASTIR_FCS_SIZE;
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DBGLOG(" RX comp (fast)", 0);
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}
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NdisAdjustBufferLength(rcb->rpd->ReceiveBuffer, rcvcnt);
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#if DBG
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if (rcvcnt > GDbgStat.rxLargestPkt) {
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GDbgStat.rxLargestPkt = rcvcnt;
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}
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// NdisGetCurrentSystemTime((PLARGE_INTEGER)&GDbgTARspTime[GDbgTATimeIdx]);
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// GDbgTATime[GDbgTATimeIdx] = GDbgTARspTime[GDbgTATimeIdx] -
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// GDbgTACmdTime[GDbgTATimeIdx];
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// GDbgTATimeIdx++;
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// GDbgTATimeIdx %= 1000; // wrap around
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#endif
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PacketArray[PacketArrayCount] = rcb->rpd->ReceivePacket;
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// 4.0.1 BOC
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if (((Adapter->NumRpd - Adapter->UsedRpdCount-Adapter->NumRcb) <= 4)|| LowResource==TRUE) {
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NDIS_SET_PACKET_STATUS(PacketArray[PacketArrayCount], NDIS_STATUS_RESOURCES);
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LowResource = TRUE;
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PacketFreeCount++;
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}
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else {
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// NDIS_SET_PACKET_STATUS(PacketArray[PacketArrayCount], NDIS_STATUS_SUCCESS);
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NDIS_SET_PACKET_STATUS(PacketArray[PacketArrayCount], NDIS_STATUS_SUCCESS);
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}
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// 4.0.1 EOC
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PacketArrayCount++;
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// 4.0.1 BOC
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Adapter->UsedRpdCount++;
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// 4.0.1 EOC
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// unbind the one we just indicated to upper layer
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rcb->rpd = (PRPD)NULL;
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rcb->rrd->addr = 0;
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// get a new one for the next rx
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rpd = (PRPD) QueuePopHead(&Adapter->FreeRpdList);
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// 4.0.1 BOC
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ASSERT(!(rpd == (PRPD)NULL));
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// if (rpd == (PRPD)NULL) {
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//****************************************
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// If there's no existing RCB that's waiting for a
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// RPD, set the start of waiting RCBs to this one.
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//****************************************
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// if (Adapter->rcbPendRpdCnt == 0) {
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// Adapter->rcbPendRpdIdx = Adapter->nextRxRcbIdx;
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// }
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// Adapter->rcbPendRpdCnt++;
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//
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//#if DBG
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// GDbgStat.rxNoRpd++;
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//#endif
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// }
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// else {
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// 4.0.1 EOC
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// bind new RDP-Packet to RCB-RRD
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rcb->rpd = rpd;
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|
|
rcb->rrd->addr = rpd->databuffphys;
|
||
|
|
rcb->rrd->count = 0;
|
||
|
|
GrantRrdToHw(rcb->rrd);
|
||
|
|
// 4.0.1 BOC
|
||
|
|
// }
|
||
|
|
// 4.0.1 EOC.
|
||
|
|
|
||
|
|
// Next receive to read from
|
||
|
|
Adapter->nextRxRcbIdx++;
|
||
|
|
Adapter->nextRxRcbIdx %= Adapter->NumRcb;
|
||
|
|
|
||
|
|
|
||
|
|
rcb = Adapter->pRcbArray[Adapter->nextRxRcbIdx];
|
||
|
|
rrd = rcb->rrd;
|
||
|
|
rrdstatus = rrd->status; // for debug
|
||
|
|
|
||
|
|
} // while
|
||
|
|
|
||
|
|
|
||
|
|
if (PacketArrayCount >= MAX_ARRAY_RECEIVE_PACKETS) {
|
||
|
|
DBGLOG(" RX max indicate", 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
//****************************************
|
||
|
|
// RYM-5+
|
||
|
|
// NOTE: This controls whether we poll the next ring buffers
|
||
|
|
// for data after serviceing the current ring buffer that
|
||
|
|
// caused the original RX int. The current int scheme
|
||
|
|
// is to get 1 rx buffer per int. So the following lines
|
||
|
|
// are replaced with a 1 rx per int logic.
|
||
|
|
// **We're done when we run into the 1st Ring entry that
|
||
|
|
// **we have no ownership.
|
||
|
|
//****************************************
|
||
|
|
if (HwOwnsRrd(rrd))
|
||
|
|
done = TRUE;
|
||
|
|
// done = TRUE;
|
||
|
|
|
||
|
|
// Indicate away
|
||
|
|
if(PacketArrayCount) {
|
||
|
|
NdisReleaseSpinLock(&Adapter->Lock);
|
||
|
|
NdisMIndicateReceivePacket(Adapter->MK7AdapterHandle,
|
||
|
|
PacketArray,
|
||
|
|
PacketArrayCount);
|
||
|
|
#if DBG
|
||
|
|
GDbgStat.rxPktsInd += PacketArrayCount;
|
||
|
|
#endif
|
||
|
|
gotdata = TRUE;
|
||
|
|
|
||
|
|
NdisAcquireSpinLock(&Adapter->Lock);
|
||
|
|
//DBGLOG(" ProcessRXInterrupt: indicated Packet(s)", PacketArrayCount);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
//****************************************
|
||
|
|
// Check Packet status on return from Indicate. Pending means
|
||
|
|
// NDIS-upper layer still holds it, else it's ours.
|
||
|
|
//****************************************
|
||
|
|
// Don't do this for deserialized driver.
|
||
|
|
// for (i=0; i<PacketArrayCount; i++ ) {
|
||
|
|
// NDIS_STATUS ReturnStatus;
|
||
|
|
//
|
||
|
|
// ReturnStatus = NDIS_GET_PACKET_STATUS(PacketArray[i]);
|
||
|
|
//
|
||
|
|
// recover the RPD
|
||
|
|
// rpd = *(PRPD *)(PacketArray[i]->MiniportReserved);
|
||
|
|
//
|
||
|
|
// if (ReturnStatus != NDIS_STATUS_PENDING) {
|
||
|
|
// ProcReturnedRpd(Adapter, rpd);
|
||
|
|
// }
|
||
|
|
// }
|
||
|
|
// 4.0.1 BOC
|
||
|
|
for (i=PacketArrayCount-PacketFreeCount; i<PacketArrayCount; i++){
|
||
|
|
rpd = *(PRPD *)(PacketArray[i]->MiniportReserved);
|
||
|
|
ProcReturnedRpd(Adapter, rpd);
|
||
|
|
Adapter->UsedRpdCount--;
|
||
|
|
}
|
||
|
|
// 4.0.1 EOC.
|
||
|
|
|
||
|
|
} while (!done);
|
||
|
|
|
||
|
|
Adapter->nowReceiving = FALSE;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
//-----------------------------------------------------------------------------
|
||
|
|
// Procedure: [ProcessTXComp]
|
||
|
|
//
|
||
|
|
// Description: TX complete processing in DPC. This is very similar to
|
||
|
|
// ProcessTXCompIsr(), the main difference being we also process the TX
|
||
|
|
// queue here and perform TXs as necessary.
|
||
|
|
//
|
||
|
|
// Arguements: Adapter.
|
||
|
|
//
|
||
|
|
// Result: (none)
|
||
|
|
//-----------------------------------------------------------------------------
|
||
|
|
VOID ProcessTXComp(PMK7_ADAPTER Adapter)
|
||
|
|
{
|
||
|
|
PTCB tcb;
|
||
|
|
MK7REG mk7reg;
|
||
|
|
NDIS_STATUS SendStatus;
|
||
|
|
PNDIS_PACKET QueuePacket;
|
||
|
|
|
||
|
|
|
||
|
|
// Process only if we get the corresponding int.
|
||
|
|
if (!(Adapter->recentInt & B_TX_INTS)) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
DBGLOG("=> TX comp", 0);
|
||
|
|
|
||
|
|
|
||
|
|
#if DBG
|
||
|
|
GDbgStat.txIsrCnt++;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// Debug
|
||
|
|
if (Adapter->CurrentSpeed > MAX_SIR_SPEED) {
|
||
|
|
DBGLOG(" TX comp (fast)", 0);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
DBGLOG(" TX comp (slow)", 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// Simplified change speed
|
||
|
|
if (Adapter->changeSpeedPending == CHANGESPEED_ON_DONE) {
|
||
|
|
// Note: We're changing speed in TX mode.
|
||
|
|
MK7ChangeSpeedNow(Adapter);
|
||
|
|
Adapter->changeSpeedPending = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
while (Adapter->tcbUsed > 0) {
|
||
|
|
tcb = Adapter->pTcbArray[Adapter->nextReturnTcbIdx];
|
||
|
|
|
||
|
|
if ( !HwOwnsTrd(tcb->trd) ) {
|
||
|
|
#if DBG
|
||
|
|
if (TrdAnyError(tcb->trd)) {
|
||
|
|
GDbgStat.txErrCnt++;
|
||
|
|
GDbgStat.txErr |= tcb->trd->status;
|
||
|
|
DBGSTATUS1(" TX err: %x \n\r", tcb->trd->status);
|
||
|
|
}
|
||
|
|
if (Adapter->recentInt & B_TX_INTS)
|
||
|
|
GDbgStat.txComp++;
|
||
|
|
else
|
||
|
|
GDbgStat.txCompNoInt++;
|
||
|
|
#endif
|
||
|
|
tcb->trd->count = 0;
|
||
|
|
|
||
|
|
|
||
|
|
// For each completing TX there's a corresponding q'd pkt.
|
||
|
|
// We release it here.
|
||
|
|
QueuePacket = Adapter->FirstTxQueue;
|
||
|
|
DequeuePacket(Adapter->FirstTxQueue, Adapter->LastTxQueue);
|
||
|
|
Adapter->NumPacketsQueued--;
|
||
|
|
NDIS_SET_PACKET_STATUS(QueuePacket, NDIS_STATUS_SUCCESS);
|
||
|
|
NdisMSendComplete( Adapter->MK7AdapterHandle,
|
||
|
|
QueuePacket,
|
||
|
|
NDIS_STATUS_SUCCESS);
|
||
|
|
Adapter->HangCheck = 0; // 1.0.0
|
||
|
|
Adapter->nextReturnTcbIdx++;
|
||
|
|
Adapter->nextReturnTcbIdx %= Adapter->NumTcb;
|
||
|
|
Adapter->tcbUsed--;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
DBGLOG(" Not our TCB; but tcbUsed>0", 0);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// No resource even if we have more to send. Return now & let subsequent
|
||
|
|
// TX completes keep the ball rolling.
|
||
|
|
if (Adapter->tcbUsed >= Adapter->NumTcb) {
|
||
|
|
// NdisReleaseSpinLock(&Adapter->Lock);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// If no TXs queued and all TXs are done, then switch to RX mode.
|
||
|
|
if ( (!Adapter->FirstTxQueue) && (Adapter->tcbUsed == 0) ) {
|
||
|
|
MK7SwitchToRXMode(Adapter);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// Send the q'd pkts until all done or until all TX ring buffers are used up.
|
||
|
|
//while(Adapter->FirstTxQueue) {
|
||
|
|
if (Adapter->FirstTxQueue) {
|
||
|
|
|
||
|
|
#if DBG
|
||
|
|
GDbgStat.txProcQ++;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
DBGLOG(" Proc Q", 0);
|
||
|
|
|
||
|
|
QueuePacket = Adapter->FirstTxQueue;
|
||
|
|
SendStatus = SendPkt(Adapter, QueuePacket);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
//-----------------------------------------------------------------------------
|
||
|
|
// Procedure: [ProcessRXCompIsr]
|
||
|
|
//
|
||
|
|
// Description: Some RX complete processing in ISR.
|
||
|
|
//
|
||
|
|
// Arguements: Adapter.
|
||
|
|
//
|
||
|
|
// Result: (none)
|
||
|
|
//-----------------------------------------------------------------------------
|
||
|
|
VOID ProcessRXCompIsr(PMK7_ADAPTER Adapter)
|
||
|
|
{
|
||
|
|
|
||
|
|
// 4.1.0 Back for HW_VER_1 support
|
||
|
|
if (Adapter->recentInt & B_RX_INTS) {
|
||
|
|
Adapter->nowReceiving=TRUE;
|
||
|
|
// if (!Adapter->mediaBusy) {
|
||
|
|
// mediaBusy: IrLAP clears mediaBusy (via OID) to indicate
|
||
|
|
// it wants to be notified when media becomes busy. Here
|
||
|
|
// we detect it is cleared. We then set it and clear
|
||
|
|
// haveIndicatedMediaBusy so we do notify later in DPC.
|
||
|
|
// Adapter->mediaBusy = TRUE;
|
||
|
|
// Adapter->haveIndicatedMediaBusy = FALSE;
|
||
|
|
// Adapter->nowReceiving = TRUE;
|
||
|
|
// }
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
//-----------------------------------------------------------------------------
|
||
|
|
// Procedure: [ProcessTXCompIsr]
|
||
|
|
//
|
||
|
|
// Description: TX complete processing in ISR. This is very similar to
|
||
|
|
// ProcessTXComp() except we don't start any TX's here.
|
||
|
|
//
|
||
|
|
// Arguements: Adapter.
|
||
|
|
//
|
||
|
|
// Result: (none)
|
||
|
|
//-----------------------------------------------------------------------------
|
||
|
|
VOID ProcessTXCompIsr(PMK7_ADAPTER Adapter)
|
||
|
|
{
|
||
|
|
PTCB tcb;
|
||
|
|
MK7REG mk7reg;
|
||
|
|
|
||
|
|
//******************************
|
||
|
|
// Whether or not there was a TX-completion interrupt, we do some
|
||
|
|
// processing here in case ever the driver or hw missed an
|
||
|
|
// interrupt previously.
|
||
|
|
//
|
||
|
|
// We loop until all tcb's are returned (tcbUsed == 0) or we run into
|
||
|
|
// a TX ring buff that the hw still owns (HwOwnsTrd()). When we leave
|
||
|
|
// here, we should have processed all current TX completions based on
|
||
|
|
// the TX ownership bit. We switch to RX mode ONLY after all TX are
|
||
|
|
// completed (either here in the ISR or in DPC).
|
||
|
|
//******************************
|
||
|
|
|
||
|
|
|
||
|
|
while (Adapter->tcbUsed > 0) {
|
||
|
|
tcb = Adapter->pTcbArray[Adapter->nextReturnTcbIdx];
|
||
|
|
|
||
|
|
if ( !HwOwnsTrd(tcb->trd) ) {
|
||
|
|
#if DBG
|
||
|
|
if (TrdAnyError(tcb->trd)) {
|
||
|
|
GDbgStat.txErrCnt++;
|
||
|
|
GDbgStat.txErr |= tcb->trd->status;
|
||
|
|
DBGSTATUS1(" TX err: %x \n\r", tcb->trd->status);
|
||
|
|
}
|
||
|
|
if (Adapter->recentInt & B_TX_INTS)
|
||
|
|
GDbgStat.txComp++;
|
||
|
|
else
|
||
|
|
GDbgStat.txCompNoInt++;
|
||
|
|
#endif
|
||
|
|
tcb->trd->count = 0;
|
||
|
|
Adapter->nextReturnTcbIdx++;
|
||
|
|
Adapter->nextReturnTcbIdx %= Adapter->NumTcb;
|
||
|
|
Adapter->tcbUsed--;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|