207 lines
8.1 KiB
C
207 lines
8.1 KiB
C
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/*****************************************************************************
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** **
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** COPYRIGHT (C) 2000, 2001 MKNET CORPORATION **
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** DEVELOPED FOR THE MK7100-BASED VFIR PCI CONTROLLER. **
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** **
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*****************************************************************************/
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/**********************************************************************
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Module Name:
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WINPCI.H
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Comments:
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PCI & Windows PCI defs.
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**********************************************************************/
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#ifndef _WINPCI_H
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#define _WINPCI_H
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//-------------------------------------------------------------------------
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// PCI configuration hardware ports
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//-------------------------------------------------------------------------
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#define CF1_CONFIG_ADDR_REGISTER 0x0CF8
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#define CF1_CONFIG_DATA_REGISTER 0x0CFC
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#define CF2_SPACE_ENABLE_REGISTER 0x0CF8
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#define CF2_FORWARD_REGISTER 0x0CFA
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#define CF2_BASE_ADDRESS 0xC000
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//-------------------------------------------------------------------------
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// Configuration Space Header
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//-------------------------------------------------------------------------
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typedef struct _PCI_CONFIG_STRUC {
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USHORT PciVendorId; // PCI Vendor ID
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USHORT PciDeviceId; // PCI Device ID
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USHORT PciCommand;
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USHORT PciStatus;
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UCHAR PciRevisionId;
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UCHAR PciClassCode[3];
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UCHAR PciCacheLineSize;
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UCHAR PciLatencyTimer;
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UCHAR PciHeaderType;
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UCHAR PciBIST;
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ULONG PciBaseReg0;
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ULONG PciBaseReg1;
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ULONG PciBaseReg2;
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ULONG PciBaseReg3;
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ULONG PciBaseReg4;
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ULONG PciBaseReg5;
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ULONG PciReserved0;
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ULONG PciReserved1;
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ULONG PciExpROMAddress;
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ULONG PciReserved2;
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ULONG PciReserved3;
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UCHAR PciInterruptLine;
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UCHAR PciInterruptPin;
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UCHAR PciMinGnt;
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UCHAR PciMaxLat;
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} PCI_CONFIG_STRUC, *PPCI_CONFIG_STRUC;
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//----------------------------------------------------------------------
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// PCI Config Space
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//----------------------------------------------------------------------
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#define PCI_VENDOR_ID_REGISTER 0x00 // PCI Vendor ID Register
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#define PCI_DEVICE_ID_REGISTER 0x02 // PCI Device ID Register
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#define PCI_CONFIG_ID_REGISTER 0x00 // PCI Configuration ID Register
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#define PCI_COMMAND_REGISTER 0x04 // PCI Command Register
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#define PCI_STATUS_REGISTER 0x06 // PCI Status Register
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#define PCI_REV_ID_REGISTER 0x08 // PCI Revision ID Register
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#define PCI_CLASS_CODE_REGISTER 0x09 // PCI Class Code Register
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#define PCI_CACHE_LINE_REGISTER 0x0C // PCI Cache Line Register
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#define PCI_LATENCY_TIMER 0x0D // PCI Latency Timer Register
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#define PCI_HEADER_TYPE 0x0E // PCI Header Type Register
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#define PCI_BIST_REGISTER 0x0F // PCI Built-In SelfTest Register
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#define PCI_BAR_0_REGISTER 0x10 // PCI Base Address Register 0
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#define PCI_BAR_1_REGISTER 0x14 // PCI Base Address Register 1
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#define PCI_BAR_2_REGISTER 0x18 // PCI Base Address Register 2
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#define PCI_BAR_3_REGISTER 0x1C // PCI Base Address Register 3
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#define PCI_BAR_4_REGISTER 0x20 // PCI Base Address Register 4
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#define PCI_BAR_5_REGISTER 0x24 // PCI Base Address Register 5
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#define PCI_SUBVENDOR_ID_REGISTER 0x2C // PCI SubVendor ID Register
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#define PCI_SUBDEVICE_ID_REGISTER 0x2E // PCI SubDevice ID Register
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#define PCI_EXPANSION_ROM 0x30 // PCI Expansion ROM Base Register
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#define PCI_INTERRUPT_LINE 0x3C // PCI Interrupt Line Register
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#define PCI_INTERRUPT_PIN 0x3D // PCI Interrupt Pin Register
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#define PCI_MIN_GNT_REGISTER 0x3E // PCI Min-Gnt Register
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#define PCI_MAX_LAT_REGISTER 0x3F // PCI Max_Lat Register
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#define PCI_NODE_ADDR_REGISTER 0x40 // PCI Node Address Register
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//-------------------------------------------------------------------------
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// PCI Class Code Definitions
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// Configuration Space Header
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//-------------------------------------------------------------------------
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#define PCI_BASE_CLASS 0x02 // Base Class - Network Controller
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#define PCI_SUB_CLASS 0x00 // Sub Class - Ethernet Controller
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#define PCI_PROG_INTERFACE 0x00 // Prog I/F - Ethernet COntroller
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//-------------------------------------------------------------------------
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// The following is copied from EQUATES.H
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// Bit Mask definitions
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//-------------------------------------------------------------------------
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#define BIT_0 0x0001
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#define BIT_1 0x0002
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#define BIT_2 0x0004
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#define BIT_3 0x0008
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#define BIT_4 0x0010
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#define BIT_5 0x0020
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#define BIT_6 0x0040
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#define BIT_7 0x0080
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#define BIT_8 0x0100
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#define BIT_9 0x0200
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#define BIT_10 0x0400
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#define BIT_11 0x0800
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#define BIT_12 0x1000
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#define BIT_13 0x2000
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#define BIT_14 0x4000
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#define BIT_15 0x8000
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#define BIT_24 0x01000000
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#define BIT_28 0x10000000
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//-------------------------------------------------------------------------
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// PCI Command Register Bit Definitions
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// Configuration Space Header
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//-------------------------------------------------------------------------
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#define CMD_IO_SPACE BIT_0
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#define CMD_MEMORY_SPACE BIT_1
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#define CMD_BUS_MASTER BIT_2
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#define CMD_SPECIAL_CYCLES BIT_3
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#define CMD_MEM_WRT_INVALIDATE BIT_4
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#define CMD_VGA_PALLETTE_SNOOP BIT_5
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#define CMD_PARITY_RESPONSE BIT_6
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#define CMD_WAIT_CYCLE_CONTROL BIT_7
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#define CMD_SERR_ENABLE BIT_8
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#define CMD_BACK_TO_BACK BIT_9
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//-------------------------------------------------------------------------
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// PCI Status Register Bit Definitions
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// Configuration Space Header
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//-------------------------------------------------------------------------
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#define STAT_BACK_TO_BACK BIT_7
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#define STAT_DATA_PARITY BIT_8
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#define STAT_DEVSEL_TIMING BIT_9 OR BIT_10
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#define STAT_SIGNAL_TARGET_ABORT BIT_11
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#define STAT_RCV_TARGET_ABORT BIT_12
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#define STAT_RCV_MASTER_ABORT BIT_13
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#define STAT_SIGNAL_MASTER_ABORT BIT_14
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#define STAT_DETECT_PARITY_ERROR BIT_15
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//-------------------------------------------------------------------------
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// PCI Base Address Register For Memory (BARM) Bit Definitions
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// Configuration Space Header
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//-------------------------------------------------------------------------
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#define BARM_LOCATE_BELOW_1_MEG BIT_1
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#define BARM_LOCATE_IN_64_SPACE BIT_2
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#define BARM_PREFETCHABLE BIT_3
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//-------------------------------------------------------------------------
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// PCI Base Address Register For I/O (BARIO) Bit Definitions
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// Configuration Space Header
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//-------------------------------------------------------------------------
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#define BARIO_SPACE_INDICATOR BIT_0
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//-------------------------------------------------------------------------
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// PCI BIOS Definitions
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// Refer To The PCI BIOS Specification
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//-------------------------------------------------------------------------
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//- Function Code List
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#define PCI_FUNCTION_ID 0xB1 // AH Register
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#define PCI_BIOS_PRESENT 0x01 // AL Register
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#define FIND_PCI_DEVICE 0x02 // AL Register
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#define FIND_PCI_CLASS_CODE 0x03 // AL Register
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#define GENERATE_SPECIAL_CYCLE 0x06 // AL Register
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#define READ_CONFIG_BYTE 0x08 // AL Register
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#define READ_CONFIG_WORD 0x09 // AL Register
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#define READ_CONFIG_DWORD 0x0A // AL Register
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#define WRITE_CONFIG_BYTE 0x0B // AL Register
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#define WRITE_CONFIG_WORD 0x0C // AL Register
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#define WRITE_CONFIG_DWORD 0x0D // AL Register
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//- Function Return Code List
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#define SUCCESSFUL 0x00
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#define FUNC_NOT_SUPPORTED 0x81
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#define BAD_VENDOR_ID 0x83
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#define DEVICE_NOT_FOUND 0x86
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#define BAD_REGISTER_NUMBER 0x87
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//- PCI BIOS Calls
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#define PCI_BIOS_INTERRUPT 0x1A // PCI BIOS Int 1Ah Function Call
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#define PCI_PRESENT_CODE 0x20494350 // Hex Equivalent Of 'PCI '
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#define PCI_SERVICE_IDENTIFIER 0x49435024 // ASCII Codes for 'ICP$'
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//- Device and Vendor IDs
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#define MK7_PCI_DEVICE_ID 0x7100
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#define MKNET_PCI_VENDOR_ID 0x1641
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// For debugging
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#define DBG_DEVICE_ID 0x7100
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#define DBG_VENDOR_ID 0x2828
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#endif // _WINPCI_H
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