283 lines
6.2 KiB
C
283 lines
6.2 KiB
C
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//
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// Module: DDC50.C
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// Date: Jun 29, 1997
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//
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// Copyright (c) 1997 by ATI Technologies Inc.
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//
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/********************** PolyTron RCS Utilities
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$Revision: 1.1 $
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$Date: 30 Jun 1997 11:36:28 $
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$Author: MACIESOW $
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$Log: V:\source\wnt\ms11\miniport\archive\ddc50.c_v $
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*
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* Rev 1.1 30 Jun 1997 11:36:28 MACIESOW
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* Initial revision.
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End of PolyTron RCS section *****************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <errno.h>
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#include <math.h>
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#include "dderror.h"
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#include "miniport.h"
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#include "ntddvdeo.h"
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#include "video.h" /* for VP_STATUS definition */
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#include "stdtyp.h"
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#include "amachcx.h"
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#include "amach1.h"
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#include "atimp.h"
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#include "atint.h"
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#include "cvtvdif.h"
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#include "cvtvga.h"
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#include "dynainit.h"
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#include "dynatime.h"
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#include "services.h"
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#include "vdptocrt.h"
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#define INCLUDE_CVTDDC
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#include "cvtddc.h"
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#if (TARGET_BUILD >= 500)
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VOID WriteClockLineDAC(PHW_DEVICE_EXTENSION phwDeviceExtension, UCHAR ucData);
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VOID WriteDataLineDAC(PHW_DEVICE_EXTENSION phwDeviceExtension, UCHAR ucData);
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BOOLEAN ReadClockLineDAC(PHW_DEVICE_EXTENSION phwDeviceExtension);
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BOOLEAN ReadDataLineDAC(PHW_DEVICE_EXTENSION phwDeviceExtension);
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VOID WaitForVsyncActiveDAC(PHW_DEVICE_EXTENSION HwDeviceExtension);
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VOID WriteClockLineGP(PHW_DEVICE_EXTENSION phwDeviceExtension, UCHAR ucData);
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VOID WriteDataLineGP(PHW_DEVICE_EXTENSION phwDeviceExtension, UCHAR ucData);
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BOOLEAN ReadClockLineGP(PHW_DEVICE_EXTENSION phwDeviceExtension);
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BOOLEAN ReadDataLineGP(PHW_DEVICE_EXTENSION phwDeviceExtension);
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VOID WaitForVsyncActiveGP(PHW_DEVICE_EXTENSION HwDeviceExtension);
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/****************************************************************
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; DDC register
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;
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; High Byte, High Word
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;
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; ... 5 4 3 2 1 0 SCW = CLK Write
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; --------|---|---|---|---|---|---| SDW = DATA Write
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; ...|SCW|SDW| |SCR|SDR| | SCR = CLK Read
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; --------------------------------- SDR = DATA Read
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;
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;****************************************************************/
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VOID WriteClockLineDAC(PHW_DEVICE_EXTENSION phwDeviceExtension, UCHAR ucData)
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{
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UCHAR Scratch;
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//
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// Value is inverted.
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//
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ucData = (ucData + 1) & 0x01;
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//
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// Write to the SCL line.
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//
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Scratch = (INP_HBHW(DAC_CNTL) & 0xE8) | (ucData << 5);
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OUTP_HBHW(DAC_CNTL, Scratch);
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}
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VOID WriteDataLineDAC(PHW_DEVICE_EXTENSION phwDeviceExtension, UCHAR ucData)
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{
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UCHAR Scratch;
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//
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// Value is inverted.
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//
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ucData = (ucData + 1) & 0x01;
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//
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// Write to the SDA line.
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//
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Scratch = (INP_HBHW(DAC_CNTL) & 0xD8) | (ucData << 4);
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OUTP_HBHW(DAC_CNTL, Scratch);
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}
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BOOLEAN ReadClockLineDAC(PHW_DEVICE_EXTENSION phwDeviceExtension)
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{
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return ((INP_HBHW(DAC_CNTL) & 0x04) >> 2);
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}
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BOOLEAN ReadDataLineDAC(PHW_DEVICE_EXTENSION phwDeviceExtension)
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{
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return ((INP_HBHW(DAC_CNTL) & 0x02) >> 1);
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}
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VOID WaitForVsyncActiveDAC(PHW_DEVICE_EXTENSION HwDeviceExtension)
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{
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//
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// BUGBUG
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//
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delay(30);
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}
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/****************************************************************
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; DDC register
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;
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; High Byte, Low Word
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;
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; ... 5 4 3 2 1 0
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; --------|---|---|---|---|---|---|
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; ...|SCR|SDR| | | | | SCR = CLK Read
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; --------------------------------- SDR = DATA Read
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;
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; High Byte, High Word
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;
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; ... 5 4 3 2 1 0 SCW = CLK Write
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; --------|---|---|---|---|---|---| SDW = DATA Write
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; ...|SCW|SDW| | | | |
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; ---------------------------------
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;
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;****************************************************************/
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VOID WriteClockLineGP(PHW_DEVICE_EXTENSION phwDeviceExtension, UCHAR ucData)
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{
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UCHAR Scratch;
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//
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// Value is inverted.
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//
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ucData = (ucData + 1) & 0x01;
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//
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// Write to the SCL line.
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//
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Scratch = (INP_HBHW(GP_IO) & 0xDF) | (ucData << 5);
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OUTP_HBHW(GP_IO, Scratch);
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}
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VOID WriteDataLineGP(PHW_DEVICE_EXTENSION phwDeviceExtension, UCHAR ucData)
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{
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UCHAR Scratch;
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//
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// Value is inverted.
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//
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ucData = (ucData + 1) & 0x01;
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//
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// Write to the SDA line.
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//
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Scratch = (INP_HBHW(GP_IO) & 0xEF) | (ucData << 4);
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OUTP_HBHW(GP_IO, Scratch);
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}
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BOOLEAN ReadClockLineGP(PHW_DEVICE_EXTENSION phwDeviceExtension)
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{
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return ((INP_HBLW(GP_IO) & 0x20) >> 5);
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}
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BOOLEAN ReadDataLineGP(PHW_DEVICE_EXTENSION phwDeviceExtension)
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{
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return ((INP_HBLW(GP_IO) & 0x10) >> 4);
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}
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VOID WaitForVsyncActiveGP(PHW_DEVICE_EXTENSION HwDeviceExtension)
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{
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//
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// BUGBUG
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//
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delay(30);
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}
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BOOLEAN
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DDC2Query50(
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PHW_DEVICE_EXTENSION phwDeviceExtension,
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PUCHAR QueryBuffer,
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ULONG BufferSize)
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//
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// DESCRIPTION:
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// Reads the basic EDID structure from the monitor using DDC2.
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//
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// PARAMETERS:
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// phwDeviceExtension Points to per-adapter device extension.
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// QueryBuffer Buffer where information will be stored.
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// BufferSize Size of the buffer to fill.
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//
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// RETURN VALUE:
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// Whether the call succeeded or not.
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//
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{
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struct query_structure * Query;
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I2C_FNC_TABLE i2c;
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ULONG Checksum;
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ULONG i;
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//
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// Get a formatted pointer into the query section of HW_DEVICE_EXTENSION.
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//
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Query = (struct query_structure *)phwDeviceExtension->CardInfo;
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//
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// Determine which class of hardware we are dealing with, since
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// different cards use different registers to control the SCL
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// and SDA lines. Don't worry about cards which don't support
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// DDC2, since the check for DDC support will have rejected
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// any of these cards so we won't reach this point in the code.
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//
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{
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i2c.WriteClockLine = WriteClockLineDAC;
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i2c.WriteDataLine = WriteDataLineDAC;
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i2c.ReadClockLine = ReadClockLineDAC;
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i2c.ReadDataLine = ReadDataLineDAC;
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i2c.WaitVsync = WaitForVsyncActiveDAC;
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VideoDebugPrint((DEBUG_NORMAL, "DAC DDC control"));
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}
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i2c.Size = sizeof(I2C_FNC_TABLE);
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if (!VideoPortDDCMonitorHelper(phwDeviceExtension,
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&i2c,
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QueryBuffer,
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BufferSize))
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{
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VideoDebugPrint((DEBUG_NORMAL, "DDC Query Failed\n"));
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return FALSE;
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}
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return TRUE;
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}
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#endif
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