505 lines
11 KiB
C
505 lines
11 KiB
C
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/* asmflt.c -- microsoft 80x86 assembler
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**
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** microsoft (r) macro assembler
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** copyright (c) microsoft corp 1986. all rights reserved
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**
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** randy nevin
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**
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** 10/90 - Quick conversion to 32 bit by Jeff Spencer
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*/
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#include <stdio.h>
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#include "asm86.h"
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#include "asmfcn.h"
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#include "asmctype.h"
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#include "asmopcod.h"
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#define TOLOWER(c) (c | 0x20) /* works only for alpha inputs */
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/* Handle 8087 opcodes, they have the following types:
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Fnoargs: No arguments at all.
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F2memstk: 0-2 args; memory 4,8 byte | ST,ST(i) | ST(i),ST
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| blank( equiv ST )
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Fstks: ST(i),ST
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Fmemstk: memory 4,8 | ST | ST(i) | blank
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Fstk: ST(i)
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Fmem42: memory 4,8 byte
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Fmem842: memory 2,4,8 bytes
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Fmem4810 memory 4,8,10 bytes | ST(i)
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Fmem2: memory 2 byte
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Fmem14: memory 14 bytes( don't force size )
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Fmem94: memory 94 bytes( don't force size )
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Fwait: Noargs, output WAIT
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Fbcdmem: memory Bcd
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*/
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/*** fltwait - output WAIT for 8087 instruction
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*
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* fltwait (p);
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*
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* Entry
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* Exit
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* Returns
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* Calls
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*/
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VOID PASCAL CODESIZE
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fltwait (
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UCHAR fseg
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){
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register SHORT idx;
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char override;
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register struct psop *pso;
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if (fltemulate) {
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idx = 0;
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/* Check for data and fixup space */
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if (pass2 && (emitcleanq ((UCHAR)(5)) || !fixroom (15)))
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emitdumpdata (0xA1); /* RN */
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if (opctype != FWAIT) {
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override = 0;
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if (fltdsc) {
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pso = &(fltdsc->dsckind.opnd);
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if ((idx = pso->seg) < NOSEG && idx != fseg)
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override = 1;
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}
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if (override)
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emitfltfix ('I',fltfixmisc[idx][0],&fltfixmisc[idx][1]);
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else
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emitfltfix ('I','D',&fltfixmisc[7][1]);
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}
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else {
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emitfltfix ('I','W', &fltfixmisc[8][1]);
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emitopcode(0x90);
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}
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}
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if (fltemulate || cputype&P86 || (cpu & FORCEWAIT)) {
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emitopcode (O_WAIT);
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if (fltemulate && override && idx)
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emitfltfix ('J',fltfixmisc[idx+3][0],&fltfixmisc[idx+3][1]);
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}
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}
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SHORT CODESIZE
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if_fwait()
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{
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/* if second byte of opcode is 'N', we don't generate fwait */
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return (TOLOWER(svname.pszName[1]) != 'n');
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}
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/*** fltmodrm - emit 8087 MODRM byte
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*
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* fltmodrm (base, p);
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*
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* Entry
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* Exit
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* Returns
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* Calls
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* Note The MODRM byte for 8087 opcode:
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* M M b b b R / M
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* M = mode, 3 is for non-memory 8087
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* b = base opcode. Together with ESC gives 6 bit opcode
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* R/M memory indexing type
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*/
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VOID PASCAL CODESIZE
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fltmodrm (
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register USHORT base,
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struct fltrec *p
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){
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register USHORT mod;
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mod = modrm;
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if (!fltdsc) {
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if (mod < 8)
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mod <<= 3;
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if (mod < 0xC0)
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mod += 0xC0;
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/* ST(i) mode */
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emitopcode ((UCHAR)(mod + base + p->stknum));
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}
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else {
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emitmodrm ((USHORT)fltdsc->dsckind.opnd.mode, (USHORT)(mod + base),
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fltdsc->dsckind.opnd.rm);
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emitrest (fltdsc);
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}
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}
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/*** fltscan - scan operands and build fltdsc
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*
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* fltscan (p);
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*
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* Entry
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* Exit
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* Returns
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* Calls
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*/
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VOID PASCAL CODESIZE
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fltscan (
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register struct fltrec *p
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){
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register struct psop *pso;
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p->args = FALSE;
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fltdsc = NULL;
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skipblanks ();
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if (ISTERM (PEEKC ())) {
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p->fseg = NOSEG;
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p->stknum = 1;
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}
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else {
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p->args = TRUE;
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p->fseg = DSSEG;
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fltdsc = expreval (&p->fseg);
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pso = &(fltdsc->dsckind.opnd);
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if (pso->mode == 3
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&& !(pso->rm == 0 && opcbase == O_FSTSW && modrm == R_FSTSW
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&& (cputype & (P286|P386))))
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errorc (E_IUR); /* Illegal use of reg */
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if (1 << FLTSTACK & pso->dtype) {
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/* Have ST or ST(i) */
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p->stknum = (USHORT)(pso->doffset & 7);
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if (pso->doffset > 7 || pso->dsign)
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/* # too big */
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errorc (E_VOR);
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if (pso->dsegment || pso->dcontext ||
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pso->dflag == XTERNAL || pso->mode != 4)
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/* Must have a constant */
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errorc (E_CXP);
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/* This means ST(i) */
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pso->mode = 3;
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oblititem (fltdsc);
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fltdsc = NULL;
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}
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else if (pso->mode == 4){
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/* pass1 error caused invalide mode assignment,
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map immdiate to direct, error on pass 2 */
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if (pass2)
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errorc(E_NIM);
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pso->mode = 2;
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if (wordsize == 4)
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pso->mode = 7;
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}
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}
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}
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/*** fltopcode - process 8087 opcode
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*
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* routine ();
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*
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* Entry
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* Exit
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* Returns
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* Calls
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*/
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VOID PASCAL CODESIZE
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fltopcode ()
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{
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struct fltrec a;
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USHORT i;
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register struct psop *pso;
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/* Save opcode name */
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switchname ();
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a.stknum = 0;
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/* Scan 1st arg, if any */
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fltscan (&a);
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if (if_fwait() || (opcbase == O_FNOP && modrm == R_FNOP))
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fltwait (a.fseg);
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if (fltdsc){
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pso = &(fltdsc->dsckind.opnd);
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emit67(pso, NULL);
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}
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switch (opctype) {
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case FNOARGS:
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/* No args allowed */
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a.stknum = 0;
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if (opcbase == O_FSETPM && modrm == R_FSETPM) {
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if (!(cputype&PROT))
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errorcSYN ();
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}
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/* Output escape byte */
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emitopcode (opcbase);
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fltmodrm (0, &a);
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if (a.args)
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/* Operands not allowed */
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errorc (E_ECL);
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break;
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case FWAIT:
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a.stknum = 0;
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if (a.args)
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/* Operands not allowed */
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errorc (E_ECL);
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break;
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case FSTK:
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if (TOLOWER(svname.pszName[1]) == 'f' && !a.args) /* ffree w/o arg */
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errorc(E_MOP);
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/* Output Escape */
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emitopcode (opcbase);
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/* Modrm byte */
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fltmodrm (0, &a);
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if (fltdsc)
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/*Must be ST(i) */
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errorc (E_IOT);
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break;
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case FMEM42:
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case FMEM842:
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case FMEM2:
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case FMEM14:
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case FMEM94:
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case FBCDMEM:
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/* All use a memory operand. Some force size */
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if (fltemulate && !if_fwait())
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/* Can't emulate */
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errorc (E_7OE);
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if (!fltdsc)
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/* must have arg */
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errorc (E_IOT);
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else {
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emitescape (fltdsc, a.fseg);
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if (opctype == FMEM42) {
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/* Integer 2,4 byte */
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forcesize (fltdsc);
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if (pso->dsize == 4)
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/* 4 byte */
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emitopcode (opcbase);
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else {
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emitopcode ((UCHAR)(opcbase + 4));
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if (pso->dsize != 2)
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errorc (E_IIS);
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}
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}
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else if (opctype == FMEM842) {
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/* Int 8,4,2 */
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forcesize (fltdsc);
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if (pso->dsize == 2 || pso->dsize == 8)
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emitopcode ((UCHAR)(opcbase + 4));
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else {
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emitopcode (opcbase);
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if (pso->dsize != 4)
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errorc (E_IIS);
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}
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}
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else if ((opctype == FMEM2) || (opctype == FBCDMEM)) {
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if (opctype == FMEM2)
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if (pso->dsize != 2 && pso->dsize)
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errorc (E_IIS);
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else {
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if (cputype & (P286|P386) &&
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opcbase == O_FSTSW && modrm == R_FSTSW &&
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pso->mode == 3 && pso->rm == 0) {
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opcbase = O_FSTSWAX;
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modrm = R_FSTSWAX;
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}
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}
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else if (pso->dsize != 10 && pso->dsize )
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errorc (E_IIS);
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emitopcode (opcbase);
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}
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else
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emitopcode (opcbase);
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if ((pso->mode == 3 || pso->mode == 4) &&
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(opcbase != O_FSTSWAX || modrm != R_FSTSWAX))
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/* Only memory operands */
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errorc (E_IOT);
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if (opctype == FMEM842 && pso->dsize == 8)
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if (TOLOWER(svname.pszName[2]) == 'l')
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fltmodrm (5, &a);
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else
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fltmodrm (4, &a);
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else
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fltmodrm (0, &a);
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}
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break;
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case FSTKS:
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if (!a.args)
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/* Operand required */
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errorc (E_MOP);
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else if (fltdsc)
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/* Must be stack */
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errorc (E_IOT);
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else {
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/* ESC */
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emitopcode (opcbase);
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/* ST(i) */
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fltmodrm (0, &a);
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if (PEEKC () != ',')
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error (E_EXP,"comma");
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/* Must have 2 args */
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/* Get 2nd operand */
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SKIPC ();
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fltscan (&a);
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pso = NULL;
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if (!a.args || fltdsc)
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errorc (E_IOT);
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if (a.stknum)
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errorc (E_OCI);
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}
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break;
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case FMEM4810:
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/* Fwait */
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if (TOLOWER(svname.pszName[1]) == 'l')
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/* FLD */
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if (!fltdsc) {/* Have ST(i) */
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if (!a.args) /* fld w/o arg */
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errorc(E_MOP);
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emitopcode (opcbase);
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fltmodrm (0, &a);
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}
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else {
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/* Any segment override */
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emitescape (fltdsc, a.fseg);
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if (pso->dsize == 10) {
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/* Have temp real */
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emitopcode ((UCHAR)(opcbase + 2));
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fltmodrm (5, &a);
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}
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else {
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/* Have normal real */
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forcesize (fltdsc);
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if (pso->dsize == 8)
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emitopcode ((UCHAR)(opcbase + 4));
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else {
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emitopcode (opcbase);
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if (pso->dsize != 4)
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errorc (E_IOT);
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}
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fltmodrm (0, &a);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if (!fltdsc) {
|
||
|
|
/* Have ST(i) */
|
||
|
|
/* Have FSTP */
|
||
|
|
if (!a.args)
|
||
|
|
errorc( E_IOT );
|
||
|
|
emitopcode ((UCHAR)(opcbase + 4));
|
||
|
|
fltmodrm (0, &a);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
emitescape (fltdsc, a.fseg);
|
||
|
|
/* Any segment override */
|
||
|
|
if (pso->dsize == 10) {
|
||
|
|
/* Have temp real */
|
||
|
|
emitopcode( (UCHAR)(opcbase + 2) );
|
||
|
|
fltmodrm (4, &a);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
/* Have normal real */
|
||
|
|
forcesize (fltdsc);
|
||
|
|
if (pso->dsize == 8)
|
||
|
|
emitopcode( (UCHAR)(opcbase + 4) );
|
||
|
|
else
|
||
|
|
emitopcode (opcbase);
|
||
|
|
fltmodrm (0, &a);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case F2MEMSTK:
|
||
|
|
if (!a.args) {
|
||
|
|
/* Have ST(1),ST */
|
||
|
|
emitopcode( (UCHAR)(opcbase + 6) );
|
||
|
|
if ((i = modrm & 7) > 3)
|
||
|
|
modrm = i^1;
|
||
|
|
fltmodrm (0, &a);
|
||
|
|
}
|
||
|
|
else if (!fltdsc) {/* Have stacks */
|
||
|
|
if (a.stknum == 0)
|
||
|
|
emitopcode (opcbase);
|
||
|
|
else {
|
||
|
|
/* Might need to reverse R bit */
|
||
|
|
if ((modrm & 7) > 3) /* Have FSUBx FDIVx */
|
||
|
|
modrm ^= 1;
|
||
|
|
emitopcode( (UCHAR)(opcbase + 4) );
|
||
|
|
/* D bit is set */
|
||
|
|
}
|
||
|
|
/* Save in case ST(i) */
|
||
|
|
a.stk1st = a.stknum;
|
||
|
|
if (PEEKC () != ',')
|
||
|
|
/* Must have , */
|
||
|
|
error (E_EXP,"comma");
|
||
|
|
/* Get 2nd operand */
|
||
|
|
SKIPC ();
|
||
|
|
fltscan (&a);
|
||
|
|
if (fltdsc)
|
||
|
|
/* not stack */
|
||
|
|
errorc (E_IOT);
|
||
|
|
if (a.args && a.stknum && a.stk1st)
|
||
|
|
errorc (E_IOT);
|
||
|
|
if (a.stk1st)
|
||
|
|
a.stknum = a.stk1st;
|
||
|
|
fltmodrm (0, &a);
|
||
|
|
}
|
||
|
|
else { /* Have real memory */
|
||
|
|
forcesize (fltdsc);
|
||
|
|
emitescape (fltdsc, a.fseg);
|
||
|
|
if (pso->dsize == 8)
|
||
|
|
emitopcode( (UCHAR)(opcbase + 4) );
|
||
|
|
else {
|
||
|
|
emitopcode (opcbase);
|
||
|
|
if (pso->dsize != 4)
|
||
|
|
errorc (E_IIS);
|
||
|
|
}
|
||
|
|
fltmodrm (0, &a);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case FMEMSTK:
|
||
|
|
if (!fltdsc)/* Have ST(i) */
|
||
|
|
if (TOLOWER(svname.pszName[1]) == 's') {
|
||
|
|
/* Special case */
|
||
|
|
if (!a.args)
|
||
|
|
errorc( E_IOT );
|
||
|
|
emitopcode( (UCHAR)(opcbase + 4) );
|
||
|
|
}
|
||
|
|
else
|
||
|
|
emitopcode (opcbase);
|
||
|
|
else {
|
||
|
|
/* Have real memory */
|
||
|
|
emitescape (fltdsc, a.fseg);
|
||
|
|
forcesize (fltdsc);
|
||
|
|
if (pso->dsize == 8)
|
||
|
|
emitopcode( (UCHAR)(opcbase + 4) );
|
||
|
|
else {
|
||
|
|
emitopcode (opcbase);
|
||
|
|
if (pso->dsize != 4)
|
||
|
|
errorc (E_IOT);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
fltmodrm (0, &a);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
if (fltdsc)
|
||
|
|
oblititem (fltdsc);
|
||
|
|
}
|