260 lines
6.9 KiB
ArmAsm
260 lines
6.9 KiB
ArmAsm
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/**
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*** Copyright (C) 1996-97 Intel Corporation. All rights reserved.
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***
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*** The information and source code contained herein is the exclusive
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*** property of Intel Corporation and may not be disclosed, examined
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*** or reproduced in whole or in part without explicit written authorization
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*** from the company.
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**/
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//++
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//
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// Module name
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// SIMSAL.S
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// Author
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// Allen Kay (akay) May-6-97
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// Description
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// Initializes the CPU and loads the first sector from the boot partition.
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// SIMSAL does the following:
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// 1. Initialize PSR with interrupt disabled.
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// 2. Invalidate ALAT.
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// 3. Invalidate RS.
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// 4. Setup GP.
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// 5. Set region registers rr[r0] - rr[r7] to RID=0, PS=8K, E=0.
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// 6. Initialize SP to 0x00902000.
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// 7. Initialize BSP to 0x00202000.
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// 8. Enable register stack engine.
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// 9. Setup IVA to 0x001F8000.
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// 10. Setup virtual->physical address translation
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// 0x80000000->0x00000000 in dtr0/itr0 for NT kernel.
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// 11. Setup virtual->physical address translation
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// 0x80400000->0x00400000 in dtr1/itr1 for HAL.dll.
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// 12. Setup virtual->physical address translation
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// 0x00800000->0x00800000 in dtr1/itr1 for NTLDR.
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//---
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#include "ksia64.h"
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#include "susetup.h"
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#include "ntfsdefs.h"
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.file "start.s"
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.global SscExit
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.type SscExit, @function
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.global ReadSectors
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.type ReadSectors, @function
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#define Buffer 0x0
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//
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// Interrupt Vector Table
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//
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#define VECTOR(Offset, Name) \
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.##org Offset; \
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Name:: \
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mov a0 = cr##.##iip; \
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br##.##call##.##sptk##.##clr brp = SscExit
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.section ivt = "ax", "progbits"
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BlIvtBase::
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VECTOR(0x0000, BlVhptTransVector)
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VECTOR(0x0400, BlInstTlbVector)
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VECTOR(0x0800, BlDataTlbVector)
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VECTOR(0x0C00, BlAltInstTlbVector)
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VECTOR(0x1000, BlAltDataTlbVector)
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VECTOR(0x1400, BlNestedTlbVector)
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VECTOR(0x1800, BlInstKeyMissVector)
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VECTOR(0x1C00, BlDataKeyMissVector)
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VECTOR(0x2000, BlDirtyBitVector)
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VECTOR(0x2400, BlInstAccessBitVector)
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VECTOR(0x2800, BlDataAccessBitVector)
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VECTOR(0x2C00, BlBreakVector)
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VECTOR(0x3000, BlExternalInterruptVector)
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VECTOR(0x5000, BlPageNotPresentVector)
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VECTOR(0x5100, BlKeyPermVector)
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VECTOR(0x5200, BlInstAccessRightsVector)
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VECTOR(0x5300, BlDataAccessRightsVector)
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VECTOR(0x5400, BlGeneralExceptionVector)
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VECTOR(0x5500, BlDisabledFpRegisterVector)
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VECTOR(0x5600, BlNatConsumptionVector)
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VECTOR(0x5700, BlSpeculationVector)
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VECTOR(0x6900, BlIA32ExceptionVector)
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VECTOR(0x6A00, BlIA32InterceptionVector)
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VECTOR(0x6B00, BlIA32InterruptionVector)
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// ***************************************************************************
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// Initialize the processor
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// ***************************************************************************
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NESTED_ENTRY(SimSal)
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NESTED_SETUP(3,3,8,0)
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PROLOGUE_END
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rpT0 = t22
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rpT1 = t21
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rpT2 = t20
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rpT3 = t19
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mov psr.l = zero // initialize psr.l
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movl t0 = FPSR_FOR_KERNEL
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mov ar.fpsr = t0 // initialize fpsr
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invala // invalidate ALAT
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mov ar.rsc = zero // invalidate register stack
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loadrs
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//
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// Initialize Region Registers
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//
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mov t0 = RR_PAGE_SIZE
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mov t1 = zero
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Bl_RRLoop:
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dep t2 = t2, t1, RR_SHIFT, RR_BITS
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mov rr[t2] = t0
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add t1 = 1, t1
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cmp4.geu pt0, pt1 = RR_SIZE, t1
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(pt0) br.cond.sptk.clr Bl_RRLoop
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//
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// Initialize the protection key registers with only pkr[0] = valid.
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//
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mov t0 = PKR_VALID
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mov t1 = zero
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mov pkr[t1] = t0
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mov t0 = zero
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Bl_PKRLoop:
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add t1 = t1, zero, 1 // increment PKR
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cmp.gtu pt0, pt1 = PKRNUM, t1
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(pt0) mov pkr[t1] = t0
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(pt0) br.cond.sptk.clr Bl_PKRLoop
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//
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// Setup SP
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//
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movl sp = BL_SP_BASE
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//
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// Set up tbe scratch area
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//
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add sp = -STACK_SCRATCH_AREA, sp
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//
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// Setup register stack backing store.
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//
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mov t0 = RSC_KERNEL_DISABLED
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mov ar.rsc = t0
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movl t1 = BL_SP_BASE
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mov ar.bspstore = t1
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//
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// Setup the base address of interrupt vector table
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//
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movl t0 = BlIvtBase
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mov cr.iva = t0
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//
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// Setup system address translation for NT kernel
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//
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//
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movl t0 = BOOT_SYSTEM_PAGE << PAGE_SHIFT
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ADDS4 (t0, 0, t0)
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mov cr.ifa = t0
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movl t1 = IDTR_IIP_VALUE(0,0,BL_PAGE_SIZE)
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mov cr.itir = t1
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movl t2 = TR_VALUE(1,BOOT_PHYSICAL_PAGE,3,0,1,1,1,1)
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mov t3 = zero
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itr.d dtr[t3] = t2
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itr.i itr[t3] = t2
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//
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// Setup the aliased kernel space
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//
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zxt4 t0 = t0 // zero extend kernel address
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mov t4 = 6 // create alias in region 6
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mov t5 = 2 // index
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dep t0 = t4, t0, 61, 3
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mov cr.ifa = t0
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itr.i itr[t5] = t2
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//
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// Setup 1-1 address translation for NT kernel
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//
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movl t0 = BOOT_USER_PAGE << PAGE_SHIFT
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ADDS4 (t0, 0, t0)
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mov cr.ifa = t0
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movl t2 = TR_VALUE(1,BOOT_USER_PAGE,3,0,1,1,1,1)
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add t3 = 1, t3
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itr.d dtr[t3] = t2
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itr.i itr[t3] = t2
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//
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// Turn on address translation, interrupt, psr.ed, protection key.
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//
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movl t1 = MASK(PSR_BN,1) | MASK(PSR_IT,1) | MASK(PSR_DA,1) | MASK(PSR_RT,1) | MASK(PSR_DT,1) | MASK(PSR_PK,1) | MASK(PSR_I,1)| MASK(PSR_IC,1)
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mov cr.ipsr = t1
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//
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// Initialize DCR to defer all speculation faults
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//
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movl t0 = DCR_DEFER_ALL
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mov cr.dcr = t0
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//
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// Read the first sector of the boot partition
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//
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mov out0 = zero
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movl out1 = 1
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movl out2 = Buffer
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mov ap = sp
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br.call.sptk.many brp = ReadSectors
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//
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// Read the first sector of the boot partition
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//
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mov out0 = zero
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#ifdef BSDT
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movl t0 = Buffer // get the sector count
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add rpT0 = 6, t0
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ld2 out1 = [rpT0]
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#else
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movl out1 = 64 // read 64 sectors, 32KB
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#endif
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movl out2 = Buffer
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mov ap = sp
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br.call.sptk.many brp = ReadSectors
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//
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// Now pass control to the first sector code
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//
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#ifdef BSDT
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movl t0 = Buffer // (the second sector).
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add rpT0 = 8, t0
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ld4 t1 = [rpT0]
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#else
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movl t1 = 0xd0 // since no bsdt, hardcode it for now.
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#endif
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mov cr.iip = t1
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rfi;;
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NESTED_EXIT(SimSal)
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