367 lines
9.6 KiB
C
367 lines
9.6 KiB
C
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/*++
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Copyright (c) 2001 Microsoft Corporation
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Module Name:
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pcienum.c
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Abstract:
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This module contains support routines for the Pci bus enumeration.
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Author:
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Bassam Tabbara (bassamt) 05-Aug-2001
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Environment:
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Real mode
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--*/
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#include "hwdetect.h"
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typedef VOID (*PINTERFACE_REFERENCE)(PVOID Context);
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typedef VOID (*PINTERFACE_DEREFERENCE)(PVOID Context);
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typedef PVOID PDEVICE_OBJECT;
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#include "pci.h"
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#include "pcienum.h"
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#define PCI_FIXED_HDR_LENGTH 16 // Through BIST
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#define UnusedParameter(x) (void)x
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#define X86_FLAG_IF 0x0200
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#define TURN_INTERRUPTS_OFF(_s_) \
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__asm { \
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__asm pushf \
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__asm pop ax \
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__asm mov _s_,ax \
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__asm cli \
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}
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#define RESTORE_INTERRUPTS(_s_) \
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do { \
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if ((_s_) & X86_FLAG_IF) { \
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__asm sti \
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} \
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} while (0)
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//////////////////////////////////////////////////////////// PCI Mechanism #0.
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//
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static ULONG PciReadInt32_0(
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UCHAR nBus,
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UCHAR nDev,
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UCHAR nFun,
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UCHAR nReg)
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{
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UnusedParameter(nBus);
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UnusedParameter(nDev);
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UnusedParameter(nFun);
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UnusedParameter(nReg);
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return ~0u;
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}
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static VOID PciWriteInt32_0(
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UCHAR nBus,
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UCHAR nDev,
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UCHAR nFun,
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UCHAR nReg,
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ULONG Data)
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{
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UnusedParameter(nBus);
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UnusedParameter(nDev);
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UnusedParameter(nFun);
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UnusedParameter(nReg);
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UnusedParameter(Data);
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return;
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}
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//////////////////////////////////////////////////////////// PCI Mechanism #1.
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//
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static ULONG PciReadInt32_1(
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UCHAR nBus,
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UCHAR nDev,
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UCHAR nFun,
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UCHAR nReg)
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{
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USHORT fl;
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ULONG data = 0;
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PCI_TYPE1_CFG_BITS cfg;
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cfg.u.bits.Reserved1 = 0;
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cfg.u.bits.RegisterNumber = nReg >> 2;
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cfg.u.bits.FunctionNumber = nFun;
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cfg.u.bits.DeviceNumber = nDev;
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cfg.u.bits.BusNumber = nBus;
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cfg.u.bits.Reserved2 = 0;
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cfg.u.bits.Enable = 1;
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TURN_INTERRUPTS_OFF(fl);
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WRITE_PORT_ULONG((PUSHORT)PCI_TYPE1_ADDR_PORT, (ULONG)cfg.u.AsULONG); // Select
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data = READ_PORT_ULONG((PUSHORT)PCI_TYPE1_DATA_PORT); // Fetch
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RESTORE_INTERRUPTS(fl);
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return data;
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}
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static VOID PciWriteInt32_1(
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UCHAR nBus,
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UCHAR nDev,
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UCHAR nFun,
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UCHAR nReg,
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ULONG Data)
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{
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USHORT fl;
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PCI_TYPE1_CFG_BITS cfg;
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cfg.u.bits.Reserved1 = 0;
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cfg.u.bits.RegisterNumber = nReg >> 2;
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cfg.u.bits.FunctionNumber = nFun;
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cfg.u.bits.DeviceNumber = nDev;
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cfg.u.bits.BusNumber = nBus;
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cfg.u.bits.Reserved2 = 0;
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cfg.u.bits.Enable = 1;
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TURN_INTERRUPTS_OFF(fl);
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WRITE_PORT_ULONG((PUSHORT)PCI_TYPE1_ADDR_PORT, cfg.u.AsULONG); // Select
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WRITE_PORT_ULONG((PUSHORT)PCI_TYPE1_DATA_PORT, Data); // Write
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RESTORE_INTERRUPTS(fl);
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}
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//////////////////////////////////////////////////////////// PCI Mechanism #2.
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//
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static ULONG PciReadInt32_2(
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UCHAR nBus,
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UCHAR nDev,
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UCHAR nFun,
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UCHAR nReg)
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{
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USHORT fl;
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ULONG data = 0;
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PCI_TYPE2_CSE_BITS cse;
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PCI_TYPE2_ADDRESS_BITS adr;
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cse.u.bits.Enable = 1;
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cse.u.bits.FunctionNumber = nFun;
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cse.u.bits.Key = 0xf;
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adr.u.bits.RegisterNumber = nReg;
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adr.u.bits.Agent = nDev;
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adr.u.bits.AddressBase = PCI_TYPE2_ADDRESS_BASE;
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TURN_INTERRUPTS_OFF(fl);
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WRITE_PORT_UCHAR((PUCHAR)PCI_TYPE2_FORWARD_PORT, nBus); // Select bus
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WRITE_PORT_UCHAR((PUCHAR)PCI_TYPE2_CSE_PORT, cse.u.AsUCHAR); // Select function & mapping
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data = READ_PORT_ULONG((PUSHORT)adr.u.AsUSHORT); // Fetch
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WRITE_PORT_UCHAR((PUCHAR)PCI_TYPE2_CSE_PORT, 0); // Disable mapping.
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RESTORE_INTERRUPTS(fl);
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return data;
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}
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static VOID PciWriteInt32_2(
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UCHAR nBus,
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UCHAR nDev,
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UCHAR nFun,
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UCHAR nReg,
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ULONG Data)
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{
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USHORT fl;
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PCI_TYPE2_CSE_BITS cse;
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PCI_TYPE2_ADDRESS_BITS adr;
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cse.u.bits.Enable = 1;
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cse.u.bits.FunctionNumber = nFun;
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cse.u.bits.Key = 0xf;
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adr.u.bits.RegisterNumber = nReg;
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adr.u.bits.Agent = nDev;
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adr.u.bits.AddressBase = PCI_TYPE2_ADDRESS_BASE;
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TURN_INTERRUPTS_OFF(fl);
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WRITE_PORT_UCHAR((PUCHAR)PCI_TYPE2_FORWARD_PORT, nBus); // Select bus
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WRITE_PORT_UCHAR((PUCHAR)PCI_TYPE2_CSE_PORT, cse.u.AsUCHAR); // Select function & mapping
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WRITE_PORT_ULONG((PUSHORT)adr.u.AsUSHORT, Data); // Write
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WRITE_PORT_UCHAR((PUCHAR)PCI_TYPE2_CSE_PORT, 0); // Disable mapping.
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RESTORE_INTERRUPTS(fl);
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}
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/////////////////////////////////////////////////////////// PCI Configuration.
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//
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typedef ULONG (*PF_PCI_READ)(UCHAR nBus,
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UCHAR nDev,
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UCHAR nFun,
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UCHAR nReg);
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typedef VOID (*PF_PCI_WRITE)(UCHAR nBus,
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UCHAR nDev,
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UCHAR nFun,
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UCHAR nReg,
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ULONG Data);
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static UCHAR s_nPciMajorRevision = 0;
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static UCHAR s_nPciMinorRevision = 0;
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static UCHAR s_nPciNumberOfBuses = 0;
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static PF_PCI_READ s_pPciRead = PciReadInt32_0;
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static PF_PCI_WRITE s_pPciWrite = PciWriteInt32_0;
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//////////////////////////////////////////////////////////////////////////////
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//
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ULONG PciReadConfig(USHORT nDevIt, ULONG cbOffset, UCHAR *pbData, ULONG cbData)
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{
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ULONG cbDone;
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UCHAR nBus = (UCHAR)PCI_ITERATOR_TO_BUS(nDevIt);
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UCHAR nDev = (UCHAR)PCI_ITERATOR_TO_DEVICE(nDevIt);
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UCHAR nFun = (UCHAR)PCI_ITERATOR_TO_FUNCTION(nDevIt);
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// CONFIG space is a space of aligned DWORDs, according to specs.
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// Therefore, if Offset is not aligned the caller is confused.
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//
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if ((cbOffset & 0x3) || (cbData & 0x3)) {
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#if DBG
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BlPrint("CPci::ReadConfig() called with Offset=x%x, Length=x%x\n", cbOffset, cbData);
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#endif
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return 0;
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}
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for (cbDone = 0; cbDone < cbData; cbDone += sizeof(ULONG)) {
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*((ULONG*)pbData)++ = s_pPciRead(nBus, nDev, nFun,
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(UCHAR)(cbOffset + cbDone));
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}
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return cbDone;
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}
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ULONG PciWriteConfig(USHORT nDevIt, ULONG cbOffset, UCHAR *pbData, ULONG cbData)
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{
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ULONG cbDone;
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UCHAR nBus = (UCHAR)PCI_ITERATOR_TO_BUS(nDevIt);
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UCHAR nDev = (UCHAR)PCI_ITERATOR_TO_DEVICE(nDevIt);
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UCHAR nFun = (UCHAR)PCI_ITERATOR_TO_FUNCTION(nDevIt);
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// CONFIG space is a space of aligned DWORDs, according to specs.
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// Therefore, if Offset is not aligned the caller is confused.
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//
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if ((cbOffset & 0x3) || (cbData & 0x3)) {
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#if DBG
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BlPrint("CPci::ReadConfig() called with Offset=x%x, Length=x%x\n", cbOffset, cbData);
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#endif
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return 0;
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}
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for (cbDone = 0; cbDone < cbData; cbDone += sizeof(ULONG)) {
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s_pPciWrite(nBus, nDev, nFun, (UCHAR)(cbOffset + cbDone),
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*((ULONG*)pbData)++);
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}
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return cbDone;
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}
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USHORT PciFindDevice(USHORT VendorId, USHORT DeviceId, USHORT nBegDevIt)
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{
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USHORT nDevIt;
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UCHAR nBus = 0;
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UCHAR nDev = 0;
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UCHAR nFun = 0;
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if (nBegDevIt != 0) {
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nBus = (UCHAR)PCI_ITERATOR_TO_BUS(nBegDevIt);
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nDev = (UCHAR)PCI_ITERATOR_TO_DEVICE(nBegDevIt);
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nFun = (UCHAR)(PCI_ITERATOR_TO_FUNCTION(nBegDevIt) + 1);
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}
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//
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// for each PCI bus
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//
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for (; nBus < s_nPciNumberOfBuses; nBus++) {
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//
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// for each PCI Device on the bus
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//
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for (; nDev < PCI_MAX_DEVICES; nDev++) {
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BOOLEAN bIsMultiFunction;
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PCI_COMMON_CONFIG config;
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//
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// Check if we have a device on function 0
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//
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config.VendorID = PCI_INVALID_VENDORID;
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PciReadConfig( PCI_TO_ITERATOR(nBus, nDev, 0),
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0,
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(UCHAR*)&config,
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PCI_FIXED_HDR_LENGTH );
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// No device on function 0, skip to next device
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if (config.VendorID == PCI_INVALID_VENDORID) {
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continue;
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}
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// check if the device is a multifunction device
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bIsMultiFunction = config.HeaderType & PCI_MULTIFUNCTION;
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for (; nFun < PCI_MAX_FUNCTION; nFun++) {
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// function numbers greater than zero
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// are only allowed on multifunction devices.
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if (nFun > 0 && !bIsMultiFunction) {
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break;
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}
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// Read configuration header.
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//
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nDevIt = PCI_TO_ITERATOR(nBus, nDev, nFun);
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config.VendorID = PCI_INVALID_VENDORID;
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PciReadConfig(nDevIt, 0, (UCHAR*)&config, PCI_FIXED_HDR_LENGTH);
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// No function found, skip to next function
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if (config.VendorID == PCI_INVALID_VENDORID) {
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continue;
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}
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if (VendorId == 0 ||
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(VendorId == config.VendorID &&
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(DeviceId == 0 || DeviceId == config.DeviceID))) {
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return nDevIt;
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}
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}
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nFun = 0;
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}
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nDev = 0;
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}
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return 0;
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}
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BOOLEAN PciInit(PCI_REGISTRY_INFO *pPCIReg)
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{
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s_nPciMajorRevision = pPCIReg->MajorRevision;
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s_nPciMinorRevision = pPCIReg->MinorRevision;
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s_nPciNumberOfBuses = pPCIReg->NoBuses;
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if ((pPCIReg->HardwareMechanism & 0x0F) == 1) {
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s_pPciRead = PciReadInt32_1;
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s_pPciWrite = PciWriteInt32_1;
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}
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else if ((pPCIReg->HardwareMechanism & 0x0F) == 2) {
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s_pPciRead = PciReadInt32_2;
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s_pPciWrite = PciWriteInt32_2;
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}
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else {
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#if DBG
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BlPrint("Unknown PCI HW Mechanism!\n");
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#endif
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return FALSE;
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}
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return TRUE;
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}
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