425 lines
21 KiB
C
425 lines
21 KiB
C
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#ifndef MERCED_H_INCLUDED
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#define MERCED_H_INCLUDED
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/*++
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Copyright (c) 1989-2000 Microsoft Corporation
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Component Name:
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HALIA64
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Module Name:
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merced.h
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Abstract:
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This header file presents IA64 Itanium [aka Merced] definitions.
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Like profiling definitions.
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Author:
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David N. Cutler (davec) 5-Mar-1989
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Environment:
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ToBeSpecified
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Revision History:
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3/15/2000 Thierry Fevrier (v-thief@microsoft.com):
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Initial version
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--*/
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//
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// MercedBranchPathPrediction - Branch Path Mask [XXTF: not really a mask, more a specification value].
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//
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typedef enum _MERCED_BRANCH_PATH_RESULT_MASK {
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MISPRED_NT = 0x0,
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MISPRED_TAKEN = 0x1,
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OKPRED_NT = 0x2,
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OKPRED_TAKEN = 0x3,
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} MERCED_BRANCH_PATH_RESULT_MASK;
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//
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// MercedBranchTakenDetail - Slot Unit Mask.
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//
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typedef enum _MERCED_BRANCH_TAKEN_DETAIL_SLOT_MASK {
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INSTRUCTION_SLOT0 = 0x1,
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INSTRUCTION_SLOT1 = 0x2,
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INSTRUCTION_SLOT2 = 0x4,
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NOT_TAKEN_BRANCH = 0x8
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} MERCED_BRANCH_TAKEN_DETAIL_SLOT_MASK;
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//
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// MercedBranchMultiWayDetail - Prediction OutCome Mask [XXTF: not really a mask, more a specification value].
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// MercedBranchMispredictDetail
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//
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typedef enum _MERCED_BRANCH_DETAIL_PREDICTION_OUTCOME_MASK {
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ALL_PREDICTIONS = 0x0,
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CORRECT_PREDICTION = 0x1,
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WRONG_PATH = 0x2,
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WRONG_TARGET = 0x3
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} MERCED_BRANCH_MWAY_DETAIL_PREDICTION_OUTCOME_MASK;
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//
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// MercedBranchMultiWayDetail - Branch Path Mask [XXTF: not really a mask, more a specification value].
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//
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typedef enum _MERCED_BRANCH_MWAY_DETAIL_BRANCH_PATH_MASK {
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NOT_TAKEN = 0x0,
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TAKEN = 0x1,
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ALL_PATH = 0x2
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} MERCED_BRANCH_MWAY_DETAIL_BRANCH_PATH_MASK;
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//
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// INST_TYPE for:
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//
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// MercedFailedSpeculativeCheckLoads
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// MercedAdvancedCheckLoads
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// MercedFailedAdvancedCheckLoads
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// MercedALATOverflows
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//
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typedef enum _MERCED_SPECULATION_EVENT_MASK {
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NONE = 0x0,
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INTEGER = 0x1,
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FP = 0x2,
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ALL = 0x3
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} MERCED_SPECULATION_EVENT_MASK;
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typedef enum _MERCED_MONITOR_EVENT_ALIAS {
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IA64_INSTS_RETIRED_EVENT_CODE = 0x09,
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FPOPS_RETIRED_EVENT_CODE = 0x0a,
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} MERCED_MONITOR_EVENT_ALIAS;
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//
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// MercedCpuCycles - Executing Instruction Set
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//
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typedef enum _MERCED_CPU_CYCLES_MODE_MASK {
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ALL_MODES = 0x0,
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IA64_MODE = 0x1,
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IA32_MODE = 0x2
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} MERCED_CPU_CYCLES_MODE_MASK;
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//
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// Merced Monitored Events:
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//
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typedef enum _MERCED_MONITOR_EVENT {
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MercedMonitoredEventMinimum = 0x00,
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MercedBranchMispredictStallCycles = 0x00, // "BRANCH_MISPRED_CYCLE"
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MercedInstAccessStallCycles = 0x01, // "INST_ACCESS_CYCLE"
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MercedExecLatencyStallCycles = 0x02, // "EXEC_LATENCY_CYCLE"
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MercedDataAccessStallCycles = 0x03, // "DATA_ACCESS_CYCLE"
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MercedBranchStallCycles = 0x04, // "BRANCH_CYCLE",
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MercedInstFetchStallCycles = 0x05, // "INST_FETCH_CYCLE",
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MercedExecStallCycles = 0x06, // "EXECUTION_CYCLE",
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MercedMemoryStallCycles = 0x07, // "MEMORY_CYCLE",
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MercedTaggedInstRetired = 0x08, // "IA64_TAGGED_INSTRS_RETIRED", XXTF - ToBeDone: Set Event Qualification
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MercedInstRetired = IA64_INSTS_RETIRED_EVENT_CODE, // "IA64_INSTS_RETIRED.u", XXTF - ToBeDone: Set Umask - 0x0.
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MercedFPOperationsRetired = FPOPS_RETIRED_EVENT_CODE, // "FPOPS_RETIRED", XXTF - ToBeDone: Set IA64_TAGGED_INSTRS_RETIRED opcode
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MercedFPFlushesToZero = 0x0b, // "FP_FLUSH_TO_ZERO",
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MercedSIRFlushes = 0x0c, // "FP_SIR_FLUSH",
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MercedBranchTakenDetail = 0x0d, // "BR_TAKEN_DETAIL", // XXTF - ToBeDone - Slot specification[0,1,2,NO] + addresses range
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MercedBranchMultiWayDetail = 0x0e, // "BR_MWAY_DETAIL", // XXTF - ToBeDone - Not taken/Taken/all path + Prediction outcome + address range
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MercedBranchPathPrediction = 0x0f, // "BR_PATH_PREDICTION", // XXTF - ToBeDone - BRANCH_PATH_RESULT specification + address range
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MercedBranchMispredictDetail = 0x10, // "BR_MISPREDICT_DETAIL", // XXTF - ToBeDone - Prediction outcome specification + address range
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MercedBranchEvents = 0x11, // "BRANCH_EVENT",
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MercedCpuCycles = 0x12, // "CPU_CYCLES", // XXTF - ToBeDone - All/IA64/IA32
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MercedISATransitions = 0x14, // "ISA_TRANSITIONS",
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MercedIA32InstRetired = 0x15, // "IA32_INSTR_RETIRED",
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MercedL1InstReads = 0x20, // "L0I_READS", // XXTF - ToBeDone - + address range
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MercedL1InstFills = 0x21, // "L0I_FILLS", // XXTF - ToBeDone - + address range
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MercedL1InstMisses = 0x22, // "L0I_MISSES", // XXTF - ToBeDone - + address range
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MercedInstEAREvents = 0x23, // "INSTRUCTION_EAR_EVENTS",
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MercedL1InstPrefetches = 0x24, // "L0I_IPREFETCHES", // XXTF - ToBeDone - + address range
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MercedL2InstPrefetches = 0x25, // "L1_INST_PREFETCHES", // XXTF - ToBeDone - + address range
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MercedInstStreamingBufferLinesIn = 0x26, // "ISB_LINES_IN", // XXTF - ToBeDone - + address range
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MercedInstTLBDemandFetchMisses = 0x27, // "ITLB_MISSES_FETCH", // XXTF - ToBeDone - + ??? address range + PMC.umask on L1ITLB/L2ITLB/ALL/NOTHING.
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MercedInstTLBHPWInserts = 0x28, // "ITLB_INSERTS_HPW", // XXTF - ToBeDone - + ??? address range
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MercedInstDispersed = 0x2d, // "INST_DISPERSED",
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MercedExplicitStops = 0x2e, // "EXPL_STOPBITS",
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MercedImplicitStops = 0x2f, // "IMPL_STOPS_DISPERSED",
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MercedInstNOPRetired = 0x30, // "NOPS_RETIRED",
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MercedInstPredicateSquashedRetired = 0x31, // "PREDICATE_SQUASHED_RETIRED",
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MercedRSELoadRetired = 0x32, // "RSE_LOADS_RETIRED",
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MercedPipelineFlushes = 0x33, // "PIPELINE_FLUSH",
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MercedCpuCPLChanges = 0x34, // "CPU_CPL_CHANGES",
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MercedFailedSpeculativeCheckLoads = 0x35, // "INST_FAILED_CHKS_RETIRED", // XXTF - ToBeDone - INST_TYPE
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MercedAdvancedCheckLoads = 0x36, // "ALAT_INST_CHKA_LDC", // XXTF - ToBeDone - INST_TYPE
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MercedFailedAdvancedCheckLoads = 0x37, // "ALAT_INST_FAILED_CHKA_LDC", // XXTF - ToBeDone - INST_TYPE
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MercedALATOverflows = 0x38, // "ALAT_CAPACITY_MISS", // XXTF - ToBeDone - INST_TYPE
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MercedExternBPMPins03Asserted = 0x5e, // "EXTERN_BPM_PINS_0_TO_3",
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MercedExternBPMPins45Asserted = 0x5f, // "EXTERN_BPM_PINS_4_TO_5",
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MercedDataTCMisses = 0x60, // "DTC_MISSES", // XXTF - ToBeDone - + ??? address range
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MercedDataTLBMisses = 0x61, // "DTLB_MISSES", // XXTF - ToBeDone - + ??? address range
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MercedDataTLBHPWInserts = 0x62, // "DTLB_INSERTS_HPW", // XXTF - ToBeDone - + ??? address range
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MercedDataReferences = 0x63, // "DATA_REFERENCES_RETIRED", // XXTF - ToBeDone - + ibr, opcode, dbr
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MercedL1DataReads = 0x64, // "L1D_READS_RETIRED", // XXTF - ToBeDone - + ibr, opcode, dbr
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MercedRSEAccesses = 0x65, // "RSE_REFERENCES_RETIRED",
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MercedL1DataReadMisses = 0x66, // "L1D_READ_MISSES_RETIRED", // XXTF - ToBeDone - + ibr, opcode, dbr
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MercedL1DataEAREvents = 0x67, // "DATA_EAR_EVENTS",
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MercedL2References = 0x68, // "L2_REFERENCES", // XXTF - ToBeDone - + ibr, opcode, dbr
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MercedL2DataReferences = 0x69, // "L2_DATA_REFERENCES", // XXTF - ToBeDone - + ibr, opcode, dbr
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MercedL2Misses = 0x6a, // "L2_MISSES", // XXTF - ToBeDone - + ibr, opcode, dbr
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MercedL1DataForcedLoadMisses = 0x6b, // "L1D_READ_FORCED_MISSES_RETIRED", // XXTF - ToBeDone - + ibr, opcode, dbr
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MercedRetiredLoads = 0x6c, // "LOADS_RETIRED",
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MercedRetiredStores = 0x6d, // "STORES_RETIRED",
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MercedRetiredUncacheableLoads = 0x6e, // "UC_LOADS_RETIRED",
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MercedRetiredUncacheableStores = 0x6f, // "UC_STORES_RETIRED",
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MercedRetiredMisalignedLoads = 0x70, // "MISALIGNED_LOADS_RETIRED",
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MercedRetiredMisalignedStores = 0x71, // "MISALIGNED_STORES_RETIRED",
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MercedL2Flushes = 0x76, // "L2_FLUSHES", // XXTF - ToBeDone - + ibr, opcode, dbr
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MercedL2FlushesDetail = 0x77, // "L2_FLUSH_DETAILS", // XXTF - ToBeDone - + ibr, opcode, dbr
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MercedL3References = 0x7b, // "L3_REFERENCES",
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MercedL3Misses = 0x7c, // "L3_MISSES",
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MercedL3Reads = 0x7d, // "L3_READS",
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MercedL3Writes = 0x7e, // "L3_WRITES",
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MercedL3LinesReplaced = 0x7f, // "L3_LINES_REPLACED",
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//
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// 02/08/00 - Are missing: [at least]
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// - Front-Side bus events,
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// - IVE events,
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// - Debug monitor events,
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// - ...
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//
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} MERCED_MONITOR_EVENT;
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//
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// Merced Derived Events:
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//
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// Assumption: MercedDerivedEventMinimum > MercedMonitoredEventMaximum.
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//
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typedef enum _MERCED_DERIVED_EVENT {
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MercedDerivedEventMinimum = 0x100, /* > Maximum of Merced Monitored Event */
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MercedRSEStallCycles = MercedDerivedEventMinimum, // XXTF - ToBeDone - (MercedMemoryStallCycles - MercedDataStallAccessCycles)
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MercedIssueLimitStallCycles, // XXTF - ToBeDone - (MercedExecStallCycles - MercedExecLatencyStallCycles)
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MercedTakenBranchStallCycles, // XXTF - ToBeDone - (MercedBranchStallCycles - MercedBranchMispredictStallCycles)
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MercedFetchWindowStallCycles, // XXTF - ToBeDone - (MercedInstFetchStallCycles - MercedInstAccessStallCycles)
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MercedIA64InstPerCycle, // XXTF - ToBeDone - (IA64_INST_RETIRED.u / CPU_CYCLES[IA64])
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MercedIA32InstPerCycle, // XXTF - ToBeDone - (IA32_INSTR_RETIRED / CPU_CYCLES[IA32])
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MercedAvgIA64InstPerTransition, // XXTF - ToBeDone - (IA64_INST_RETIRED.u / (ISA_TRANSITIONS * 2))
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MercedAvgIA32InstPerTransition, // XXTF - ToBeDone - (IA32_INSTR_RETIRED / (ISA_TRANSITIONS * 2))
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MercedAvgIA64CyclesPerTransition, // XXTF - ToBeDone - (CPU_CYCLES[IA64] / (ISA_TRANSITIONS * 2))
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MercedAvgIA32CyclesPerTransition, // XXTF - ToBeDone - (CPU_CYCLES[IA32] / (ISA_TRANSITIONS * 2))
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MercedL1InstReferences, // XXTF - ToBeDone - (L1I_READS / L1I_IPREFETCHES)
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MercedL1InstMissRatio, // XXTF - ToBeDone - (L1I_MISSES / MercedL1InstReferences)
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MercedL1DataReadMissRatio, // XXTF - ToBeDone - (L1D_READS_MISSES_RETIRED / L1D_READS_RETIRED)
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MercedL2MissRatio, // XXTF - ToBeDone - (L2_MISSES / L2_REFERENCES)
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MercedL2DataMissRatio, // XXTF - ToBeDone - (L3_DATA_REFERENCES / L2_DATA_REFERENCES)
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MercedL2InstMissRatio, // XXTF - ToBeDone - (L3_DATA_REFERENCES / L2_DATA_REFERENCES)
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MercedL2DataReadMissRatio, // XXTF - ToBeDone - (L3_LOAD_REFERENCES.u / L2_DATA_READS.u)
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MercedL2DataWriteMissRatio, // XXTF - ToBeDone - (L3_STORE_REFERENCES.u / L2_DATA_WRITES.u)
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MercedL2InstFetchRatio, // XXTF - ToBeDone - (L1I_MISSES / L2_REFERENCES)
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MercedL2DataRatio, // XXTF - ToBeDone - (L2_DATA_REFERENCES / L2_REFERENCES)
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MercedL3MissRatio, // XXTF - ToBeDone - (L3_MISSES / L2_MISSES)
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MercedL3DataMissRatio, // XXTF - ToBeDone - ((L3_LOAD_MISSES.u + L3_STORE_MISSES.u) / L3_REFERENCES.d)
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MercedL3InstMissRatio, // XXTF - ToBeDone - (L3_INST_MISSES.u / L3_INST_REFERENCES.u)
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MercedL3DataReadMissRatio, // XXTF - ToBeDone - (L3_LOAD_REFERENCES.u / L3_DATA_REFERENCES.d)
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MercedL3DataRatio, // XXTF - ToBeDone - (L3_DATA_REFERENCES.d / L3_REFERENCES)
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MercedInstReferences, // XXTF - ToBeDone - (L1I_READS)
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MercedInstTLBMissRatio, // XXTF - ToBeDone - (ITLB_MISSES_FETCH / L1I_READS)
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MercedDataTLBMissRatio, // XXTF - ToBeDone - (DTLB_MISSES / DATA_REFERENCES_RETIRED)
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MercedDataTCMissRatio, // XXTF - ToBeDone - (DTC_MISSES / DATA_REFERENCES_RETIRED)
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MercedInstTLBEAREvents, // XXTF - ToBeDone - (INSTRUCTION_EAR_EVENTS)
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MercedDataTLBEAREvents, // XXTF - ToBeDone - (DATA_EAR_EVENTS)
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MercedCodeDebugRegisterMatches, // XXTF - ToBeDone - (IA64_TAGGED_INSTRS_RETIRED)
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MercedDataDebugRegisterMatches, // XXTF - ToBeDone - (LOADS_RETIRED + STORES_RETIRED)
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MercedControlSpeculationMissRatio, // XXTF - ToBeDone - (INST_FAILED_CHKS_RETIRED / IA64_TAGGED_INSTRS_RETIRED[chk.s])
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MercedDataSpeculationMissRatio, // XXTF - ToBeDone - (ALAT_INST_FAILED_CHKA_LDC / ALAT_INST_CHKA_LDC)
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MercedALATCapacityMissRatio, // XXTF - ToBeDone - (ALAT_CAPACITY_MISS / IA64_TAGGED_INSTRS_RETIRED[ld.sa,ld.a,ldfp.a,ldfp.sa])
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MercedL1DataWayMispredicts, // XXTF - ToBeDone - (EventCode: 0x33 / Umask: 0x2)
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MercedL2InstReferences, // XXTF - ToBeDone - (L1I_MISSES + L2_INST_PREFETCHES)
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MercedInstFetches, // XXTF - ToBeDone - (L1I_MISSES)
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MercedL2DataReads, // XXTF - ToBeDone - (L2_DATA_REFERENCES/0x1)
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MercedL2DataWrites, // XXTF - ToBeDone - (L2_DATA_REFERENCES/0x2)
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MercedL3InstReferences, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
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MercedL3InstMisses, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
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MercedL3InstHits, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
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MercedL3DataReferences, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
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MercedL3LoadReferences, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
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|
MercedL3LoadMisses, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL3LoadHits, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL3ReadReferences, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL3ReadMisses, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL3ReadHits, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL3StoreReferences, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL3StoreMisses, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL3StoreHits, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL2WriteBackReferences, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL2WriteBackMisses, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL2WriteBackHits, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL2WriteReferences, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL2WriteMisses, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedL2WriteHits, // XXTF - ToBeDone - (PMC.umask{17:16}HIT/MISS/ALL + PMC.umask{19:18})
|
||
|
|
MercedBranchInstructions, // XXTF - ToBeDone - (TAGGED_INSTR + opcode)
|
||
|
|
MercedIntegerInstructions, // XXTF - ToBeDone - (TAGGED_INSTR + opcode)
|
||
|
|
MercedL1DataMisses, // XXTF - ToBeDone -
|
||
|
|
} MERCED_DERIVED_EVENT;
|
||
|
|
|
||
|
|
typedef enum _KPROFILE_MERCED_SOURCE {
|
||
|
|
//
|
||
|
|
// Profile Merced Monitored Events:
|
||
|
|
//
|
||
|
|
ProfileMercedMonitoredEventMinimum = ProfileMaximum + 0x1,
|
||
|
|
ProfileMercedBranchMispredictStallCycles = ProfileMercedMonitoredEventMinimum,
|
||
|
|
ProfileMercedInstAccessStallCycles,
|
||
|
|
ProfileMercedExecLatencyStallCycles,
|
||
|
|
ProfileMercedDataAccessStallCycles,
|
||
|
|
ProfileMercedBranchStallCycles,
|
||
|
|
ProfileMercedInstFetchStallCycles,
|
||
|
|
ProfileMercedExecStallCycles,
|
||
|
|
ProfileMercedMemoryStallCycles,
|
||
|
|
ProfileMercedTaggedInstRetired,
|
||
|
|
ProfileMercedInstRetired,
|
||
|
|
ProfileMercedFPOperationsRetired,
|
||
|
|
ProfileMercedFPFlushesToZero,
|
||
|
|
ProfileMercedSIRFlushes,
|
||
|
|
ProfileMercedBranchTakenDetail,
|
||
|
|
ProfileMercedBranchMultiWayDetail,
|
||
|
|
ProfileMercedBranchPathPrediction,
|
||
|
|
ProfileMercedBranchMispredictDetail,
|
||
|
|
ProfileMercedBranchEvents,
|
||
|
|
ProfileMercedCpuCycles,
|
||
|
|
ProfileMercedISATransitions,
|
||
|
|
ProfileMercedIA32InstRetired,
|
||
|
|
ProfileMercedL1InstReads,
|
||
|
|
ProfileMercedL1InstFills,
|
||
|
|
ProfileMercedL1InstMisses,
|
||
|
|
ProfileMercedInstEAREvents,
|
||
|
|
ProfileMercedL1InstPrefetches,
|
||
|
|
ProfileMercedL2InstPrefetches,
|
||
|
|
ProfileMercedInstStreamingBufferLinesIn,
|
||
|
|
ProfileMercedInstTLBDemandFetchMisses,
|
||
|
|
ProfileMercedInstTLBHPWInserts,
|
||
|
|
ProfileMercedInstDispersed,
|
||
|
|
ProfileMercedExplicitStops,
|
||
|
|
ProfileMercedImplicitStops,
|
||
|
|
ProfileMercedInstNOPRetired,
|
||
|
|
ProfileMercedInstPredicateSquashedRetired,
|
||
|
|
ProfileMercedRSELoadRetired,
|
||
|
|
ProfileMercedPipelineFlushes,
|
||
|
|
ProfileMercedCpuCPLChanges,
|
||
|
|
ProfileMercedFailedSpeculativeCheckLoads,
|
||
|
|
ProfileMercedAdvancedCheckLoads,
|
||
|
|
ProfileMercedFailedAdvancedCheckLoads,
|
||
|
|
ProfileMercedALATOverflows,
|
||
|
|
ProfileMercedExternBPMPins03Asserted,
|
||
|
|
ProfileMercedExternBPMPins45Asserted,
|
||
|
|
ProfileMercedDataTCMisses,
|
||
|
|
ProfileMercedDataTLBMisses,
|
||
|
|
ProfileMercedDataTLBHPWInserts,
|
||
|
|
ProfileMercedDataReferences,
|
||
|
|
ProfileMercedL1DataReads,
|
||
|
|
ProfileMercedRSEAccesses,
|
||
|
|
ProfileMercedL1DataReadMisses,
|
||
|
|
ProfileMercedL1DataEAREvents,
|
||
|
|
ProfileMercedL2References,
|
||
|
|
ProfileMercedL2DataReferences,
|
||
|
|
ProfileMercedL2Misses,
|
||
|
|
ProfileMercedL1DataForcedLoadMisses,
|
||
|
|
ProfileMercedRetiredLoads,
|
||
|
|
ProfileMercedRetiredStores,
|
||
|
|
ProfileMercedRetiredUncacheableLoads,
|
||
|
|
ProfileMercedRetiredUncacheableStores,
|
||
|
|
ProfileMercedRetiredMisalignedLoads,
|
||
|
|
ProfileMercedRetiredMisalignedStores,
|
||
|
|
ProfileMercedL2Flushes,
|
||
|
|
ProfileMercedL2FlushesDetail,
|
||
|
|
ProfileMercedL3References,
|
||
|
|
ProfileMercedL3Misses,
|
||
|
|
ProfileMercedL3Reads,
|
||
|
|
ProfileMercedL3Writes,
|
||
|
|
ProfileMercedL3LinesReplaced,
|
||
|
|
//
|
||
|
|
// 02/08/00 - Are missing: [at least]
|
||
|
|
// - Front-Side bus events,
|
||
|
|
// - IVE events,
|
||
|
|
// - Debug monitor events,
|
||
|
|
// - ...
|
||
|
|
//
|
||
|
|
//
|
||
|
|
// Profile Merced Derived Events:
|
||
|
|
//
|
||
|
|
ProfileMercedDerivedEventMinimum,
|
||
|
|
ProfileMercedRSEStallCycles = ProfileMercedDerivedEventMinimum,
|
||
|
|
ProfileMercedIssueLimitStallCycles,
|
||
|
|
ProfileMercedTakenBranchStallCycles,
|
||
|
|
ProfileMercedFetchWindowStallCycles,
|
||
|
|
ProfileMercedIA64InstPerCycle,
|
||
|
|
ProfileMercedIA32InstPerCycle,
|
||
|
|
ProfileMercedAvgIA64InstPerTransition,
|
||
|
|
ProfileMercedAvgIA32InstPerTransition,
|
||
|
|
ProfileMercedAvgIA64CyclesPerTransition,
|
||
|
|
ProfileMercedAvgIA32CyclesPerTransition,
|
||
|
|
ProfileMercedL1InstReferences,
|
||
|
|
ProfileMercedL1InstMissRatio,
|
||
|
|
ProfileMercedL1DataReadMissRatio,
|
||
|
|
ProfileMercedL2MissRatio,
|
||
|
|
ProfileMercedL2DataMissRatio,
|
||
|
|
ProfileMercedL2InstMissRatio,
|
||
|
|
ProfileMercedL2DataReadMissRatio,
|
||
|
|
ProfileMercedL2DataWriteMissRatio,
|
||
|
|
ProfileMercedL2InstFetchRatio,
|
||
|
|
ProfileMercedL2DataRatio,
|
||
|
|
ProfileMercedL3MissRatio,
|
||
|
|
ProfileMercedL3DataMissRatio,
|
||
|
|
ProfileMercedL3InstMissRatio,
|
||
|
|
ProfileMercedL3DataReadMissRatio,
|
||
|
|
ProfileMercedL3DataRatio,
|
||
|
|
ProfileMercedInstReferences,
|
||
|
|
ProfileMercedInstTLBMissRatio,
|
||
|
|
ProfileMercedDataTLBMissRatio,
|
||
|
|
ProfileMercedDataTCMissRatio,
|
||
|
|
ProfileMercedInstTLBEAREvents,
|
||
|
|
ProfileMercedDataTLBEAREvents,
|
||
|
|
ProfileMercedCodeDebugRegisterMatches,
|
||
|
|
ProfileMercedDataDebugRegisterMatches,
|
||
|
|
ProfileMercedControlSpeculationMissRatio,
|
||
|
|
ProfileMercedDataSpeculationMissRatio,
|
||
|
|
ProfileMercedALATCapacityMissRatio,
|
||
|
|
ProfileMercedL1DataWayMispredicts,
|
||
|
|
ProfileMercedL2InstReferences,
|
||
|
|
ProfileMercedInstFetches,
|
||
|
|
ProfileMercedL2DataReads,
|
||
|
|
ProfileMercedL2DataWrites,
|
||
|
|
ProfileMercedL3InstReferences,
|
||
|
|
ProfileMercedL3InstMisses,
|
||
|
|
ProfileMercedL3InstHits,
|
||
|
|
ProfileMercedL3DataReferences,
|
||
|
|
ProfileMercedL3LoadReferences,
|
||
|
|
ProfileMercedL3LoadMisses,
|
||
|
|
ProfileMercedL3LoadHits,
|
||
|
|
ProfileMercedL3ReadReferences,
|
||
|
|
ProfileMercedL3ReadMisses,
|
||
|
|
ProfileMercedL3ReadHits,
|
||
|
|
ProfileMercedL3StoreReferences,
|
||
|
|
ProfileMercedL3StoreMisses,
|
||
|
|
ProfileMercedL3StoreHits,
|
||
|
|
ProfileMercedL2WriteBackReferences,
|
||
|
|
ProfileMercedL2WriteBackMisses,
|
||
|
|
ProfileMercedL2WriteBackHits,
|
||
|
|
ProfileMercedL2WriteReferences,
|
||
|
|
ProfileMercedL2WriteMisses,
|
||
|
|
ProfileMercedL2WriteHits,
|
||
|
|
ProfileMercedBranchInstructions,
|
||
|
|
ProfileMercedIntegerInstructions,
|
||
|
|
ProfileMercedL1DataMisses,
|
||
|
|
ProfileMercedMaximum
|
||
|
|
} KPROFILE_MERCED_SOURCE, *PKPROFILE_MERCED_SOURCE;
|
||
|
|
|
||
|
|
#define ProfileIA64Maximum ProfileMercedMaximum
|
||
|
|
|
||
|
|
#endif /* MERCED_H_INCLUDED */
|
||
|
|
|
||
|
|
|