561 lines
14 KiB
NASM
561 lines
14 KiB
NASM
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title "Irql Processing"
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;++
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;
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; Copyright (c) 1989 Microsoft Corporation
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; Copyright (c) 1992 Intel Corporation
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; All rights reserved
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;
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; INTEL CORPORATION PROPRIETARY INFORMATION
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;
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; This software is supplied to Microsoft under the terms
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; of a license agreement with Intel Corporation and may not be
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; copied nor disclosed except in accordance with the terms
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; of that agreement.
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;
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;
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; Module Name:
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;
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; mpirql.asm
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;
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; Abstract:
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;
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; This module implements the mechanism for raising and lowering IRQL
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; and dispatching software interrupts for PC+MP compatible systems
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;
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; Author:
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;
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; Shie-Lin Tzong (shielint) 8-Jan-1990
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;
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; Environment:
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;
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; Kernel mode only.
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;
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; Revision History:
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;
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; Ron Mosgrove (Intel) Sept 1993
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; Modified for PC+MP
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;
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;--
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.386p
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.xlist
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include hal386.inc
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include callconv.inc ; calling convention macros
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include mac386.inc
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include apic.inc
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include ntapic.inc
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include i386\kimacro.inc
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.list
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EXTRNP _KeBugCheck,1,IMPORT
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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align dword
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;
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; Global8259Mask is used to avoid reading the PIC to get the current
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; interrupt mask; format is the same as for SET_8259_MASK, i.e.,
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; bits 7:0 -> PIC1, 15:8 -> PIC2
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;
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public _HalpGlobal8259Mask
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_HalpGlobal8259Mask dw 0
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_DATA ends
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_TEXT SEGMENT DWORD PUBLIC 'DATA'
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;
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; IOunitRedirectionTable is the memory image of the redirection table to be
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; loaded into APIC I/O unit 0 at initialization. there is one 64-bit entry
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; per interrupt input to the I/O unit. the edge/level trigger mode bit will
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; be set dynamically when the table is actually loaded. the mask bit is set
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; initially, and reset by EnableSystemInterrupt.
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;
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;
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; _HalpIRQLtoTPR maps IRQL to an APIC TPR register value
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;
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align dword
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public _HalpIRQLtoTPR
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_HalpIRQLtoTPR label byte
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db ZERO_VECTOR ; IRQL 0
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db APC_VECTOR ; IRQL 1
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db DPC_VECTOR ; IRQL 2
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db DPC_VECTOR ; IRQL 3
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db DEVICE_LEVEL1 ; IRQL 4
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db DEVICE_LEVEL2 ; IRQL 5
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db DEVICE_LEVEL3 ; IRQL 6
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db DEVICE_LEVEL4 ; IRQL 7
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db DEVICE_LEVEL5 ; IRQL 8
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db DEVICE_LEVEL6 ; IRQL 9
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db DEVICE_LEVEL7 ; IRQL 10
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db DEVICE_LEVEL7 ; IRQL 11
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db DEVICE_LEVEL7 ; IRQL 12
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db DEVICE_LEVEL7 ; IRQL 13
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db DEVICE_LEVEL7 ; IRQL 14
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db DEVICE_LEVEL7 ; IRQL 15
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db DEVICE_LEVEL7 ; IRQL 16
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db DEVICE_LEVEL7 ; IRQL 17
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db DEVICE_LEVEL7 ; IRQL 18
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db DEVICE_LEVEL7 ; IRQL 19
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db DEVICE_LEVEL7 ; IRQL 20
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db DEVICE_LEVEL7 ; IRQL 21
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db DEVICE_LEVEL7 ; IRQL 22
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db DEVICE_LEVEL7 ; IRQL 23
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db DEVICE_LEVEL7 ; IRQL 24
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db DEVICE_LEVEL7 ; IRQL 25
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db DEVICE_LEVEL7 ; IRQL 26
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db APIC_GENERIC_VECTOR ; IRQL 27
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db APIC_CLOCK_VECTOR ; IRQL 28
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db APIC_IPI_VECTOR ; IRQL 29
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db POWERFAIL_VECTOR ; IRQL 30
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db NMI_VECTOR ; IRQL 31
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_TEXT ends
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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;
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; VECTOR_MAP_ENTRY macro generates sparse table required for APIC vectors
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;
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VECTOR_MAP_ENTRY macro vector_number, apic_inti
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current_entry = $ - _HalpVectorToINTI
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entry_count = vector_number - current_entry
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REPT entry_count
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dw 0ffffh
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ENDM
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dw apic_inti
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endm
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;
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; _HalpVectorToINTI maps interrupt vector to EISA interrupt level
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; (APIC INTI input);
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; NOTE: this table must ordered by ascending vector numbers
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; also note that there is no entry for unused INTI13.
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;
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align dword
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public _HalpVectorToINTI
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_HalpVectorToINTI label word
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VECTOR_MAP_ENTRY NMI_VECTOR, 0FFFFh
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VECTOR_MAP_ENTRY (1+MAX_NODES)*100h-1, 0FFFFh ; End of Table
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;
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; _HalpVectorToIRQL maps interrupt vector to NT IRQLs
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; NOTE: this table must ordered by ascending vector numbers
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;
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VECTORTOIRQL_ENTRY macro idt_entry, irql
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current_entry = $ - _HalpVectorToIRQL
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priority_number = (idt_entry/16)
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entry_count = priority_number - current_entry
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REPT entry_count
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db 0FFh
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ENDM
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db irql
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endm
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align dword
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public _HalpVectorToIRQL
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_HalpVectorToIRQL label byte
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VECTORTOIRQL_ENTRY ZERO_VECTOR, 0 ; placeholder
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VECTORTOIRQL_ENTRY APC_VECTOR, APC_LEVEL
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VECTORTOIRQL_ENTRY DPC_VECTOR, DISPATCH_LEVEL
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VECTORTOIRQL_ENTRY APIC_GENERIC_VECTOR, PROFILE_LEVEL
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VECTORTOIRQL_ENTRY APIC_CLOCK_VECTOR, CLOCK1_LEVEL
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VECTORTOIRQL_ENTRY APIC_IPI_VECTOR, IPI_LEVEL
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VECTORTOIRQL_ENTRY POWERFAIL_VECTOR, POWER_LEVEL
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_DATA ENDS
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page ,132
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subttl "Raise Irql"
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_TEXT SEGMENT DWORD PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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;++
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;
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; KIRQL
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; FASTCALL
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; KfRaiseIrql (
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; IN KIRQL NewIrql
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; )
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;
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; Routine Description:
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;
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; This routine is used to raise IRQL to the specified value.
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; The APIC TPR is used to block all lower-priority HW interrupts.
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;
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; Arguments:
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;
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; (cl) = NewIrql - the new irql to be raised to
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;
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;
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; Return Value:
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;
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; OldIrql - the addr of a variable which old irql should be stored
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;
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;--
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cPublicFastCall KfRaiseIrql,1
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cPublicFpo 0,0
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movzx edx, cl ; (edx) = New Irql
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movzx ecx, byte ptr _HalpIRQLtoTPR[edx] ; get TPR value for IRQL
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mov eax, dword ptr APIC[LU_TPR] ; (eax) = Old Priority
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mov dword ptr APIC[LU_TPR], ecx ; Write New Priority to the TPR
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;
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; get IRQL for Old Priority, and return it
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;
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shr eax, 4
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movzx eax, _HalpVectorToIRQL[eax] ; (al) = OldIrql
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fstRET KfRaiseIrql
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fstENDP KfRaiseIrql
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;++
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;
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; VOID
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; KIRQL
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; KeRaiseIrqlToDpcLevel (
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; )
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;
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; Routine Description:
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;
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; This routine is used to raise IRQL to DPC level.
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; The APIC TPR is used to block all lower-priority HW interrupts.
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;
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; Arguments:
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;
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; Return Value:
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;
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; OldIrql - the addr of a variable which old irql should be stored
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;
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;--
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cPublicProc _KeRaiseIrqlToDpcLevel,0
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cPublicFpo 0, 0
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mov edx, dword ptr APIC[LU_TPR] ; (ecx) = Old Priority
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mov dword ptr APIC[LU_TPR], DPC_VECTOR ; Set New Priority
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shr edx, 4
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movzx eax, _HalpVectorToIRQL[edx] ; (al) = OldIrql
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stdRET _KeRaiseIrqlToDpcLevel
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stdENDP _KeRaiseIrqlToDpcLevel
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;++
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;
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; VOID
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; KIRQL
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; KeRaiseIrqlToSyncLevel (
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; )
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;
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; Routine Description:
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;
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; This routine is used to raise IRQL to SYNC level.
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; The APIC TPR is used to block all lower-priority HW interrupts.
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;
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; Arguments:
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;
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; Return Value:
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;
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; OldIrql - the addr of a variable which old irql should be stored
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;
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;--
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cPublicProc _KeRaiseIrqlToSynchLevel,0
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cPublicFpo 0, 0
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mov edx, dword ptr APIC[LU_TPR] ; (ecx) = Old Priority
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mov dword ptr APIC[LU_TPR], APIC_SYNCH_VECTOR ; Write New Priority
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shr edx, 4
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movzx eax, _HalpVectorToIRQL[edx] ; (al) = OldIrql
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stdRET _KeRaiseIrqlToSynchLevel
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stdENDP _KeRaiseIrqlToSynchLevel
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page ,132
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subttl "Lower irql"
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;++
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;
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; VOID
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; FASTCALL
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; KfLowerIrql (
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; IN KIRQL NewIrql
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; )
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;
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; Routine Description:
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;
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; This routine is used to lower IRQL to the specified value.
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; The IRQL and PIRQL will be updated accordingly.
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;
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; Arguments:
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;
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; (cl) = NewIrql - the new irql to be set.
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;
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; Return Value:
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;
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; None.
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;
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;--
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; equates for accessing arguments
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;
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cPublicFastCall KfLowerIrql ,1
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cPublicFpo 0,0
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xor eax, eax
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mov al, cl ; get new irql value
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if DBG
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;
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; Make sure we are not lowering to ABOVE current level
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;
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mov ecx, dword ptr APIC[LU_TPR] ; (ebx) = Old Priority
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shr ecx, 4
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movzx ecx, _HalpVectorToIRQL[ecx] ; get IRQL for Old Priority
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cmp al, cl
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jbe short KliDbg
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push ecx ; new irql for debugging
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push eax ; old irql for debugging
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stdCall _KeBugCheck, <IRQL_NOT_LESS_OR_EQUAL>
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KliDbg:
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endif
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xor ecx, ecx ; Avoid a partial stall
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mov cl, _HalpIRQLtoTPR[eax] ; get TPR value corresponding to IRQL
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mov dword ptr APIC[LU_TPR], ecx
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;
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; We have to ensure that the requested priority is set before
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; we return. The caller is counting on it.
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;
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mov eax, dword ptr APIC[LU_TPR]
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if DBG
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cmp ecx, eax ; Verify IRQL read back is same as
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je short @f ; set value
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int 3
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@@:
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endif
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fstRET KfLowerIrql
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fstENDP KfLowerIrql
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page ,132
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subttl "Get current irql"
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;++
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;
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; KIRQL
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; KeGetCurrentIrql (VOID)
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;
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; Routine Description:
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;
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; This routine returns to current IRQL.
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;
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; Arguments:
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;
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; None.
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;
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; Return Value:
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;
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; The current IRQL.
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;
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;--
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cPublicProc _KeGetCurrentIrql ,0
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mov eax, dword ptr APIC[LU_TPR] ; (eax) = Old Priority
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shr eax, 4
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movzx eax, _HalpVectorToIRQL[eax] ; get IRQL for Old Priority
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stdRET _KeGetCurrentIrql
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stdENDP _KeGetCurrentIrql
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;++
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;
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; KIRQL
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; HalpDisableAllInterrupts (VOID)
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;
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; Routine Description:
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;
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; This routine is called during a system crash. The hal needs all
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; interrupts disabled.
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;
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; Arguments:
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;
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; None.
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;
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; Return Value:
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||
|
|
;
|
||
|
|
; Old IRQL value.
|
||
|
|
;
|
||
|
|
;--
|
||
|
|
|
||
|
|
cPublicProc _HalpDisableAllInterrupts,0
|
||
|
|
|
||
|
|
;
|
||
|
|
; Raising to HIGH_LEVEL
|
||
|
|
;
|
||
|
|
|
||
|
|
mov ecx, HIGH_LEVEL
|
||
|
|
fstCall KfRaiseIrql
|
||
|
|
stdRET _HalpDisableAllInterrupts
|
||
|
|
|
||
|
|
stdENDP _HalpDisableAllInterrupts
|
||
|
|
|
||
|
|
;++
|
||
|
|
;
|
||
|
|
; VOID
|
||
|
|
; HalpReenableInterrupts (
|
||
|
|
; IN KIRQL Irql
|
||
|
|
; )
|
||
|
|
;
|
||
|
|
; Routine Description:
|
||
|
|
;
|
||
|
|
; Restores irql level.
|
||
|
|
;
|
||
|
|
; Arguments:
|
||
|
|
;
|
||
|
|
; Irql - Irql state to restore to.
|
||
|
|
;
|
||
|
|
; Return Value:
|
||
|
|
;
|
||
|
|
; None
|
||
|
|
;
|
||
|
|
;--
|
||
|
|
|
||
|
|
HriNewIrql equ [esp + 4]
|
||
|
|
|
||
|
|
cPublicProc _HalpReenableInterrupts,1
|
||
|
|
cPublicFpo 1, 0
|
||
|
|
|
||
|
|
movzx ecx, byte ptr HriNewIrql
|
||
|
|
fstCall KfLowerIrql
|
||
|
|
|
||
|
|
stdRET _HalpReenableInterrupts
|
||
|
|
|
||
|
|
stdENDP _HalpReenableInterrupts
|
||
|
|
|
||
|
|
_TEXT ends
|
||
|
|
|
||
|
|
PAGELK SEGMENT DWORD PUBLIC 'CODE'
|
||
|
|
ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
|
||
|
|
|
||
|
|
;
|
||
|
|
; PIC initialization command strings - first word is port to write to,
|
||
|
|
; followed by bytes of Initialization Control Words (ICWs) and Operation
|
||
|
|
; Control Words (OCWs). Last string is zero-terminated.
|
||
|
|
;
|
||
|
|
|
||
|
|
PICsInitializationString label byte
|
||
|
|
;
|
||
|
|
; Master PIC initialization commands
|
||
|
|
;
|
||
|
|
dw PIC1_PORT0
|
||
|
|
db ICW1_ICW + ICW1_EDGE_TRIG + ICW1_INTERVAL8 + \
|
||
|
|
ICW1_CASCADE + ICW1_ICW4_NEEDED
|
||
|
|
db PIC1_BASE
|
||
|
|
db 1 SHL PIC_SLAVE_IRQ
|
||
|
|
db ICW4_NOT_SPEC_FULLY_NESTED + \
|
||
|
|
ICW4_NON_BUF_MODE + \
|
||
|
|
ICW4_NORM_EOI + \
|
||
|
|
ICW4_8086_MODE
|
||
|
|
PIC1InitMask db 0FFh ; OCW1 - mask all inputs
|
||
|
|
;
|
||
|
|
; Slave PIC initialization commands
|
||
|
|
;
|
||
|
|
dw PIC2_PORT0
|
||
|
|
db ICW1_ICW + ICW1_EDGE_TRIG + ICW1_INTERVAL8 + \
|
||
|
|
ICW1_CASCADE + ICW1_ICW4_NEEDED
|
||
|
|
db PIC2_BASE
|
||
|
|
db PIC_SLAVE_IRQ
|
||
|
|
db ICW4_NOT_SPEC_FULLY_NESTED + \
|
||
|
|
ICW4_NON_BUF_MODE + \
|
||
|
|
ICW4_NORM_EOI + \
|
||
|
|
ICW4_8086_MODE
|
||
|
|
PIC2InitMask db 0FFh ; OCW1 - mask all inputs
|
||
|
|
dw 0 ; end of string
|
||
|
|
|
||
|
|
|
||
|
|
page ,132
|
||
|
|
subttl "Interrupt Controller Chip Initialization"
|
||
|
|
;++
|
||
|
|
;
|
||
|
|
; VOID
|
||
|
|
; HalpInitializePICs (
|
||
|
|
; BOOLEAN EnableInterrupts
|
||
|
|
; )
|
||
|
|
;
|
||
|
|
; Routine Description:
|
||
|
|
;
|
||
|
|
; This routine initializes the interrupt structures for the 8259A PIC.
|
||
|
|
;
|
||
|
|
; Context:
|
||
|
|
;
|
||
|
|
; This procedure is executed by CPU 0 during Phase 0 initialization.
|
||
|
|
;
|
||
|
|
; Arguments:
|
||
|
|
;
|
||
|
|
; None
|
||
|
|
;
|
||
|
|
; Return Value:
|
||
|
|
;
|
||
|
|
; None.
|
||
|
|
;
|
||
|
|
;--
|
||
|
|
EnableInterrupts equ [esp + 0ch]
|
||
|
|
|
||
|
|
cPublicProc _HalpInitializePICs ,1
|
||
|
|
|
||
|
|
push esi ; save caller's esi
|
||
|
|
pushfd
|
||
|
|
cli ; disable interrupt
|
||
|
|
|
||
|
|
lea esi, PICsInitializationString
|
||
|
|
lodsw ; (AX) = PIC port 0 address
|
||
|
|
Hip10: movzx edx, ax
|
||
|
|
outsb ; output ICW1
|
||
|
|
IODelay
|
||
|
|
inc edx ; (DX) = PIC port 1 address
|
||
|
|
outsb ; output ICW2
|
||
|
|
IODelay
|
||
|
|
outsb ; output ICW3
|
||
|
|
IODelay
|
||
|
|
outsb ; output ICW4
|
||
|
|
IODelay
|
||
|
|
outsb ; output OCW1 (mask register)
|
||
|
|
IODelay
|
||
|
|
lodsw
|
||
|
|
cmp ax, 0 ; end of init string?
|
||
|
|
jne short Hip10 ; go init next PIC
|
||
|
|
|
||
|
|
mov al, PIC2InitMask ; save the initial mask in
|
||
|
|
shl ax, 8 ; mask in global variable
|
||
|
|
mov al, PIC1InitMask
|
||
|
|
mov _HalpGlobal8259Mask, ax
|
||
|
|
|
||
|
|
mov al, EnableInterrupts
|
||
|
|
.if (al != 0)
|
||
|
|
or [esp], EFLAGS_INTERRUPT_MASK ; enable interrupts
|
||
|
|
.endif
|
||
|
|
popfd
|
||
|
|
pop esi ; restore caller's esi
|
||
|
|
stdRET _HalpInitializePICs
|
||
|
|
stdENDP _HalpInitializePICs
|
||
|
|
|
||
|
|
PAGELK ends
|
||
|
|
end
|