687 lines
16 KiB
NASM
687 lines
16 KiB
NASM
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title "Interval Clock Interrupt"
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;++
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;
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; Copyright (c) 1989 Microsoft Corporation
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;
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; Module Name:
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;
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; mpprofile.asm
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;
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; Abstract:
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;
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; This module implements the code necessary to initialize,
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; field and process the profile interrupt.
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;
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; Author:
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;
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; Shie-Lin Tzong (shielint) 12-Jan-1990
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;
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; Environment:
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;
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; Kernel mode only.
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;
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; Revision History:
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;
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; bryanwi 20-Sep-90
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;
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;--
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.586p
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.xlist
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include hal386.inc
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include i386\ix8259.inc
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include i386\ixcmos.inc
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include callconv.inc ; calling convention macros
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include i386\kimacro.inc
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include mac386.inc
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include apic.inc
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include ntapic.inc
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include i386\mp8254.inc
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.list
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EXTRNP _DbgBreakPoint,0,IMPORT
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EXTRNP _KeProfileInterrupt,1,IMPORT
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EXTRNP Kei386EoiHelper,0,IMPORT
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EXTRNP _HalEndSystemInterrupt,2
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EXTRNP _HalBeginSystemInterrupt,3
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EXTRNP _HalpAcquireSystemHardwareSpinLock,0
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EXTRNP _HalpReleaseSystemHardwareSpinLock,0
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EXTRNP _HalpAcquireCmosSpinLock ,0
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EXTRNP _HalpReleaseCmosSpinLock ,0
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extrn _HalpUse8254:BYTE
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;
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; APIC Timer Constants
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;
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APIC_TIMER_DISABLED equ (INTERRUPT_MASKED OR PERIODIC_TIMER OR APIC_PROFILE_VECTOR)
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APIC_TIMER_ENABLED equ (PERIODIC_TIMER OR APIC_PROFILE_VECTOR)
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;
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; number of 100ns intervals in one second
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;
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Num100nsIntervalsPerSec equ 10000000
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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ALIGN dword
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public _HalpProfileRunning, _HalpPerfInterruptHandler
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_HalpProfileRunning dd 0
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_HalpPerfInterruptHandler dd 0
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_DATA ends
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_TEXT SEGMENT DWORD PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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;++
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;
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; HalStartProfileInterrupt(
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; IN ULONG Reserved
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; );
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;
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; Routine Description:
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;
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; What we do here is set the interrupt rate to the value that's been set
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; by the KeSetProfileInterval routine. Then enable the APIC Timer interrupt.
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;
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; This function gets called on every processor so the hal can enable
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; a profile interrupt on each processor.
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;
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;--
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cPublicProc _HalStartProfileInterrupt ,1
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;
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; Set the interrupt rate to what is actually needed.
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;
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mov eax, PCR[PcHal.ProfileCountDown]
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mov dword ptr APIC[LU_INITIAL_COUNT], eax
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mov _HalpProfileRunning, 1 ; Indicate profiling
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;
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; Set the Local APIC Timer to interrupt Periodically at APIC_PROFILE_VECTOR
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;
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mov dword ptr APIC[LU_TIMER_VECTOR], APIC_TIMER_ENABLED
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stdRET _HalStartProfileInterrupt
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stdENDP _HalStartProfileInterrupt
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;++
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;
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; HalStopProfileInterrupt(
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; IN ULONG Reserved
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; );
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;
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; Routine Description:
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;
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;--
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cPublicProc _HalStopProfileInterrupt ,1
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;
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; Turn off profiling
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;
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mov _HalpProfileRunning, 0 ; Indicate profiling is off
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mov dword ptr APIC[LU_TIMER_VECTOR], APIC_TIMER_DISABLED
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stdRET _HalStopProfileInterrupt
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stdENDP _HalStopProfileInterrupt
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;++
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; ULONG
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; HalSetProfileInterval (
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; ULONG Interval
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; );
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;
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; Routine Description:
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;
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; This procedure sets the interrupt rate (and thus the sampling
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; interval) for the profiling interrupt.
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;
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; Arguments:
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;
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; (TOS+4) - Interval in 100ns unit.
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; (MINIMUM is 1221 or 122.1 uS) see ke\profobj.c
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;
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; Return Value:
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;
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; Interval actually used
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;
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;--
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cPublicProc _HalSetProfileInterval ,1
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mov ecx, [esp+4] ; ecx = interval in 100ns unit
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and ecx, 7FFFFFFFh ; Remove sign bit.
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;
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; The only possible error is if we will cause a divide overflow
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; this can happen only if the (frequency * request count) is
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; greater than 2^32* Num100nsIntervalsPerSec.
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;
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; To protect against that we just ensure that the request count
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; is less than (or equal to) Num100nsIntervalsPerSec
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;
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cmp ecx, Num100nsIntervalsPerSec
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jle @f
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mov ecx, Num100nsIntervalsPerSec
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@@:
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;
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; Save the interval we're using to return
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;
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push ecx
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;
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; Compute the countdown value
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;
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; let
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; R == caller's requested 100ns interval count
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; F == APIC Counter Freguency (hz)
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; N == Number of 100ns Intervals per sec
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;
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; then
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; count = (R*F)/N
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;
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; Get the previously computed APIC counter Freq
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; for this processor
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;
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mov eax, PCR[PcHal.ApicClockFreqHz]
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;
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; eax <= F and ecx <= R
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;
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;
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; Compute (request count) * (ApicClockFreqHz) == (R*F)
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;
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xor edx, edx
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mul ecx
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;
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; edx:eax contains 64Bits of (R*F)
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;
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mov ecx, Num100nsIntervalsPerSec
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div ecx
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;
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; Compute (R*F) / Num100nsIntervalsPerSec == (R*F)/N
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;
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mov PCR[PcHal.ProfileCountDown], eax ; Save the Computed Count Down
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mov edx, dword ptr APIC[LU_CURRENT_COUNT]
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;
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; Set the interrupt rate in the chip.
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;
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mov dword ptr APIC[LU_INITIAL_COUNT], eax
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pop eax ; Return Actual Interval Used
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stdRET _HalSetProfileInterval
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stdENDP _HalSetProfileInterval
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page ,132
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subttl "System Profile Interrupt"
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;++
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;
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; Routine Description:
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;
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; This routine is entered as the result of a profile interrupt.
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; Its function is to dismiss the interrupt, raise system Irql to
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; HAL_PROFILE_LEVEL and transfer control to
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; the standard system routine to process any active profiles.
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;
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; Arguments:
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;
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; None
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; Interrupt is disabled
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;
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; Return Value:
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;
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; Does not return, jumps directly to KeProfileInterrupt, which returns
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;
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; Sets Irql = HAL_PROFILE_LEVEL and dismisses the interrupt
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;
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;--
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ENTER_DR_ASSIST Hpi_a, Hpi_t
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cPublicProc _HalpProfileInterrupt ,0
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;
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; Save machine state in trap frame
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;
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ENTER_INTERRUPT Hpi_a, Hpi_t
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;
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; (esp) - base of trap frame
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;
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push APIC_PROFILE_VECTOR
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sub esp, 4 ; allocate space to save OldIrql
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stdCall _HalBeginSystemInterrupt, <HAL_PROFILE_LEVEL,APIC_PROFILE_VECTOR,esp>
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cmp _HalpProfileRunning, 0 ; Profiling?
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je @f ; if not just exit
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stdCall _KeProfileInterrupt,<ebp> ; (ebp) = TrapFrame address
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@@:
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INTERRUPT_EXIT
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stdENDP _HalpProfileInterrupt
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subttl "System Perf Interrupt"
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;++
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;
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; Routine Description:
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;
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; This routine is entered as the result of a perf interrupt.
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; Its function is to dismiss the interrupt, raise system Irql to
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; HAL_PROFILE_LEVEL and transfer control to
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; the standard system routine to process any active profiles.
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;
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; Arguments:
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;
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; None
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; Interrupt is disabled
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;
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; Return Value:
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;
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; Does not return, jumps directly to KeProfileInterrupt, which returns
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;
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; Sets Irql = HAL_PROFILE_LEVEL and dismisses the interrupt
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;
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;--
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ENTER_DR_ASSIST Hpf_a, Hpf_t
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cPublicProc _HalpPerfInterrupt ,0
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;
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; Save machine state in trap frame
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;
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ENTER_INTERRUPT Hpf_a, Hpf_t
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;
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; (esp) - base of trap frame
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;
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push APIC_PERF_VECTOR
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sub esp, 4 ; allocate space to save OldIrql
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stdCall _HalBeginSystemInterrupt, <HAL_PROFILE_LEVEL,APIC_PERF_VECTOR,esp>
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;
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; Invoke perf interrupt handler
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;
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mov ecx, ebp ; param1 = trap frame
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mov eax, _HalpPerfInterruptHandler
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or eax, eax
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jz short hpf20
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call eax
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hpf10:
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;
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; Starting with the Willamette processor, the perf interrupt gets masked on
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; interrupting. Needs to clear the mask before leaving the interrupt handler.
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; Do this regardless of whether a valid interrupt handler exists or not.
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;
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and dword ptr APIC[LU_PERF_VECTOR], (NOT INTERRUPT_MASKED)
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INTERRUPT_EXIT
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hpf20:
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if DBG
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int 3
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endif
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jmp short hpf10
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stdENDP _HalpPerfInterrupt
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_TEXT ends
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PAGELK SEGMENT PARA PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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;++
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;
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; VOID
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; HalCalibratePerformanceCounter (
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; IN LONG volatile *Number,
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; IN ULONGLONG NewCount
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; )
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;
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; /*++
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;
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; Routine Description:
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;
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; This routine calibrates the performance counter value for a
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; multiprocessor system. The calibration can be done by zeroing
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; the current performance counter, or by calculating a per-processor
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; skewing between each processors counter.
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;
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; Arguments:
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;
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; Number - Supplies a pointer to count of the number of processors in
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; the configuration.
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;
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; NewCount - Supplies the value to synchronize the counter too
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;
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; Return Value:
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;
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; None.
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;--
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NewCountLow equ [esp + 24]
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NewCountHigh equ [esp + 28]
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ifdef MMTIMER
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cPublicProc _HalpAcpiTimerCalibratePerfCount,3
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else
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cPublicProc _HalCalibratePerformanceCounter,3
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endif
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cPublicFpo 3,0
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push esi
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push edi
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push ebx
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mov esi, [esp+16] ; pointer to Number
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pushfd ; save previous interrupt state
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cli ; disable interrupts
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cPublicFpo 3,4
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xor eax, eax
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lock dec dword ptr [esi] ; count down
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@@: YIELD
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cmp dword ptr [esi], 0 ; wait for all processors to signal
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jnz short @b
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cpuid ; fence
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mov ecx, MsrTSC ; MSR of time stamp counter
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mov eax, NewCountLow
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mov edx, NewCountHigh
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mov PCR[PcHal.PerfCounterLow], eax
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mov PCR[PcHal.PerfCounterHigh], edx
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||
|
|
xor eax,eax
|
||
|
|
xor edx,edx
|
||
|
|
|
||
|
|
wrmsr ; zero the time stamp counter
|
||
|
|
|
||
|
|
popfd ; restore interrupt flag
|
||
|
|
pop ebx
|
||
|
|
pop edi
|
||
|
|
pop esi
|
||
|
|
ifdef MMTIMER
|
||
|
|
stdRET _HalpAcpiTimerCalibratePerfCount
|
||
|
|
|
||
|
|
stdENDP _HalpAcpiTimerCalibratePerfCount
|
||
|
|
else
|
||
|
|
stdRET _HalCalibratePerformanceCounter
|
||
|
|
|
||
|
|
stdENDP _HalCalibratePerformanceCounter
|
||
|
|
endif
|
||
|
|
|
||
|
|
PAGELK ends
|
||
|
|
|
||
|
|
INIT SEGMENT PARA PUBLIC 'CODE'
|
||
|
|
ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
|
||
|
|
|
||
|
|
page ,132
|
||
|
|
subttl "Scale Apic Timer"
|
||
|
|
;++
|
||
|
|
;
|
||
|
|
; VOID
|
||
|
|
; HalpScaleTimers (
|
||
|
|
; IN VOID
|
||
|
|
; )
|
||
|
|
;
|
||
|
|
; Routine Description:
|
||
|
|
;
|
||
|
|
; Determines the frequency of the APIC timer. This routine is run
|
||
|
|
; during initialization
|
||
|
|
;
|
||
|
|
;
|
||
|
|
;--
|
||
|
|
|
||
|
|
cPublicProc _HalpScaleTimers ,0
|
||
|
|
push ebx
|
||
|
|
push esi
|
||
|
|
push edi
|
||
|
|
|
||
|
|
;
|
||
|
|
; Don't let anyone in until we've finished here
|
||
|
|
;
|
||
|
|
stdCall _HalpAcquireCmosSpinLock
|
||
|
|
|
||
|
|
;
|
||
|
|
; Protect us from interrupts
|
||
|
|
;
|
||
|
|
pushfd
|
||
|
|
cli
|
||
|
|
|
||
|
|
;
|
||
|
|
; First set up the Local Apic Counter
|
||
|
|
;
|
||
|
|
; The following code assumes the CPU clock will never
|
||
|
|
; exceed 4Ghz. For the short term this is probably OK
|
||
|
|
;
|
||
|
|
|
||
|
|
;
|
||
|
|
; Configure the APIC timer
|
||
|
|
;
|
||
|
|
|
||
|
|
APIC_TIMER_DISABLED equ (INTERRUPT_MASKED OR PERIODIC_TIMER OR APIC_PROFILE_VECTOR)
|
||
|
|
TIMER_ROUNDING equ 10000
|
||
|
|
|
||
|
|
|
||
|
|
mov dword ptr APIC[LU_TIMER_VECTOR], APIC_TIMER_DISABLED
|
||
|
|
mov dword ptr APIC[LU_DIVIDER_CONFIG], LU_DIVIDE_BY_1
|
||
|
|
|
||
|
|
;
|
||
|
|
; We're going to do this twice & take the second results
|
||
|
|
;
|
||
|
|
mov esi, 2
|
||
|
|
hst10:
|
||
|
|
|
||
|
|
;
|
||
|
|
; Make sure the write has occurred
|
||
|
|
;
|
||
|
|
mov eax, dword ptr APIC[LU_DIVIDER_CONFIG]
|
||
|
|
|
||
|
|
;
|
||
|
|
; We don't care what the actual time is we are only interested
|
||
|
|
; in seeing the UIP transition. We are garenteed a 1 sec interval
|
||
|
|
; if we wait for the UIP bit to complete an entire cycle.
|
||
|
|
|
||
|
|
;
|
||
|
|
; We also don't much care which direction the transition we use is
|
||
|
|
; as long as we wait for the same transition to read the APIC clock.
|
||
|
|
; Just because it is most likely that when we begin the UIP bit will
|
||
|
|
; be clear, we'll use the transition from !UIP to UIP.
|
||
|
|
;
|
||
|
|
|
||
|
|
;
|
||
|
|
; Wait for the UIP bit to be cleared, this is our starting state
|
||
|
|
;
|
||
|
|
|
||
|
|
@@:
|
||
|
|
mov al, 0Ah ; Specify register A
|
||
|
|
CMOS_READ ; (al) = CMOS register A
|
||
|
|
test al, CMOS_STATUS_BUSY ; Is time update in progress?
|
||
|
|
jnz short @b ; if z, no, wait some more
|
||
|
|
|
||
|
|
;
|
||
|
|
; Wait for the UIP bit to get set
|
||
|
|
;
|
||
|
|
|
||
|
|
@@:
|
||
|
|
mov al, 0Ah ; Specify register A
|
||
|
|
CMOS_READ ; (al) = CMOS register A
|
||
|
|
test al, CMOS_STATUS_BUSY ; Is time update in progress?
|
||
|
|
jz short @b ; if z, no, wait some more
|
||
|
|
|
||
|
|
;
|
||
|
|
; At this point we found the UIP bit set, now set the initial
|
||
|
|
; count. Once we write this register its value is copied to the
|
||
|
|
; current count register and countdown starts or continues from
|
||
|
|
; there
|
||
|
|
;
|
||
|
|
|
||
|
|
xor eax, eax
|
||
|
|
mov PCR[PcHal.PerfCounterLow], eax
|
||
|
|
mov PCR[PcHal.PerfCounterHigh], eax
|
||
|
|
|
||
|
|
cpuid ; fence
|
||
|
|
|
||
|
|
mov ecx, MsrTSC ; MSR of RDTSC
|
||
|
|
xor edx, edx
|
||
|
|
mov eax, edx
|
||
|
|
mov dword ptr APIC[LU_INITIAL_COUNT], 0FFFFFFFFH
|
||
|
|
wrmsr ; Clear TSC count
|
||
|
|
|
||
|
|
;
|
||
|
|
; Wait for the UIP bit to be cleared again
|
||
|
|
;
|
||
|
|
|
||
|
|
@@:
|
||
|
|
mov al, 0Ah ; Specify register A
|
||
|
|
CMOS_READ ; (al) = CMOS register A
|
||
|
|
test al, CMOS_STATUS_BUSY ; Is time update in progress?
|
||
|
|
jnz short @b ; if z, no, wait some more
|
||
|
|
|
||
|
|
;
|
||
|
|
; Wait for the UIP bit to get set
|
||
|
|
;
|
||
|
|
|
||
|
|
@@:
|
||
|
|
mov al, 0Ah ; Specify register A
|
||
|
|
CMOS_READ ; (al) = CMOS register A
|
||
|
|
test al, CMOS_STATUS_BUSY ; Is time update in progress?
|
||
|
|
jz short @b ; if z, no, wait some more
|
||
|
|
|
||
|
|
;
|
||
|
|
; The cycle is complete, we found the UIP bit set. Now read
|
||
|
|
; the counters and compute the frequency. The frequency is
|
||
|
|
; just the ticks counted which is the initial value minus
|
||
|
|
; the current value.
|
||
|
|
;
|
||
|
|
|
||
|
|
xor eax, eax
|
||
|
|
cpuid ; fence
|
||
|
|
|
||
|
|
rdtsc
|
||
|
|
mov ecx, dword ptr APIC[LU_CURRENT_COUNT]
|
||
|
|
|
||
|
|
dec esi ; if this is the first time
|
||
|
|
jnz hst10 ; around, go loop
|
||
|
|
|
||
|
|
mov PCR[PcHal.TSCHz], eax
|
||
|
|
|
||
|
|
mov eax, 0FFFFFFFFH
|
||
|
|
sub eax, ecx
|
||
|
|
|
||
|
|
;
|
||
|
|
; Round the Apic Timer Freq
|
||
|
|
;
|
||
|
|
|
||
|
|
xor edx, edx ; (edx:eax) = dividend
|
||
|
|
|
||
|
|
mov ecx, TIMER_ROUNDING
|
||
|
|
div ecx ; now edx has remainder
|
||
|
|
|
||
|
|
cmp edx, TIMER_ROUNDING / 2
|
||
|
|
jle @f ; if less don't round
|
||
|
|
inc eax ; else round up
|
||
|
|
@@:
|
||
|
|
|
||
|
|
;
|
||
|
|
; Multiply by the Rounding factor to get the rounded Freq
|
||
|
|
;
|
||
|
|
mov ecx, TIMER_ROUNDING
|
||
|
|
xor edx, edx
|
||
|
|
mul ecx
|
||
|
|
|
||
|
|
mov dword ptr PCR[PcHal.ApicClockFreqHz], eax
|
||
|
|
|
||
|
|
;
|
||
|
|
; Round TSC freq
|
||
|
|
;
|
||
|
|
|
||
|
|
mov eax, PCR[PcHal.TSCHz]
|
||
|
|
xor edx, edx
|
||
|
|
|
||
|
|
mov ecx, TIMER_ROUNDING
|
||
|
|
div ecx ; now edx has remainder
|
||
|
|
|
||
|
|
cmp edx, TIMER_ROUNDING / 2
|
||
|
|
jle @f ; if less don't round
|
||
|
|
inc eax ; else round up
|
||
|
|
@@:
|
||
|
|
mov ecx, TIMER_ROUNDING
|
||
|
|
xor edx, edx
|
||
|
|
mul ecx
|
||
|
|
|
||
|
|
mov PCR[PcHal.TSCHz], eax
|
||
|
|
|
||
|
|
;
|
||
|
|
; Convert TSC to microseconds
|
||
|
|
;
|
||
|
|
|
||
|
|
xor edx, edx
|
||
|
|
mov ecx, 1000000
|
||
|
|
div ecx ; Convert to microseconds
|
||
|
|
|
||
|
|
xor ecx, ecx
|
||
|
|
cmp ecx, edx ; any remainder?
|
||
|
|
adc eax, ecx ; Yes, add one
|
||
|
|
|
||
|
|
mov PCR[PcStallScaleFactor], eax
|
||
|
|
|
||
|
|
stdCall _HalpReleaseCmosSpinLock
|
||
|
|
|
||
|
|
;
|
||
|
|
; Return Value is the timer frequency
|
||
|
|
;
|
||
|
|
|
||
|
|
mov eax, dword ptr PCR[PcHal.ApicClockFreqHz]
|
||
|
|
mov PCR[PcHal.ProfileCountDown], eax
|
||
|
|
|
||
|
|
;
|
||
|
|
; Set the interrupt rate in the chip.
|
||
|
|
;
|
||
|
|
|
||
|
|
mov dword ptr APIC[LU_INITIAL_COUNT], eax
|
||
|
|
|
||
|
|
popfd
|
||
|
|
|
||
|
|
pop edi
|
||
|
|
pop esi
|
||
|
|
pop ebx
|
||
|
|
|
||
|
|
stdRET _HalpScaleTimers
|
||
|
|
stdENDP _HalpScaleTimers
|
||
|
|
|
||
|
|
|
||
|
|
INIT ends
|
||
|
|
|
||
|
|
end
|