194 lines
5.8 KiB
C
194 lines
5.8 KiB
C
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/*++ BUILD Version: 0001 // Increment this if a change has global effects
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Copyright (c) 1993 ACER America Corporation
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Module Name:
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acer.h
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Abstract:
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This header file defines the unique interfaces, defines and structures
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for the ACER product line
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Revision History:
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1.0b - plm initial release
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1.1b - acer.c: halpacereisa: handle scrabled eisa data gracefully.
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--*/
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#define ACER_HAL_VERSION_NUMBER "Acer HAL Version 1.1b for October Windows NT Beta.\n"
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/* ACER Special I/O Port defintions
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* I/O Port Address 0xcc4h
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* |
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* 0: cpu0 & cpu1
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* c: cpu2 & cpu3
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*
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* bits < 7 6 5 4 3 2 1 0 > (WRITE-ONLY)
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* 0 0 | 0 0 | 0 |
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* | | BIOS Shadow Control
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* | | 0: ROM BIOS
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* | | 1: RAM BIOS
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* | |
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* | |
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* | Write-Back Cache Control
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* | 0: write-thru ( write-back disabled)
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* | 1: write-back enabled
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* |
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* 15Mb to 16Mb Memory Setup
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* 0: Ram
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* 1: EISA
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*
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*/
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// where do i find the CSR which controls the write-back enabling?
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#define ACER_PORT_CPU01 0xcc4 // write only - setup reg. cpu 0,1
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#define ACER_PORT_CPU23 0xccc4 // write onlY - setup reg. cpu 2,3
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#define WRITE_BALLOC_ON 0x04 // bit<2> - enable write-back cache bit
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#define WRITE_BALLOC_OFF 0x00 // bit<2> - disable write-back cache bit
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/* ACER RT/CMOS contents
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*
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* index 35h bit<1>: 15Mb to 16Mb Memory Setup
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* 0: EISA
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* 1: Ram
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* all other bits RESERVED
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*
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* index 39h bit<0>: BIOS Shadow Control
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* 0: ROM BIOS
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* 1: RAM BIOS
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* all other bits RESERVED
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*
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*/
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// RT/CMOS indexes where special Acer machine config info is kept
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// where is the information kept that tells me if bios shadowing is eabled?
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#define ACER_SHADOW_IDX 0x39 // RT/CMOS index for shadow bios control
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#define RAM_ROM_MASK 0x01 // bit<0>, 0:RAM BIOS 1:ROM BIOS
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// where is the information kept that tells me if 15M-16M is EISA or RAM?
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#define ACER_15M_16M_IDX 0x35 // RT/CMOS index for 15Mb-16Mb mem cntrl
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#define DRAM_EISA_MASK 0x02 // bit<1>, 0:EISA 1:RAM
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// EISA ID base addresses for cpu0
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#define ACER_CPU0_EISA_ID0 0x0c80 /* 1 digit + part of digit 2 */
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#define ACER_CPU0_EISA_ID1 0x0c81 /* rest of digit 2 + digit 3 */
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#define ACER_CPU0_EISA_ID2 0x0c82 /* msw id */
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#define ACER_CPU0_EISA_ID3 0x0c83 /* msw id */
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// ACER EISA ID's
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#define ACER_ID0 0x04 /* acr32xx */
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#define ACER_ID1 0x72
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#define ACER_ID2 0x32
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// ALTOS EISA ID's
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#define ALTOS_ID0 0x04 /* acs32xx */
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#define ALTOS_ID1 0x73
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#define ALTOS_ID2 0x32
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// ICL EISA ID's
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#define ICL_ID0 0x24 /* icl00xx */
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#define ICL_ID1 0x6c
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#define ICL_ID2 0x00
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// EISA IDs of ACER/ALTOS machines which support a write-back secondary cache
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#define ACER_EISA_ID_WB_CPU0 0x61
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// EISA IDs of ICL machine (acer oem) which supports write-back scndry cache
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// NOTE: THESE IDS ARE STILL TBD!!!
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#define ICL_EISA_ID_WB_CPU0 0x61
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// EISA constants
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#define MAX_IRQS_PER_EISABUS 16 // how many irq to search for
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#define MAX_EISA_SLOTS 16 // number of eisa slots
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// magic number for kefindconfigurationentry
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//#define EISA_DATA_OFFSET 24 // offset to data portion of eisa pointer
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// cpu0's i/o address space for cpu1's pic's
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//
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// NOTE: These defines MUST MATCH EXACTLY the equ's found in spirql.asm
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//
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#define CPU1_PIC1_PORT0 0xc024
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#define CPU1_PIC1_PORT1 0xc0a4
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#define CPU1_PIC2_PORT0 0xc025
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#define CPU1_PIC2_PORT1 0xc0a5
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#define CPU0_PIC1_PORT0 0x020
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#define CPU0_PIC1_PORT1 0x0a0
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// cpu0's eisa level/edge register
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#define EISA_LEVEL_EDGE_PIC1 0x04d0
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#define EISA_LEVEL_EDGE_PIC2 0x04d1
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#define SET_TO_EDGE ((UCHAR) 0x0000)
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#define SET_TO_LEVEL ((UCHAR) -1)
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// eisa level/edge register bit which MUST BE edges
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#define EISA_LEVEL_EDGE_PIC1_INIT 0xb8
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#define EISA_LEVEL_EDGE_PIC2_INIT 0xde
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// eisa 8259
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#define READ_IRR 0x0a
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#define READ_ISR 0x0b
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// a safe eisa i/o location that can be read to force any caches
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// to flush any pending i/o writes. This just happens to be
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// the eisa manufacturer i.d. location
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#define EISA_FLUSH_ADDR 0x0c80
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// This define MUST EXACTLY MATCH asm equ located in file spmp.inc
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#define SMP_ACER 3
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#define MAX_ACER_CPUS 4 // maximum number of cpus a acer can hold
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//
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// acer_irq_distribution callback data structure
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//
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typedef struct _ACER_IRQ_DISTRIBUTION {
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BOOLEAN distribte_irqs; // shall i try to distribute irqs across cpus
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// cpu x pics can handle level irqs?
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BOOLEAN px_set_to_level_irqs[ MAX_ACER_CPUS ];
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// number of irqs which have been assigned, used for load balancing
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SHORT px_numb_irqs_assigned[ MAX_ACER_CPUS ];
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// only a certain number of irqs per pic pair can handle level triggerring
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BOOLEAN eisa_level_compatable[ MAX_IRQS_PER_EISABUS ];
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} ACER_IRQ_DISTRIBUTION, *PACER_IRQ_DISTRIBUTION;
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// default number of irq's assinged
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#define ACER_IRQS_ASSIGED_CPU0 1 // stay away from 0 for init case
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#define ACER_IRQS_ASSIGED_CPU1 0
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#define ACER_IRQS_ASSIGED_CPU2 0
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#define ACER_IRQS_ASSIGED_CPU3 0
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// what irqs can be level distriubted?
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#define ACER_DISTRIBUTE_LEVEL_IRQ0 FALSE
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#define ACER_DISTRIBUTE_LEVEL_IRQ1 FALSE
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#define ACER_DISTRIBUTE_LEVEL_IRQ2 FALSE
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#define ACER_DISTRIBUTE_LEVEL_IRQ3 TRUE
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#define ACER_DISTRIBUTE_LEVEL_IRQ4 TRUE
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#define ACER_DISTRIBUTE_LEVEL_IRQ5 TRUE
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#define ACER_DISTRIBUTE_LEVEL_IRQ6 FALSE
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#define ACER_DISTRIBUTE_LEVEL_IRQ7 TRUE
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#define ACER_DISTRIBUTE_LEVEL_IRQ8 FALSE
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#define ACER_DISTRIBUTE_LEVEL_IRQ9 TRUE
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#define ACER_DISTRIBUTE_LEVEL_IRQ10 TRUE
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#define ACER_DISTRIBUTE_LEVEL_IRQ11 TRUE
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#define ACER_DISTRIBUTE_LEVEL_IRQ12 TRUE
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#define ACER_DISTRIBUTE_LEVEL_IRQ13 FALSE
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#define ACER_DISTRIBUTE_LEVEL_IRQ14 TRUE
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#define ACER_DISTRIBUTE_LEVEL_IRQ15 TRUE
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